CAT22C10W-30-TE13

CAT22C10 256-Bit Nonvolatile CMOS Static RAM FEATURES ■ Single 5V Supply ■ Fast RAM Access Times: H GEN FR ALO EE LE ■ Low CMOS Power Consumption: A D F R E ETM –200ns –300ns ■ Infinite EEPROM to RAM Recall ■ CMOS and TTL Compatible I/O ■ Power Up/Down Protection ■ 100,000 Program/Erase Cycles (E2PROM) –Active: 40mA Max. –Standby: 30 µA Max. ■ JEDEC Standard Pinouts: –18-pin DIP –16-pin SOIC ■ 10 Year Data Retention ■ Commercial, Industrial and Automotive Temperature Ranges ■ "Green" Package Options Available DESCRIPTION The CAT22C10 NVRAM is a 256-bit nonvolatile memory organized as 64 words x 4 bits. The high speed Static RAM array is bit for bit backed up by a nonvolatile EEPROM array which allows for easy transfer of data from RAM array to EEPROM (STORE) and from EEPROM to RAM (RECALL). STORE operations are completed in 10ms max. and RECALL operations typically within 1.5µs. The CAT22C10 features unlimited RAM write operations either through external RAM writes or internal recalls from EEPROM. Internal false store protection circuitry prohibits STORE operations when VCC is less than 3.0V. The CAT22C10 is manufactured using Catalyst’s advanced CMOS floating gate technology. It is designed to endure 100,000 program/erase cycles (EEPROM) and has a data retention of 10 years. The device is available in JEDEC approved 18-pin plastic DIP and 16pin SOIC packages. PIN CONFIGURATION DIP Package (P, L) SOIC Package (J, W) A4 A3 A2 A1 A0 CS Vss STORE 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 Vcc A5 I/O4 I/O3 I/O2 I/O1 WE RECALL PIN FUNCTIONS Pin Name A0–A5 I/O0–I/O3 WE CS RECALL STORE VCC VSS NC Function Address Data In/Out Write Enable Chip Select Recall Store +5V Ground No Connect NC A4 A3 A2 A1 A0 CS Vss STORE 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 Vcc NC A5 I/O3 I/O2 I/O1 I/O0 WE RECALL © 2004 by Catalyst Semiconductor, Inc., Patent Pending Characteristics subject to change without notice Doc. No. 1082, Rev. O CAT22C10 BLOCK DIAGRAM EEPROM ARRAY A0 A1 A2 A3 A4 A5 STORE RECALL ROW STATIC RAM STORE SELECT ARRAY RECALL COLUMN SELECT CONTROL LOGIC READ/WRITE CIRCUITS CS WE I/O0 I/O1 I/O2 I/O3 MODE SELECTION(1)(2)(3) Input Mode Standby RAM Read RAM Write (EEPROM→RAM) (EEPROM→RAM) (RAM→EEPROM) (RAM→EEPROM) POWER-UP TIMING(4) Symbol VCCSR Parameter VCC Slew Rate Min. 0.5 Max. 0.005 Units V/ms CS H L L X H X H WE X H L H X H X RECALL H H H L L H H STORE H H H H H L L I/O Output High-Z Output Data Input Data Output High-Z RECALL Output High-Z RECALL Output High-Z STORE Output High-Z STORE Note: (1) RECALL signal has priority over STORE signal when both are applied at the same time. (2) STORE is inhibited when RECALL is active. (3) The store operation is inhibited when VCC is below ≈ 3.0V. (4) This parameter is tested initially and after a design or process change that affects the parameter. Doc. No. 1082, Rev. O 2 CAT22C10 ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias ................. –55°C to +125°C Storage Temperature ....................... –65°C to +150°C Voltage on Any Pin with Respect to Ground(2) .............. -2.0 to +VCC +2.0V VCC with Respect to Ground ................ -2.0V to +7.0V Package Power Dissipation Capability (Ta = 25°C) ................................... 1.0W Lead Soldering Temperature (10 secs) ............ 300°C Output Short Circuit Current(3) ........................ 100 mA RELIABILITY CHARACTERISTICS Symbol NEND(1) TDR(1) VZAP(1) ILTH(1)(4) Parameter Endurance Data Retention ESD Susceptibility Latch-Up Min. 100,000 10 2000 100 Max. *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Units Cycles/Byte Years Volts mA Reference Test Method MIL-STD-883, Test Method 1033 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 3015 JEDEC Standard 17 D.C. OPERATING CHARACTERISTICS VCC = +5V ±10%, unless otherwise specified. Limits Symbol ICC Parameter Current Consumption (Operating) Current Consumption (Standby) Input Current Output Leakage Current High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage RAM Data Holding Voltage 1.5 2 0 2.4 0.4 5.5 Min. Typ. Max. 40 Unit mA Conditions All Inputs = 5.5V TA = 0°C All I/O’s Open CS = VCC All I/O’s Open 0 ≤ VIN ≤ 5.5V 0 ≤ VOUT ≤ 5.5V ISB ILI ILO VIH VIL VOH VOL VDH 30 10 10 VCC 0.8 µA µA µA V V V V V IOH = –2mA IOL = 4.2mA VCC CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V Symbol CI/O(1) CIN(1) Parameter Input/Output Capacitance Input Capacitance Max. 10 6 Unit pF pF Conditions VI/O = 0V VIN = 0V Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) The minimum DC input voltage is -0.5V. During transitions, inputs may undershoot to -2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns. (3) Output shorted for no more than one second. No more than one output shorted at a time. (4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from -1V to VCC +1V. 3 Doc. No. 1082, Rev. O CAT22C10 A.C. CHARACTERISTICS, Write Cycle VCC = +5V ±10%, unless otherwise specified. 22C10-20 Symbol tWC tCW tAS tWP tWR tDW tDH tWZ(1) tOW Parameter Write Cycle Time CS Write Pulse Width Address Setup Time Write Pulse Width Write Recovery Time Data Valid Time Data Hold Time Output Disable Time Output Enable Time 0 Min. 200 150 50 150 25 100 0 100 0 Max. 22C10-30 Min. 300 150 50 150 25 100 0 100 Max. Unit ns ns ns ns ns ns ns ns ns CL = 100pF +1TTL gate VOH = 2.2V VOL = 0.65V VIH = 2.2V VIL = 0.65V Conditions A.C. CHARACTERISTICS, Read Cycle VCC = +5V ±10%, unless otherwise specified. 22C10-20 Symbol tRC tAA tCO tOH tLZ(1) tHZ(1) Parameter Read Cycle Time Address Access Time CS Access Time Output Data Hold Time CS Enable Time CS Disable Time 0 0 100 Min. 200 200 200 0 0 100 Max. 22C10-30 Min. 300 300 300 Max. Unit ns ns ns ns ns ns Conditions CL = 100pF +1TTL gate VOH = 2.2V VOL = 0.65V VIH = 2.2V VIL = 0.65V Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. Doc. No. 1082, Rev. O 4 CAT22C10 A.C. CHARACTERISTICS, Store Cycle VCC = +5V ±10%, unless otherwise specified. Limits Symbol tSTC tSTP tSTZ(1) tOST(1) Parameter Store Time Store Pulse Width Store Disable Time Store Enable Time 0 200 100 Min. Max. 10 Units ms ns ns ns CL = 100pF + 1TTL gate VOH = 2.2V, VOL = 0.65V VIH = 2.2V, VIL = 0.65V Conditions A.C. CHARACTERISTICS, Recall Cycle VCC = +5V ±10%, unless otherwise specified. Limits Symbol tRCC tRCP tRCZ tORC tARC Parameter Recall Cycle Time Recall Pulse Width Recall Disable Time Recall Enable Time Recall Data Access Time 0 1.1 Min. 1.4 300 100 Max. Units µs ns ns ns µs CL = 100pF + 1TTL gate VOH = 2.2V, VOL = 0.65V VIH = 2.2V, VIL = 0.65V Conditions Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. 5 Doc. No. 1082, Rev. O CAT22C10 DEVICE OPERATION The configuration of the CAT22C10 allows a common address bus to be directly connected to the address inputs. Additionally, the Input/Output (I/O) pins can be directly connected to a common I/O bus if the bus has less than 1 TTL load and 100pF capacitance. If not, the I/O path should be buffered. When the chip select (CS) pin goes low, the device is activated. When CS is forced high, the device goes into the standby mode and consumes very little current. With the nonvolatile functions inhibited, the device operates like a Static RAM. The Write Enable (WE) pin selects a write operation when WE is low and a read operation when WE is high. In either of these modes, an array byte (4 bits) can be addressed uniquely by using the address lines (A0–A5), and that byte will be read or written to through the Input/Output pins (I/O0–I/O3). The nonvolatile functions are inhibited by holding the STORE input and the RECALL input high. When the RECALL input is taken low, it initiates a recall operation which transfers the contents of the entire EEPROM array into the Static RAM. When the STORE input is taken low, it initiates a store operation which transfers the entire Static RAM array contents into the EEPROM array. Standby Mode The chip select (CS) input controls all of the functions of the CAT22C10. When a high level is supplied to the CS pin, the device goes into the standby mode where the outputs are put into a high impendance state and the power consumption is drastically reduced. With ISB less than 100µA in standby mode, the designer has the flexibility to use this part in battery operated systems. Read When the chip is enabled (CS = low), the nonvolatile functions are inhibited (STORE = high and RECALL = high). With the Write Enable (WE) pin held high, the data in the Static RAM array may be accessed by selecting an address with input pins A0–A5. This will occur when the outputs are connected to a bus which is loaded by no more than 100pF and 1 TTL gate. If the loading is greater than this, some additional buffering circuitry is recom- Figure 1. Read Cycle Timing tRC ADDRESS tAA CS tLZ DATA I/O tOH DATA VALID tHZ HIGH-Z tCO Doc. No. 1082, Rev. O 6 CAT22C10 mended. Write With the chip enabled and the nonvolatile functions inhibited, the Write Enable (WE) pin will select the write mode when driven to a low level. In this mode, the address must be supplied for the byte being written. After the set-up time (tAS), the input data must be Figure 2. Write Cycle Timing tWC ADDRESS tCW CS tAS WE tDW DATA IN tWZ DATA OUT HIGH-Z DATA VALID tOW tDH tWP tWR supplied to pins I/O0–I/O3. When these conditions, including the write pulse width time (tWP) are met, the data will be written to the specified location in the Static RAM. A write function may also be initiated from the standby mode by driving WE low, inhibiting the nonvolatile functions, supplying valid addresses, and then taking CS low and supplying input data. Figure 3. Early Write Cycle Timing tWC ADDRESS tCW CS tAS tWP WE tDW DATA IN DATA VALID tDH tWR DATA OUT HIGH-Z 7 Doc. No. 1082, Rev. O CAT22C10 Recall At anytime, except during a store operation, taking the RECALL pin low will initiate a recall operation. This is independent of the state of CS, WE, or A0–A5. After the RECALL pin has been held low for the duration of the Recall Pulse Width (tRCP), the recall will continue independent of any other inputs. During the recall, the entire contents of the EEPROM array is transferred to the Static RAM array. The first byte of data may be externally accessed after the recalled data access time from end of recall (tARC) is met. After this, any other byte may be accessed by using the normal read mode. If the RECALL pin is held low for the entire Recall Cycle time (tRCC), the contents of the Static RAM may be immediately accessed by using the normal read mode. A recall operation can be performed an unlimited number of times without affecting the integrity of the data. The outputs I/O0–I/O3 will go into the high impedance state as long as the RECALL signal is held low. Store At any time, except during a recall operation, taking the STORE pin low will initiate a store operation. This takes Figure 4. Recall Cycle Timing place independent of the state of CS, WE or A0–A5. The STORE pin must be held low for the duration of the Store Pulse Width (tSTP) to ensure that a store operation is initiated. Once initiated, the STORE pin becomes a “Don’t Care”, and the store operation will complete its transfer of the entire contents of the Static RAM array into the EEPROM array within the Store Cycle time (tSTC). If a store operation is initiated during a write cycle, the contents of the addressed Static RAM byte and its corresponding byte in the EEPROM array will be unknown. During the store operation, the outputs are in a high impedance state. A minimum of 100,000 store operations can be performed reliably and the data written into the EEPROM array has a minimum data retention time of 10 years. DATA PROTECTION DURING POWER-UP AND POWER-DOWN The CAT22C10 has on-chip circuitry which will prevent a store operation from occurring when VCC falls below 3.0V typ. This function eliminates the potential hazard of spurious signals initiating a store operation when the system power is below 3.0V typ. tRCC ADDRESS tRCP RECALL tARC CS tORC HIGH-Z DATA I/O tRCZ DATA UNDEFINED DATA VALID Figure 5. Store Cycle Timing tSTC tSTP STORE tSTZ DATA I/O HIGH-Z Doc. No. 1082, Rev. O 8 CAT22C10 ORDERING INFORMATION Prefix CAT Device # 22C10 J Suffix I -20 -TE13 Optional Company ID Product Number Temperature Range Blank = Commercial (0˚ - 70˚C) I = Industrial (-40˚ - 85˚C) A = Automotive (-40˚ - 105˚C)* Tape & Reel Package P: PDIP J: SOIC (JEDEC) L: PDIP (Lead free, Halogen free) W: SOIC (Lead free, Halogen free) * -40˚ to +125˚C is available upon request Speed 20: 200ns 30: 300ns Notes: (1) The device used in the above example is a 22C10JI-20TE13 (SOIC, Industrial Temperature, 200ns Access Time, Tape & Reel) 9 Doc. No. 1082, Rev. O REVISION HISTORY Date 04/16/2004 Revision Comments O Add Lead free logo Update Features Update Pin Configuration Update Ordering Information Update Rev. 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Corporate Headquarters 1250 Borregas Avenue Sunnyvale, CA 94089 Phone: 408.542.1000 Fax: 408.542.1200 www.catalyst-semiconductor.com Publication #: Revison: Issue date: 1082 O 04/16/04