CAT24AA01

CAT24AA01, CAT24AA02 1-Kb and 2-Kb I2C CMOS Serial EEPROM FEATURES Supports Standard and Fast I C Protocol 1.7 V to 5.5 V Supply Voltage Range 16-Byte Page Write Buffer Hardware Write Protection for entire memory Schmitt Triggers and Noise Suppression Filters on I2C Bus Inputs (SCL and SDA) Low power CMOS technology 1,000,000 program/erase cycles 100 year data retention Industrial temperature range RoHS-compliant TSOT-23 5-lead and SOIC 8-lead packages For Ordering Information details, see page 12. 2 DESCRIPTION The CAT24AA01/24AA02 are 1-Kb and 2-Kb CMOS Serial EEPROM devices internally organized as 128x8/256x8 bits. They feature a 16-byte page write buffer and support both the Standard (100kHz) and the Fast (400kHz) I2C protocols. In contrast to the CAT24C01/24C02, the CAT24AA01/24AA02 have no external address pins, and are therefore suitable in applications that require a single CAT24AA01/02 on the I2C bus. PIN CONFIGURATION SOIC (W) NC NC NC VSS 1 2 3 4 8 VCC 7 WP 6 SCL 5 SDA TSOT-23 (TD) SCL VSS SDA 1 2 3 4 VCC 5 WP FUNCTIONAL SYMBOL VCC SCL CAT24AA01 CAT24AA02 WP SDA * For the location of Pin 1, please consult the corresponding package drawing. VSS PIN FUNCTIONS Pin Name SDA SCL WP VCC VSS Function Serial Data/Address Clock Input Write Protect Power Supply Ground © Catalyst Semiconductor, Inc. Characteristics subject to change without notice 1 Doc. No. MD-1120 Rev. B CAT24AA01, CAT24AA02 ABSOLUTE MAXIMUM RATINGS(1) Parameters Storage Temperature Voltage on any Pin with Respect to Ground REABILITY CHARACTERISTICS(3) Symbol NEND (4) (2) Ratings –65 to +150 –0.5 to +6.5 Units ºC V Parameter Endurance Data Retention Min 1,000,000 100 Units Program/Erase Cycles Years TDR D.C. OPERATING CHARACTERISTICS VCC = 1.7 V to 5.5 V, TA = -40°C to 85°C, unless otherwise specified. Symbol ICCR ICCW ISB IL VIL VIH VOL1 VOL2 Parameter Read Current Write Current Standby Current I/O Pin Leakage Input Low Voltage Input High Voltage Output Low Voltage Output Low Voltage VCC ≥ 2.5 V, IOL = 3.0 mA VCC < 2.5 V, IOL = 1.0 mA Test Conditions Read, fSCL = 400 kHz Write All I/O Pins at GND or VCC Pin at GND or VCC -0.5 VCC x 0.7 Min Max 0.5 1 1 1 VCC x 0.3 VCC + 0.5 0.4 0.2 Units mA mA μA μA V V V V PIN IMPEDANCE CHARACTERISTICS VCC = 1.7 V to 5.5 V, TA = -40°C to 85°C, unless otherwise specified. Symbol CIN CIN (3) (3) Parameter SDA I/O Pin Capacitance Input Capacitance (other pins) WP Input Current Conditions VIN = 0V VIN = 0V VIN < VIH VIN > VIH Max 8 6 100 1 Units pF pF μA IWP(5) Notes: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. (2) The DC input voltage on any pin should not be lower than -0.5V or higher than VCC + 0.5V. During transitions, the voltage on any pin may undershoot to no less than -1.5V or overshoot to no more than VCC + 1.5V, for periods of less than 20ns. (3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100 and JEDEC test methods. (4) Page Mode @ 25°C (5) When not driven, the WP pin is pulled down to GND internally. For improved noise immunity, the internal pull-down is relatively strong; therefore the external driver must be able to supply the pull-down current when attempting to drive the input HIGH. To conserve power, as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x VCC), the strong pull-down reverts to a weak current source. Doc. No. MD-1120 Rev. B 2 © Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT24AA01, CAT24AA02 A.C. CHARACTERISTICS VCC = 1.7 V to 5.5 V, TA = -40°C to 85°C. Standard Symbol FSCL tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF (2) (1) Fast Min 0.6 1.3 0.6 0.6 0 100 Max 400 Units kHz μs μs μs μs μs ns 300 300 0.6 1.3 ns ns μs μs 0.9 100 100 0 2.5 5 1 5 1 μs ns ns μs μs ms ms Parameter Clock Frequency START Condition Hold Time Low Period of SCL Clock High Period of SCL Clock START Condition Setup Time Data In Hold Time Data In Setup Time SDA and SCL Rise Time SDA and SCL Fall Time STOP Condition Setup Time Bus Free Time Between STOP and START SCL Low to Data Out Valid Data Out Hold Time Noise Pulse Filtered at SCL and SDA Inputs WP Setup Time WP Hold Time Write Cycle Time Power-up to Ready Mode Min 4 4.7 4 4.7 0 250 Max 100 1000 300 4 4.7 3.5 100 100 0 2.5 tSU:STO tBUF tAA tDH Ti (2) tSU:WP tHD:WP tWR tPU (2, 3) A.C. TEST CONDITIONS Input Levels Input Rise and Fall Times Input Reference Levels Output Reference Levels Output Load 0.2 x VCC to 0.8 x VCC ≤ 50ns 0.3 x VCC, 0.7 x VCC 0.5 x VCC Current Source: IOL = 3mA (VCC ≥ 2.5V); IOL = 1mA (VCC < 2.5V); CL = 100pF Notes: (1) Test conditions according to “A.C. Test Conditions” table. (2) Tested initially and after a design or process change that affects this parameter. (3) tPU is the delay between the time VCC is stable and the device is ready to accept commands. © Catalyst Semiconductor, Inc. Characteristics subject to change without notice 3 Doc. No. MD-1120 Rev. B CAT24AA01, CAT24AA02 POWER-ON RESET (POR) Each CAT24AA01/02 incorporates Power-On Reset (POR) circuitry which protects the internal logic against powering up in the wrong state. The device will power up into Standby mode after VCC exceeds the POR trigger level and will power down into Reset mode when VCC drops below the POR trigger level. This bi-directional POR behavior protects the device against brown-out failure, following a temporary loss of power. FUNCTIONAL DESCRIPTION The CAT24AA01/02 supports the Inter-Integrated Circuit (I2C) Bus protocol. The protocol relies on the use of a Master device, which provides the clock and directs bus traffic, and Slave devices which execute requests. The CAT24AA01/02 operates as a Slave device. Both Master and Slave can transmit or receive, but only the Master can assign those roles. I2C BUS PROTOCOL The 2-wire I2C bus consists of two lines, SCL and SDA, connected to the VCC supply via pull-up resistors. The Master provides the clock to the SCL line, and the Master and Slaves drive the SDA line. A ‘0’ is transmitted by pulling a line LOW and a ‘1’ by releasing it HIGH. Data transfer may be initiated only when the bus is not busy (see A.C. Characteristics). During data transfer, SDA must remain stable while SCL is HIGH. START/STOP Condition An SDA transition while SCL is HIGH creates a START or STOP condition (Figure 1). A START is generated by a HIGH to LOW transition, while a STOP is generated by a LOW to HIGH transition. The START acts like a wake-up call. Absent a START, no Slave will respond to the Master. The STOP completes all commands. Device Addressing The Master addresses a Slave by creating a START condition and then broadcasting an 8-bit Slave address (Figure 2). The first four bits of the Slave address are 1010 (Ah). For the CAT24AA01/02 the next three bits must be 000. PIN DESCRIPTION SCL: The Serial Clock input pin accepts the clock signal generated by the Master. SDA: The Serial Data I/O pin accepts input data and delivers output data. In transmit mode, this pin is open drain. Data is acquired on the positive edge, and delivered on the negative edge of SCL. WP: When the Write Protect input pin is forced HIGH by an external source, all write operations are inhibited. When the pin is not driven by an external source, it is pulled LOW internally. ¯¯, The last bit, R/W instructs the Slave to either provide (1) or accept (0) data, i.e. it signals a Read (1) or a Write (0) request. Acknowledge During the 9th clock cycle following every byte sent onto the bus, the transmitter releases the SDA line, allowing the receiver to respond. The receiver then either acknowledges (ACK) by pulling SDA LOW, or does not acknowledge (NoACK) by letting SDA stay HIGH (Figure 3). Bus timing is illustrated in Figure 4. Doc. No. MD-1120 Rev. B 4 © Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT24AA01, CAT24AA02 Figure 1: Start/Stop Timing SCL SDA START CONDITION STOP CONDITION Figure 2: Slave Address Bits 1 0 1 0 0 0 0 ¯¯ R/W Figure 3: Acknowledge Timing BUS RELEASE DELAY (TRANSMITTER) SCL FROM MASTER 1 8 9 BUS RELEASE DELAY (RECEIVER) DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER START ACK DELAY (≤ tAA) ACK SETUP (≥ tSU:DAT) Figure 4: Bus Timing tF tLOW SCL tHIGH tR tLOW tSU:STA SDA IN tHD:STA tHD:DAT tSU:DAT tSU:STO tAA tDH tBUF SDA OUT © Catalyst Semiconductor, Inc. Characteristics subject to change without notice 5 Doc. No. MD-1120 Rev. B CAT24AA01, CAT24AA02 WRITE OPERATIONS Byte Write To write data to memory, the Master creates a START condition on the bus and then broadcasts a Slave ¯¯ address with the R/W bit set to ‘0’. The Master then sends an address byte and a data byte and concludes the session by creating a STOP condition on the bus. The Slave responds with ACK after every byte sent by the Master (Figure 5). The STOP starts the internal Write cycle, and while this operation is in progress (tWR), the SDA output is tri-stated and the Slave does not acknowledge the Master (Figure 6). Page Write The Byte Write operation can be expanded to Page Write, by sending more than one data byte to the Slave before issuing the STOP condition (Figure 7). Up to 16 distinct data bytes can be loaded into the internal Page Write Buffer starting at the address provided by the Master. The page address is latched, and as long as the Master keeps sending data, the internal byte address is incremented up to the end of page, where it then wraps around (within the page). New data can therefore replace data loaded earlier. Following the STOP, data loaded during the Page Write session will be written to memory in a single internal Write cycle (tWR). Acknowledge Polling As soon (and as long) as internal Write is in progress, the Slave will not acknowledge the Master. This feature enables the Master to immediately follow-up with a new Read or Write request, rather than wait for the maximum specified Write time (tWR) to elapse. Upon receiving a NoACK response from the Slave, the Master simply repeats the request until the Slave responds with ACK. Hardware Write Protection With the WP pin held HIGH, the entire memory is protected against Write operations. If the WP pin is left floating or is grounded, it has no impact on the Write operation. The state of the WP pin is strobed on the last falling edge of SCL immediately preceding the st 1 data byte (Figure 8). If the WP pin is HIGH during the strobe interval, the Slave will not acknowledge the data byte and the Write request will be rejected. Delivery State The CAT24AA01/02 is shipped erased, i.e., all bytes are FFh. Doc. No. MD-1120 Rev. B 6 © Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT24AA01, CAT24AA02 Figure 5: Byte Write Sequence S T A R T S BUS ACTIVITY: MASTER SLAVE ADDRESS ADDRESS BYTE DATA BYTE a7 ÷ a0 d7 ÷ d0 S T O P P SLAVE A C K A C K A C K Figure 6: Write Cycle Timing SCL SDA 8th Bit Byte n ACK tWR STOP CONDITION START CONDITION ADDRESS Figure 7: Page Write Sequence BUS ACTIVITY: MASTER S T A R T S SLAVE ADDRESS ADDRESS BYTE DATA BYTE n DATA BYTE n+1 DATA BYTE n+x S T O P P A C K A C K A C K SLAVE n=1 x ≤ 15 A C K A C K Figure 8: WP Timing ADDRESS BYTE 1 SCL 8 9 1 DATA BYTE 8 SDA a7 a0 tSU:WP d7 d0 WP tHD:WP © Catalyst Semiconductor, Inc. Characteristics subject to change without notice 7 Doc. No. MD-1120 Rev. B CAT24AA01, CAT24AA02 READ OPERATIONS Immediate Read To read data from memory, the Master creates a START condition on the bus and then broadcasts a ¯¯ Slave address with the R/W bit set to ‘1’. The Slave responds with ACK and starts shifting out data residing at the current address. After receiving the data, the Master responds with NoACK and terminates the session by creating a STOP condition on the bus (Figure 9). The Slave then returns to Standby mode. Selective Read To read data residing at a specific address, the selected address must first be loaded into the internal address register. This is done by starting a Byte Write sequence, whereby the Master creates a START condition, then broadcasts a Slave address with the ¯¯ R/W bit set to ‘0’ and then sends an address byte to the Slave. Rather than completing the Byte Write sequence by sending data, the Master then creates a START condition and broadcasts a Slave address ¯¯ with the R/W bit set to ‘1’. The Slave responds with ACK after every byte sent by the Master and then sends out data residing at the selected address. After receiving the data, the Master responds with NoACK and then terminates the session by creating a STOP condition on the bus (Figure 10). Sequential Read If, after receiving data sent by the Slave, the Master responds with ACK, then the Slave will continue transmitting until the Master responds with NoACK followed by STOP (Figure 11). During Sequential Read the internal byte address is automatically incremented up to the end of memory, where it then wraps around to the beginning of memory. For the CAT24AA01, the internal address counter will not wrap around at the end of the 128 byte memory space. Doc. No. MD-1120 Rev. B 8 © Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT24AA01, CAT24AA02 Figure 9: Immediate Read Sequence and Timing N O SLAVE ADDRESS BUS ACTIVITY: MASTER S T A R T S S AT CO KP P SLAVE A C K DATA BYTE SCL 8 9 SDA 8th Bit DATA OUT NO ACK STOP Figure 10: Selective Read Sequence N O BUS ACTIVITY: MASTER S T A R T SLAVE ADDRESS ADDRESS BYTE S T A R T S SLAVE ADDRESS S AT CO KP P S SLAVE A C K A C K A C K DATA BYTE Figure 11: Sequential Read Sequence BUS ACTIVITY: MASTER N O S AT CO KP P SLAVE ADDRESS A C K A C K A C K SLAVE A C K DATA BYTE n DATA BYTE n+1 DATA BYTE n+2 DATA BYTE n+x © Catalyst Semiconductor, Inc. Characteristics subject to change without notice 9 Doc. No. MD-1120 Rev. B CAT24AA01, CAT24AA02 PACKAGE OUTLINE DRAWINGS SOIC 8-Lead 150mils (W) (1)(2) SYMBOL MIN NOM MAX A A1 b c E1 E 1.35 0.10 0.33 0.19 4.80 5.80 3.80 1.27 BSC 0.25 0.40 0º 1.75 0.25 0.51 0.25 5.00 6.20 4.00 0.50 1.27 8º D E E1 e h L θ PIN # 1 IDENTIFICATION TOP VIEW D h A1 A θ c e b L SIDE VIEW END VIEW For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf. Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC standard MS-012. Doc. No. MD-1120 Rev. B 10 © Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT24AA01, CAT24AA02 TSOT 5-Lead (TD) (1)(2) D e SYMBOL A A1 A2 b c D E1 E MIN 0.01 0.80 0.30 0.12 NOM 0.05 0.87 0.15 2.90 BSC 2.80 BSC 1.60 BSC 0.95 TYP MAX 1.00 0.10 0.90 0.45 0.20 E E1 e L L1 L2 θ 0º 0.30 0.40 0.60 REF 0.25 BSC 0.50 8º TOP VIEW A2 A θ b A1 L1 L c L2 SIDE VIEW END VIEW For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf. Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC standard MO-193. © Catalyst Semiconductor, Inc. Characteristics subject to change without notice 11 Doc. No. MD-1120 Rev. B CAT24AA01, CAT24AA02 EXAMPLE OF ORDERING INFORMATION (1) Prefix CAT Company ID Device # Suffix 24AA02 TD I – G T3 Tape & Reel T: Tape & Reel 3: 3,000/Reel 10: 10,000/Reel Temperature Range I: Industrial (-40ºC to 85ºC) Product Number 24AA01 24AA02 Package TD: TSOT-23 5-lead W: SOIC 8-lead Lead Finish G: NiPdAu Blank: Matte-Tin For Product Top Mark Codes, click here: http://www.catsemi.com/techsupport/producttopmark.asp Notes: (1) All packages are RoHS-compliant (Lead-free, Halogen-free). (2) The standard plated finish is NiPdAu. (3) The device used in the above example is a CAT24AA02TDI-GT3 (TSOT-23 5-lead, Industrial Temperature, NiPdAu, Tape & Reel, 3,000/Reel). (4) For additional package and temperature options, please contact your nearest Catalyst Semiconductor Sales office. Doc. No. MD-1120 Rev. B 12 © Catalyst Semiconductor, Inc. Characteristics subject to change without notice REVISION HISTORY Date 12/07/2007 03/12/2008 Rev. A B Reason Initial Issue Add CAT24AA01 Add link to Product Top Mark Code Copyrights, Trademarks and Patents © Catalyst Semiconductor, Inc. Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: Adaptive Analog™, Beyond Memory™, DPP™, EZDim™, LDD™, MiniPot™, Quad-Mode™ and Quantum Charge Programmable™ I2C™ is a trademark of Philips Corporation. Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol. Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. 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Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete. Catalyst Semiconductor, Inc. Corporate Headquarters 2975 Stender Way Santa Clara, CA 95054 Phone: 408.542.1000 Fax: 408.542.1200 www.catsemi.com Document No: MD-1120 Revision: B Issue date: 03/12/08