CAT24FC16JETE13

CAT24FC16 16-kb I2C Serial EEPROM FEATURES I 400 kHz (2.5 V) I2C bus compatible I 2.5 to 5.5 volt operation I Low power CMOS technology I 16-byte page write buffer I Industrial and extended temperature ranges I Self-timed write cycle with auto-clear I 1,000,000 program/erase cycles I 100 year data retention H GEN FR ALO EE LE A D F R E ETM I 8-pin DIP, SOIC, TSSOP, MSOP and TDFN packages - “Green” package option available I 2,048 x 8 memory organization I Hardware write protect DESCRIPTION The CAT24FC16 is a 16-kb Serial CMOS EEPROM internally organized as 2048 words of 8 bits each. Catalyst’s advanced CMOS technology substantially reduces device power requirements. The CAT24FC16 PIN CONFIGURATION DIP Package (P, L) NC NC NC VSS 1 2 3 4 8 7 6 5 VCC WP SCL SDA SOIC Package (J, W) NC NC NC 1 2 3 4 8 7 6 5 MSOP Package (R, Z) NC NC NC VSS 1 2 3 4 8 7 6 5 D NC NC NC VSS is 1 2 3 4 TSSOP Package (U, Y) 8 7 6 5 o c VSS VCC 1 WP 2 SCL 3 SDA 4 i t n VCC WP SCL SDA VCC WP SCL SDA 8 NC 7 NC 6 NC 5 VSS u n VCC VSS SDA WP SCL features a 16-byte page write buffer. The device operates via the I2C bus serial interface and is available in 8-pin DIP, SOIC, TSSOP, MSOP and TDFN packages. BLOCK DIAGRAM EXTERNAL LOAD d e a P XDEC t r DOUT ACK SENSE AMPS SHIFT REGISTERS WORD ADDRESS BUFFERS COLUMN DECODERS START/STOP LOGIC E2PROM CONTROL LOGIC DATA IN STORAGE TDFN Package (RD4, ZD4) STATE COUNTERS HIGH VOLTAGE/ TIMING CONTROL VCC WP SCL SDA PIN FUNCTIONS Pin Name NC SDA SCL WP VCC Function No Connect Serial Data/Address Serial Clock Write Protect 2.5 V to 5.5 V Power Supply Ground * Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol. © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice. VSS 1 Doc. No. 1054, Rev. I CAT24FC16 Lead Soldering Temperature (10 seconds) ...... 300°C Output Short Circuit Current(2) ....................... 100 mA ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias –55°C to +125°C Storage Temperature ....................... –65°C to +150°C Voltage on Any Pin with Respect to Ground(1) ............ –2.0 V to VCC + 2.0 V VCC with Respect to Ground ............. –2.0 V to +7.0 V Package Power Dissipation Capability (TA = 25°C) .................................. 1.0 W RELIABILITY CHARACTERISTICS(3) Symbol NEND TDR VZAP ILTH(4) Parameter Endurance Data Retention ESD Susceptibility Latch-up *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Min 1,000,000 100 4000 Typ D.C. OPERATING CHARACTERISTICS VCC = 2.5 V to 5.5 V, unless otherwise specified. Symbol ICC ICC ISB(5) ILI ILO VIL VIH VOL Parameter Power Supply Current (Read) Power Supply Current (Write) Test Conditions Standby Current (VCC = 5.0 V) Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage CAPACITANCE TA = 25°C, f = 400 kHz, VCC = 5 V Symbol CI/O(3) CIN(3) Test Conditions VI/O = 0 V VIN = 0 V Min Typ Max 8 6 Units pF pF Input/Output Capacitance (SDA) Input Capacitance (other pins) Note: (1) The minimum DC input voltage is –0.5 V. During transitions, inputs may undershoot to –2.0 V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC + 0.5 V, which may overshoot to VCC + 2.0 V for periods of less than 20 ns. (2) Output shorted for no more than one second. No more than one output shorted at a time. (3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100 and JEDEC test methods. (4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1.0 V to VCC + 1.0 V. (5) Maximum standby current (ISB) = 10µA for the Extended Automotive temperature range. is D Output Low Voltage (VCC = 3.0 V) o c i t n fSCL = 400 kHz fSCL = 400 kHz VIN = GND or VCC VIN = GND to VCC VOUT = GND to VCC u n d e Min –1 100 a P Max Max 1 3 1 1 1 VCC x 0.3 VCC + 1.0 0.4 Units Cycles/Byte Years Volts mA t r Units mA mA µA µA µA V V V Typ VCC x 0.7 IOL = 3 mA Doc. No. 1054, Rev. I 2 CAT24FC16 A.C. CHARACTERISTICS VCC = 2.5 V to 5.5 V, unless otherwise specified. Read & Write Cycle Limits Symbol Parameter 2.5 V - 5.5 V Min FSCL TI(1) tAA tBUF (1) Max 400 100 Units Clock Frequency Noise Suppression Time Constant at SCL, SDA Inputs SCL Low to SDA Data Out and ACK Out Time the Bus Must be Free Before a New Transmission Can Start Start Condition Hold Time Clock Low Period Clock High Period Start Condition Setup Time (for a Repeated Start Condition) Data In Hold Time Data In Setup Time SDA and SCL Rise Time SDA and SCL Fall Time 1300 600 1300 tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR(1) tF (1) tSU:STO tDH Stop Condition Setup Time Data Out Hold Time Power-Up Timing(1)(2) Symbol tPUR tPUW Write Cycle Limits Symbol tWR The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle, the bus is D Power-up to Read Operation Power-up to Write Operation o c Parameter Parameter i t n u n d e 600 600 0 100 600 100 Typ Typ a P 300 300 Max 1 1 900 t r ns ns ns ns ns ns ns ns ns ns ns ns ns kHz Min Units ms ms Min Max 5 Units ms Write Cycle Time interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address. Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. 3 Doc No. 1054, Rev. I CAT24FC16 FUNCTIONAL DESCRIPTION The CAT24FC16 supports the I2C Bus data transmission protocol. This Inter-Integrated Circuit Bus protocol defines any device that sends data to the bus to be a transmitter and any device receiving data to be a receiver. Data transfer is controlled by the Master device which generates the serial clock and all START and STOP conditions for bus access. The CAT24FC16 operates as a Slave device. Both the Master and Slave devices can operate as either transmitter or receiver, but the Master device controls which mode is activated. PIN DESCRIPTIONS SCL: Serial Clock The CAT24FC16 serial clock input pin is used to clock all data transfers into or out of the device. This is an input pin. SDA: Serial Data/Address The CAT24FC16 bidirectional serial data/address pin is used to transfer data into and out of the device. The SDA pin is an open drain output and can be wire-ORed with other open drain or open collector outputs. WP: Write Protect This input, when tied to GND, allows write operations to the entire memory. For CAT24FC16 when this pin is tied to VCC, the entire array of memory is write protected. When left floating, memory is unprotected. Figure 1. Bus Timing tF tLOW tHIGH tLOW tR SCL tSU:STA tHD:STA tHD:DAT SDA IN tAA SDA OUT Figure 2. Write Cycle Timing SCL SDA Figure 3. Start/Stop Timing D is SDA SCL 8TH BIT BYTE n o c START BIT i t n u n tSU:DAT tDH d e a P t r tSU:STO tBUF ACK tWR STOP CONDITION START CONDITION ADDRESS STOP BIT Doc. No. 1054, Rev. I 4 CAT24FC16 I2C BUS PROTOCOL The following defines the features of the I2C bus protocol: (1) Data transfer may be initiated only when the bus is not busy. (2) During a data transfer, the data line must remain stable whenever the clock line is high. Any changes in the data line while the clock line is high will be interpreted as a START or STOP condition. START Condition The START Condition precedes all commands to the device, and is defined as a HIGH to LOW transition of SDA when SCL is HIGH. The CAT24FC16 monitor the SDA and SCL lines and will not respond until this condition is met. STOP Condition A LOW to HIGH transition of SDA when SCL is HIGH determines the STOP condition. All operations must end with a STOP condition. whether a Read or Write operation is to be performed. When this bit is set to 1, a Read operation is selected, and when set to 0, a Write operation is selected. After the Master sends a START condition and the slave address byte, the CAT24FC16 monitors the bus and responds with an acknowledge (on the SDA line) when its address matches the transmitted slave address. The CAT24FC16 then performs a Read or a Write operation depending on the state of the R/W bit. Acknowledge After a successful data transfer, each receiving device is required to generate an acknowledge. The Acknowledging device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data. The CAT24FC16 responds with an acknowledge after receiving a START condition and its slave address. If the device has been selected along with a write operation, it responds with an acknowledge after receiving each byte. DEVICE ADDRESSING The Master begins a transmission by sending a START condition. The Master then sends the address of the particular slave device it is requesting. The four most significant bits of the 8-bit slave address are fixed as 1010 for the CAT24FC16 (see Fig. 5). The next three significant bits (A10, A9, A8) are the memory array address bits. The last bit of the slave address specifies Figure 4. Acknowledge Timing is D DATA OUTPUT FROM TRANSMITTER o c SCL FROM MASTER 1 0 i t n 1 1 0 A10 u n When the CAT24FC16 begins a READ mode, it transmits 8 bits of data, releases the SDA line, and monitors the line for an acknowledge. Once it receives this acknowledge, the CAT24FC16 will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a STOP condition. d e 8 a P 9 t r DATA OUTPUT FROM RECEIVER START ACKNOWLEDGE Figure 5. Slave Address Bits A9 A8 R/W Normal Read and Write DEVICE ADDRESS 5 Doc No. 1054, Rev. I CAT24FC16 WRITE OPERATIONS Byte Write In the Byte Write mode, the Master device sends the START condition and the slave address information (with the R/W bit set to zero) to the Slave device. After the Slave generates an acknowledge, the Master sends the byte address that is to be written into the address pointer of the CAT24FC16. After receiving another acknowledge from the Slave, the Master device transmits the data byte to be written into the addressed memory location. The CAT24FC16 acknowledges once more and the Master generates the STOP condition, at which time the device begins its internal programming to nonvolatile memory. While this internal cycle is in progress, the device will not respond to any request from the Master device. Page Write The CAT24FC16 writes up to 16 bytes of data in a single write cycle, using the Page Write operation. The Page Write operation is initiated in the same manner as the Byte Write operation, however instead of terminating after the initial word is transmitted, the Master is allowed to send up to 15 additional bytes. After each byte has been transmitted the CAT24FC16 will respond with an acknowledge, and internally increment the low order address bits by one. The high order bits remain unchanged. Once all 16 bytes are received and the STOP condition has been sent by the Master, the internal programming cycle begins. At this point all received data is written to the CAT24FC16 in a single write cycle. Acknowledge Polling The disabling of the inputs can be used to take advantage of the typical write cycle time. Once the stop condition is issued to indicate the end of the host’s write operation, the CAT24FC16 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation. If the CAT24FC16 is still busy with the write operation, no ACK will be returned. If the CAT24FC16 has completed the write operation, an ACK will be returned and the host can then proceed with the next read or write operation. WRITE PROTECTION If the Master transmits more than 16 bytes prior to sending the STOP condition, the address counter ‘wraps around ’ , and previously transmitted data will be overwritten. Figure 6. Byte Write Timing Figure 7. Page Write Timing BUS ACTIVITY: MASTER SDA LINE S T A R T S A C K SLAVE ADDRESS * A C K A C K A C K A C K BYTE ADDRESS (n) S T O P P D is BUS ACTIVITY: MASTER SDA LINE o c S T A R T S i t n SLAVE ADDRESS u n BYTE ADDRESS The CAT24FC16 is designed with a hardware protect pin that enables the user to protect the entire memory. The hardware protection feature of the CAT24FC16 is designed into the part to provide added flexibility to the design engineers. The write protection feature of CAT24FC16 allows the user to protect against inadvertent programming of the memory array. If the WP pin is tied to Vcc, the entire memory array is protected and becomes read only. The entire memory becomes write protected regardless of whether the write protect register has been written or not. When WP pin is tied to Vcc, the user cannot program the write protect register. If the WP pin is left floating or tied to Vss, the device can be written into. d e DATA a P t r S T O P P DATA n DATA n+1 DATA n+P NOTE: IN THIS EXAMPLE n = XXXX 0000(B); X = 1 or 0 Doc. No. 1054, Rev. I 6 CAT24FC16 Read Operations The READ operation for the CAT24FC16 is initiated in the same manner as the write operation with the one exception that the R/W bit is set to a one. Three different READ operations are possible: Immediate Address READ, Selective READ and Sequential READ. Immediate Address Read The CAT24FC16’s address counter contains the address of the last byte accessed, incremented by one. In other words, if the last READ or WRITE access was to address N, the READ immediately following would access data from address N + 1. If N = 2047 for 24FC16, then the counter will ‘wrap around’ to address 0 and continue to clock out data. After the CAT24FC16 receives its slave address information (with the R/W bit set to one), it issues an acknowledge, then transmits the 8-bit byte requested. The master device does not send an acknowledge but will generate a STOP condition. Selective Read Selective READ operations allow the Master device to select at random any memory location for a READ operation. The Master device first performs a ‘dummy’ write operation by sending the START condition, slave address and byte address of the location it wishes to read. After the CAT24FC16 acknowledge the word address, the Master device resends the START condition and the slave address, this time with the R/W bit set to one. The CAT24FC16 then responds with its acknowledge and sends the 8-bit byte requested. The master device does not send an acknowledge but will generate a STOP condition. Sequential Read The Sequential READ operation can be initiated by either the Immediate Address READ or Selective READ operations. After the CAT24FC16 sends the initial 8-bit data requested, the Master will respond with an acknowledge which tells the device it requires more data. The CAT24FC16 will continue to output a byte for each acknowledge sent by the Master. The operation will terminate operation when the Master fails to respond with an acknowledge, thus sending the STOP condition. The data being transmitted from the CAT24FC16 is outputted sequentially with data from address N followed by data from address N + 1. The READ operation address counter increments all of the CAT24FC16 address bits so that the entire memory array can be read during one operation. If more than the 2047 bytes are read out, the counter will “wrap around” and continue to clock out data bytes. Figure 8. Immediate Address Read Timing S T A R T S is D SCL SDA o c BUS ACTIVITY: MASTER SDA LINE 8 i t n SLAVE ADDRESS u n A C K DATA d e S T O P P N O A C K a P t r 9 8TH BIT DATA OUT NO ACK STOP 7 Doc No. 1054, Rev. I CAT24FC16 Figure 9. Selective Read Timing S T A R T S A C K A C K S T A R T S A C K DATA n N O A C K BUS ACTIVITY: MASTER SDA LINE SLAVE ADDRESS BYTE ADDRESS (n) SLAVE ADDRESS S T O P P Figure 10. Sequential Read Timing BUS ACTIVITY: MASTER SDA LINE SLAVE ADDRESS DATA n DATA n+1 DATA n+2 A C K A C K is D Doc. No. 1054, Rev. I o c i t n u n A C K d e A C K a P DATA n+x S T O P P N O A C K t r 8 CAT24FC16 ORDERING INFORMATION Prefix CAT Device # 24FC16 J Suffix I TE13 REV-F Optional Company ID Product Number Temperature Range I = Industri E = Extended (-40°C to +125°C) Tape & Reel Package P: PDIP J: SOIC (JEDEC) R: MSOP U: TSSOP RD4: TDFN L: PDIP (Lead-free, Halogen-free) W: SOIC (JEDEC), (Lead-free, Halogen-free) Y: TSSOP (Lead-free, Halogen-free) Z: MSOP (Lead-free, Halogen-free) ZD4: TDFN (Lead-free, Halogen-free) GL: PDIP (Lead-free, Halogen-free, NiPdAu lead plating) GW: SOIC (JEDEC) (Lead-free, Halogen-free, NiPdAu lead plating) GY: TSSOP (Lead-free, Halogen-free, NiPdAu lead plating) GZ: MSOP (Lead-free, Halogen-free, NiPdAu lead plating) GD4: TDFN (Lead-free, Halogen-free, NiPdAu lead plating) Notes: (1) The device used in the above example is a 24FC16JI-TE13 (SOIC, Industrial Temperature, 2.5 Volt to 5.5 Volt Operating Voltage, Tape & Reel) is D o c i t n u n d e a P Die Revision t r 9 Doc No. 1054, Rev. I CAT24FC16 REVISION HISTORY Date 11/18/03 12/09/03 03/10/04 04/02/04 Revision Comments A B C D Initial Issue Changed Industrial Temp to “ I” from “ Blank” in ordering information Corrected TDFN ordering info Eliminated data sheet designation Removed reference to a write protect register in “ Write Protection” 05/15/04 E D.C. Operating Characteristics Write Cycle Limits Update Ordering Information Update Revision History Update Rev Number 06/07/04 7/27/04 03/24/05 F G H Update Write Cycle Limits Update notes on page 2 Updated Updated Updated Updated Updated Updated Updated Features Description Pin Function Reliability Characteristics Operating Characteristics A.C. Characteristics Ordering Information 06/23/05 I Update Ordering Information is D Doc. No. 1054, Rev. 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Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur. Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete. is D o c i t n u n d e a P t r Catalyst Semiconductor, Inc. Corporate Headquarters 1250 Borregas Avenue Sunnyvale, CA 94089 Phone: 408.542.1000 Fax: 408.542.1200 www.catalyst-semiconductor.com Publication #: Revison: Issue date: 1054 I 06/23/05