CAT24WC164PETE13

CAT24WC164 16K-Bit Serial EEPROM, Cascadable FEATURES I 400 kHz I C bus compatible* 2 H GEN FR ALO EE LE A D F R E ETM I Self-timed write cycle with auto-clear I 1,000,000 program/erase cycles I 100 year data retention I 8-pin DIP, 8-pin SOIC, 8-pin MSOP or I 1.8 to 5.5 volt operation I Low power CMOS technology I Write protect feature 8 pin TSSOP I Industrial, automotive and - Entire array protected when WP at VIH I Page write buffer (Also available in "Green" packages) extended temperature ranges DESCRIPTION The CAT24WC164 is a16K-bit, cascadable Serial CMOS EEPROM internally organized as 2048 words of 8 bits each. Catalyst’s advanced CMOS technology substantially reduces device power requirements. The CAT24WC164 features a 16-byte page write buffer. The device operates via the I2C bus serial interface, has a special write protection feature, and is available in 8-pin DIP, 8-pin SOIC, 8-pin TSSOP and 8-lead MSOP. PIN CONFIGURATION DIP Package (P, L) A0 A1 A2 VSS 1 2 3 4 8 7 6 5 VCC WP SCL SDA SOIC Package (J, W) A0 A1 A2 VSS 1 2 3 4 MSOP Package (R, Z) A0 A1 A2 VSS 1 2 3 4 PIN FUNCTIONS Pin Name A0, A1, A2 SDA SCL WP VCC VSS is D SCL SDA 8 7 6 5 VCC TEST A0 A1 A2 VSS o c 1 2 3 4 TSSOP Package (U, Y) 8 7 6 5 i t n 8 7 6 5 VCC WP SCL SDA 5020 FHD F01 u n VCC VSS SDA VCC WP SCL SDA WP BLOCK DIAGRAM EXTERNAL LOAD d e START/STOP LOGIC CONTROL LOGIC a P XDEC t r DOUT ACK SENSE AMPS SHIFT REGISTERS WORD ADDRESS BUFFERS COLUMN DECODERS E2PROM Function DATA IN STORAGE Device Address Inputs HIGH VOLTAGE/ TIMING CONTROL SCL A0 A1 A2 STATE COUNTERS SLAVE ADDRESS COMPARATORS Serial Data/Address Serial Clock Write Protect +1.8V to +5.5V Power Supply Ground * Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol. © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 1 Doc. No. 1026, Rev. J CAT24WC164 ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias ................. –55°C to +125°C Storage Temperature ....................... –65°C to +150°C Voltage on Any Pin with Respect to Ground(1) ........... –2.0V to +VCC + 2.0V VCC with Respect to Ground ............... –2.0V to +7.0V Package Power Dissipation Capability (Ta = 25°C) ................................... 1.0W Lead Soldering Temperature (10 secs) ............ 300°C Output Short Circuit Current(2) ........................ 100mA RELIABILITY CHARACTERISTICS Symbol NEND(3) TDR(3) VZAP(3) ILTH(3)(4) Parameter Endurance Data Retention ESD Susceptibility Latch-up Min. *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Max. 1,000,000 100 2000 100 D.C. OPERATING CHARACTERISTICS VCC = +1.8V to +5.5V, unless otherwise specified. Symbol ICC ISB (5) Parameter Power Supply Current Standby Current (VCC = 5.0V) Input Leakage Current Output Leakage Current Input Low Voltage ILI ILO VIL VIH VOL1 VOL2 CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V Symbol CI/O(3) CIN(3) Parameter Test Conditions VI/O = 0V VIN = 0V Min Typ Max 8 6 Units pF pF Input/Output Capacitance (SDA) is D Input High Voltage Output Low Voltage (VCC = 3.0V) Output Low Voltage (VCC = 1.8V) o c i t n Test Conditions fSCL = 100 kHz VIN = GND or VCC VIN = GND to VCC u n d e Min –1 a P Units Cycles/Byte Years Volts mA Max 3 1 10 10 VCC x 0.3 VCC + 0.5 0.4 0.5 t r mA µA µA µA V V V V Typ Units VOUT = GND to VCC VCC x 0.7 IOL = 3 mA IOL = 1.5 mA Input Capacitance (A0, A1, A2, SCL, WP) Note: (1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns. (2) Output shorted for no more than one second. No more than one output shorted at a time. (3) These parameter are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100 and JEDEC test methods. (4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V. (5) Maximum standby current (ISB ) = 10µA for the Automotive and Extended Automotive temperature range. Doc. No. 1026, Rev. J 2 CAT24WC164 A.C. CHARACTERISTICS VCC = +1.8V to +5.5V, unless otherwise specified. Read & Write Cycle Limits Symbol Parameter 1.8 V - 5.5 V Min FSCL TI(1) tAA tBUF(1) tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR(1) tF (1) 2.5 V - 5.5 V Min Max 400 200 Units Max 100 200 3.5 Clock Frequency Noise Suppression Time Constant at SCL, SDA Inputs SCL Low to SDA Data Out and ACK Out Time the Bus Must be Free Before a New Transmission Can Start Start Condition Hold Time Clock Low Period Clock High Period Start Condition Setup Time (for a Repeated Start Condition) Data In Hold Time Data In Setup Time 4.7 4 4.7 4 1.2 SDA and SCL Rise Time SDA and SCL Fall Time tSU:STO tDH Stop Condition Setup Time Data Out Hold Time Power-Up Timing(1)(2) Symbol tPUR tPUW Write Cycle Limits Symbol tWR The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle, the bus is D Parameter Power-up to Read Operation Power-up to Write Operation o c i t n u n 0 50 4 100 4.7 d e 1.2 0.6 0.6 0 50 1 300 0.6 100 Min Typ 0.6 a P 1 0.3 300 Max 1 1 t r kHz ns µs µs µs µs µs µs ns ns µs ns µs ns Units ms ms Parameter Write Cycle Time Min Typ Max 5 Units ms interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address. Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. 3 Doc. No. 1026, Rev. J CAT24WC164 FUNCTIONAL DESCRIPTION The CAT24WC164 supports the I 2 C Bus data transmission protocol. This Inter-Integrated Circuit Bus protocol defines any device that sends data to the bus to be a transmitter and any device receiving data to be a receiver. Data transfer is controlled by the Master device which generates the serial clock and all START and STOP conditions for bus access. The CAT24WC164 operates as a Slave device. Both the Master and Slave devices can operate as either transmitter or receiver, but the Master device controls which mode is activated. A maximum of 8 devices may be connected to the bus as determined by the device address inputs A0, A1, and A2. PIN DESCRIPTIONS SCL: Serial Clock The CAT24WC164 serial clock input pin is used to clock all data transfers into or out of the device. This is an input pin. SDA: Serial Data/Address The CAT24WC164 bidirectional serial data/address pin is used to transfer data into and out of the device. The SDA pin is an open drain output and can be wire-ORed with other open drain or open collector outputs. A0, A1, A2: Device Address Inputs These inputs set device address when cascading multiple devices. When these pins are left floating the default values are zeros. A maximum of eight devices can be cascaded. If only one CAT24WC164 is addressed on the bus, all three Figure 1. Bus Timing tF tLOW tHIGH tLOW tR SCL tSU:STA tHD:STA SDA IN SDA OUT Figure 2. Write Cycle Timing SCL SDA Figure 3. Start/Stop Timing D is SDA SCL 8TH BIT BYTE n o c START BIT i t n tAA tHD:DAT u n tDH tWR tSU:DAT d e a P tSU:STO tBUF t r ACK STOP CONDITION START CONDITION ADDRESS STOP BIT Doc. No. 1026, Rev. J 4 CAT24WC164 address pins (A0, A1and A2) can be left floating or connected to VSS. The CAT24WC164 can be made compatible with the CAT24WC16 by tying A2, A1 and A0 to VSS or by leaving A2, A1 and A0 float. WP: Write Protect If the WP pin is tied to VCC the entire memory array becomes Write Protected (READ only). When the WP pin is tied to VSS or left floating normal read/write operations are allowed to the device. DEVICE ADDRESSING The bus Master begins a transmission by sending a START condition. The Master then sends the address of the particular slave device it is requesting. The most significant bit of the 8-bit slave address is fixed as 1. (see Fig. 5). The next three significant bits (A2, A1, A0) are the device address bits and define which device or which part of the device the Master is accessing (The A1 bit must be the compliment of the A1 input pin signal). Up to eight CAT24WC164 devices may be individually addressed by the system. The next three bits are used as the three most significant bits of the data word address. The last bit of the slave address specifies whether a Read or Write operation is to be performed. When this bit is set to 1, a Read operation is selected, and when set to 0, a Write operation is selected. After the Master sends a START condition and the slave address byte, the CAT24WC164 monitors the bus and responds with an acknowledge (on the SDA line) when its address matches the transmitted slave address. The CAT24WC164 then performs a Read or Write operation depending on the state of the R/W bit. Acknowledge I2C BUS PROTOCOL The following defines the features of the I2C bus protocol: (1) Data transfer may be initiated only when the bus is not busy. (2) During a data transfer, the data line must remain stable whenever the clock line is high. Any changes in the data line while the clock line is high will be interpreted as a START or STOP condition. START Condition The START Condition precedes all commands to the device, and is defined as a HIGH to LOW transition of SDA when SCL is HIGH. The CAT24WC164 monitor the SDA and SCL lines and will not respond until this condition is met. STOP Condition A LOW to HIGH transition of SDA when SCL is HIGH determines the STOP condition. All operations must end with a STOP condition. Figure 4. Acknowledge Timing is D o c SCL FROM MASTER i t n 1 u n After a successful data transfer, each receiving device is required to generate an acknowledge. The Acknowledging device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data. The CAT24WC164 responds with an acknowledge after receiving a START condition and its slave address. If the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8bit byte. d e 8 a P t r 9 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER START ACKNOWLEDGE 5 Doc. No. 1026, Rev. J CAT24WC164 When the CAT24WC164 is in a READ mode it transmits 8 bits of data, releases the SDA line, and monitors the line for an acknowledge. Once it receives this acknowledge, the CAT24WC164 will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a STOP condition. address bits by one. The high order bits remain unchanged. If the Master transmits more than sixteen bytes prior to sending the STOP condition, the address counter ‘wraps around ’ , and previously transmitted data will be overwritten. Once all sixteen bytes are received and the STOP condition has been sent by the Master, the internal programming cycle begins. At this point all received data is written to the CAT24WC164 in a single write cycle. Acknowledge Polling WRITE OPERATIONS Byte Write In the Byte Write mode, the Master device sends the START condition and the slave address information (with the R/W bit set to zero) to the Slave device. After the Slave generates an acknowledge, the Master sends the remainder of the byte address that is to be written into the address pointer of the CAT24WC164. After receiving another acknowledge from the Slave, the Master device transmits the data byte to be written into the addressed memory location. The CAT24WC164 acknowledge once more and the Master generates the STOP condition, at which time the device begins its internal programming cycle to nonvolatile memory. While this internal cycle is in progress, the device will not respond to any request from the Master device. Page Write The CAT24WC164 writes up to 16 bytes of data in a single write cycle, using the Page Write operation. The Page Write operation is initiated in the same manner as the Byte Write operation, however instead of terminating after the initial word is transmitted, the Master is allowed to send up to fifteen additional bytes. After each byte has been transmitted the CAT24WC164 will respond with an acknowledge, and internally increment the low order Figure 5. Slave Address Bits is D o c 1 i t n A2 A1 u n A0 a10 The disabling of the inputs can be used to take advantage of the typical write cycle time. Once the stop condition is issued to indicate the end of the host’s write operation, the CAT24WC164 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation. If the CAT24WC164 is still busy with the write operation, no ACK will be returned. If the CAT24WC164 has completed the write operation, an ACK will be returned and the host can then proceed with the next read or write operation. WRITE PROTECTION The Write Protection feature allows the user to protect against inadvertent programming of the memory array. If the WP pin is tied to VCC, the entire memory array is protected and becomes read only. The CAT24WC164 will accept both slave and byte addresses, but the memory location accessed is protected from programming by the device’s failure to send an acknowledge after the first byte of data is received. d e a P t r CAT24WC164 a9 a8 R/W ** a8, a9 and a10 correspond to the address of the memory array address word. *** A0, A1 and A2 must compare to its corresponding hard wired input pins (pins 1, 2 and 3). Doc. No. 1026, Rev. J 6 CAT24WC164 READ OPERATIONS The READ operation for the CAT24WC164 is initiated in the same manner as the write operation with the one exception that the R/W bit is set to a one. Three different READ operations are possible: Immediate Address READ, Selective READ and Sequential READ. Immediate Address Read The device address counter contains the address of the last byte accessed, incremented by one. In other words, if the last READ or WRITE access was to address N, the READ immediately following would access data from address N+1. If N=2047, then the counter will 'wrap around' to addrss 0 and continue to clock out data. After the CAT24WC164 receives its slave address information (with the R/W bit set to one), it issues an acknowledge, then transmits the 8-bit byte requested. The master device does not send an acknowledge but will generate a STOP condition. Selective Read Selective READ operations allow the Master device to select at random any memory location for a READ operation. The Master device first performs a ‘dummy’ write operation by sending the START condition, slave address and byte address of the location it wishes to read. After the CAT24WC164 acknowledge the word address, the Master device resends the START condition and the slave address, this time with the R/W bit set to one. The CAT24WC164 then responds with its acknowledge and sends the 8-bit byte requested. The master device does not send an acknowledge but will generate a STOP condition. Sequential Read The Sequential READ operation can be initiated by either the immediate Address READ or Selective READ operations. After the CAT24WC164 sends initial 8-bit byte requested, the Master will respond with an acknowledge which tells the device it requires more data. The CAT24WC164 will continue to output an 8-bit byte for each acknowledge sent by the Master. The operation is terminated when the Master fails to respond with an acknowledge, thus sending the STOP condition. The data being transmitted from the CAT24WC164 is outputted sequentially with data from address N followed by data from address N+1. The READ operation address counter increments all of the CAT24WC164 address bits so that the entire memory array can be read during one operation. If more than the 2047 bytes are read out, the counter will “wrap around” and continue to clock out data bytes. Figure 6. Byte Write Timing BUS ACTIVITY: MASTER Figure 7. Page Write Timing S T A R T is D BUS ACTIVITY: MASTER SDA LINE o c S T A R T SDA LINE S i t n SLAVE ADDRESS u n BYTE ADDRESS d e DATA A C K a P S T O P t r P A C K A C K SLAVE ADDRESS BYTE ADDRESS (n) DATA n DATA n+1 DATA n+15 S T O P P S A C K A C K A C K A C K A C K NOTE: IN THIS EXAMPLE n = XXXX 0000(B); X = 1 or 0 7 Doc. No. 1026, Rev. J CAT24WC164 Figure 8. Immediate Address Read Timing BUS ACTIVITY: MASTER SDA LINE S T A R T S SLAVE ADDRESS S T O P P A C K DATA N O A C K SCL 8 9 SDA 8TH BIT DATA OUT NO ACK Figure 9. Selective Read Timing S T A R T BUS ACTIVITY: MASTER SDA LINE SLAVE ADDRESS S Figure 10. Sequential Read Timing BUS ACTIVITY: MASTER SDA LINE SLAVE ADDRESS is D o c A C K i t n A C K A C K BYTE ADDRESS (n) u n S T A R T S A C K d e A C K STOP a P S T O P P N O A C K t r SLAVE ADDRESS DATA n DATA n DATA n+1 DATA n+2 DATA n+x S T O P P A C K A C K N O A C K Doc. No. 1026, Rev. J 8 CAT24WC164 8-LEAD 300 MIL WIDE PLASTIC DIP (P, L) 0.245 (6.17) 0.295 (7.49) 0.355 (9.02) 0.400 (10.16) 0.120 (3.05) 0.150 (3.81) 0.180 (4.57) MAX 0.300 (7.62) 0.325 (8.26) 0.015 (0.38) 0.110 (2.79) 0.150 (3.81) 0.100 (2.54) BSC 0.045 (1.14) 0.060 (1.52) 0.014 (0.36) 0.022 (0.56) Notes: 1. Complies with JEDEC Publication 95 MS001 dimensions; however, some of the dimensions may be more stringent. 2. All linear dimensions are in inches and parenthetically in millimeters. 8-LEAD 150 MIL WIDE SOIC (J, W) is D o c 0.1890 (4.80) 0.1968 (5.00) i t n 0.0532 (1.35) 0.0688 (1.75) 0.0040 (0.10) 0.0098 (0.25) u n d e 0.310 (7.87) 0.380 (9.65) a P t r 0.1497 (3.80) 0.1574 (4.00) 0.2284 (5.80) 0.2440 (6.20) 0.0099 (0.25) X 45 0.0196 (0.50) 0.0075 (0.19) 0.0098 (0.25) 0 —8 0.016 (0.40) 0.050 (1.27) 0.050 (1.27) BSC 0.013 (0.33) 0.020 (0.51) Notes: 1. Complies with JEDEC publication 95 MS-012 dimensions; however, some dimensions may be more stringent. 2. All linear dimensions are in inches and parenthetically in millimeters. 9 Doc. No. 1026, Rev. J CAT24WC164 8 LEAD MSOP (R, Z) 0.0150 0.0110 0.38 0.28 0.1970 0.1890 5.00 4.80 S 0.0256 [0.65] BSC 0.1220 0.1142 3.10 2.90 0.0433 [1.10] MAX. 0.0276 0.0157 0.70 0.40 Notes: (1) All dimensions are in mm Angles in degrees. 2 Does not include Mold Flash, Protrusion or Gate Burrs. Mold Flash, Protrusions or Gate Burrs shall not exceed 0.15 mm. per side. 3 Does not include Interlead Flash orProtrusion. Interlead Flash or Protrusion shall not exceed 0.25 mm per side. 4 Does not include Dambar Protrusion, allowable Dambar Protrusion shall be 0.08 mm. (5) This part is compliant with JEDEC Specification MO-187 Variations AA. (6) Lead span/stand off height/coplanarity are considered as special characteristics. (S) (7) Controlling dimensions in inches. [mm] D is 0.1220 0.1142 o c 3.10 2.90 0.039 [0.10] MAX. i t n S 0˚ - 6˚ u n 0.0059 0.0020 0.15 0.05 0.0091 0.0051 WITH d e 0.0374 0.0295 S 0.23 0.13 PLATING a P 0.38 0.28 t r 0.95 0.75 0.0150 0.0110 WITH PLATING 0.0050 [0.127] BASE METAL 0.0118 [0.30] REF. SECTION A - A Doc. No. 1026, Rev. J 10 CAT24WC164 8-LEAD TSSOP (U,Y) is D o c i t n u n d e a P t r 11 Doc. No. 1026, Rev. J CAT24WC164 ORDERING INFORMATION Prefix CAT Device # 24WC164 Suffix J I -1.8 TE13 Rev F(2) Optional Company ID Product Number 24WC164: 16K Temperature Range I = Industrial (-40 to 85 C) A = Automotive (-40 to 105 C)* E = Extended (-40 to 125 C) Tape & Reel Package P: PDIP J: SOIC (JEDEC) U: TSSOP R: MSOP L: PDIP (Lead free, Halogen free) W: SOIC (Lead free, Halogen free) Y: TSSOP (Lead free, Halogen free) Z: MSOP (Lead free, Halogen free) Operating Voltage Blank: 2.5V - 5.5V 1.8: 1.8V - 5.5V Notes: (1) The device used in the above example is a CAT24WC164JI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 5.5 Volt Operating Voltage, Tape & Reel). (2) Product die revision letter is marked on top of the package as a suffix to the production date code (e.g. AYWWF). For additional information, please contact your Catalyst sales office. is D Doc. No. 1026, Rev. J o c i t n u n d e a P Die Revision t r 12 CAT24WC164 REVISION HISTORY Date 12/29/2003 Rev. F Reason Added 8-pin MSOP package to Features section Deleted 2.5V - 6.0V from AC Characteristics Changed 4.5V - 5.5V to 2.5V - 6.0V in AC Characteristics Changed max to 5 in Write Cycle Limits (tWR) Added overbar to A1 in Figure 5 (slave address bits) 7/23/2004 8/3/2004 03/10/2005 04/21/2005 G H I J Added die revision to Ordering Information Update DC Operating Characteristics table & notes Update Ordering Information Edit Features Edit Pin Functions Edit Reliability Characteristics Edit D.C. Operating Characteristics Edit A.C. Characteristics Add Package Dimensions Edit Ordering Information Copyrights, Trademarks and Patents Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: DPP ™ AE2 ™ Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000. CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES. Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur. Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete. is D o c i t n u n d e a P t r Catalyst Semiconductor, Inc. Corporate Headquarters 1250 Borregas Avenue Sunnyvale, CA 94089 Phone: 408.542.1000 Fax: 408.542.1200 www.catalyst-semiconductor.com Publication #: Revison: Issue date: 1026 J 04/21/05 13 Doc. No. 1026, Rev. J