CAT24WC65PTE13D

CAT24WC33/65 32K/64K-Bit I2C Serial CMOS EEPROM FEATURES I 400 KHz I2C Bus Compatible* I 1.8 to 5.5 Volt Read and Write Operation I Cascadable for up to Eight Devices I 32/64-Byte Page Write Buffer I Self-Timed Write Cycle with Auto-Clear I 8-Pin DIP or 8-Pin SOIC I Schmitt Trigger Inputs for Noise Protection I Commercial, Industrial and Automotive Tem- perature Ranges I Write Protection I 1,000,000 Program/Erase Cycles I 100 Year Data Retention –Bottom 1/4 Array Protected When WP at VIH DESCRIPTION The CAT24WC33/65 is a 32K/64K-bit Serial CMOS E2PROM internally organized as 4096/8192 words of 8 bits each. Catalyst’s advanced CMOS technology substantially reduces device power requirements. The CAT24WC33/65 features a 32-byte page write buffer. The device operates via the I2C bus serial interface and is available in 8-pin DIP or 8-pin SOIC packages. PIN CONFIGURATION DIP Package (P, L) A0 A1 A2 VSS 1 2 3 4 8 7 6 5 SOIC Package (J, W, K, X) A0 A1 A2 1 2 3 4 8 7 6 5 VCC WP SCL SDA PIN FUNCTIONS Pin Name A0, A1, A2 SDA SCL WP VCC VSS i D VSS c s Ground i t n o VCC WP SCL SDA u n VCC VSS SDA WP BLOCK DIAGRAM DOUT ACK SENSE AMPS SHIFT REGISTERS EXTERNAL LOAD d e START/STOP LOGIC CONTROL LOGIC a P ts r COLUMN DECODERS 256 WORD ADDRESS BUFFERS E2PROM XDEC 128/256 128/256 X 256 Function DATA IN STORAGE Device Address Inputs Serial Data/Address Serial Clock Write Protect +1.8V to +5.5V Power Supply SCL A0 A1 A2 STATE COUNTERS SLAVE ADDRESS COMPARATORS HIGH VOLTAGE/ TIMING CONTROL * Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol. © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 1 Doc. No. 1049, Rev. D CAT24WC33/65 ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias ................. –55°C to +125°C Storage Temperature ....................... –65°C to +150°C Voltage on Any Pin with Respect to Ground(1) ........... –2.0V to +VCC + 2.0V VCC with Respect to Ground ............... –2.0V to +7.0V Package Power Dissipation Capability (Ta = 25°C) ................................... 1.0W Lead Soldering Temperature (10 secs) ............ 300°C Output Short Circuit Current(2) ........................ 100mA RELIABILITY CHARACTERISTICS Symbol NEND(3) TDR(3) VZAP (3) *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Parameter Endurance Data Retention ESD Susceptibility Latch-up Min. 1,000,000 100 2000 100 Max. ILTH(3)(4) D.C. OPERATING CHARACTERISTICS VCC = +1.8V to +5.5V, unless otherwise specified. Symbol ICC ISB(5) ILI ILO VIL VIH VOL1 VOL2 Parameter Power Supply Current Standby Current (VCC = 5V) Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V Symbol CI/O(3) CIN (3) Note: (1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns. (2) Output shorted for no more than one second. No more than one output shorted at a time. (3) These parameter are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100 and JEDEC test methods. (4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V. (5) Maximum standby current (ISB ) = 10µA for the Automotive and Extended Automotive temperature range. i D Output Low Voltage (VCC = +3.0V) Output Low Voltage (VCC = +1.8V) c s i t n o Test Min. u n Limits Typ. Max. 8 6 d e Max. 3 1 10 10 µA µA µA V V V V 0.4 0.5 a P Units Volts mA Cycles/Byte Years ts r Units mA Test Conditions fSCL = 100 KHz VIN = GND or VCC VIN = GND to VCC VOUT = GND to VCC –1 VCC x 0.3 VCC + 0.5 VCC x 0.7 IOL = 3.0 mA IOL = 1.5 mA Units pF pF Conditions VI/O = 0V VIN = 0V Input/Output Capacitance (SDA) Input Capacitance (A0, A1, A2, SCL, WP) Doc. No. 1049, Rev. D 2 © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT24WC33/65 A.C. CHARACTERISTICS VCC = +1.8V to +5.5V, unless otherwise specified Output Load is 1 TTL Gate and 100pF Read & Write Cycle Limits CAT24WCXX-1.8 1.8V-5.5V Symbol FSCL TI (1) CAT24WCXX 2.5V-5.5V Min. Max. 100 200 3.5 4.7 4 4.5V-5.5V Min. Max. 400 Parameter Clock Frequency Noise Suppression Time Constant at SCL, SDA Inputs SCL Low to SDA Data Out and ACK Out Time the Bus Must be Free Before a New Transmission Can Start Start Condition Hold Time Clock Low Period Clock High Period Start Condition Setup Time (for a Repeated Start Condition) Data In Hold Time Data In Setup Time SDA and SCL Rise Time SDA and SCL Fall Time Data Out Hold Time Min. Max. 10 0 200 3.5 tAA tBUF (1) 4.7 4 4.7 4 4.7 tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF (1) (1) tSU:STO tDH Stop Condition Setup Time Power-Up Timing (1)(2) Symbol tPUR Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. Write Cycle Limits Symbol tWR i D tPUW c s Power-Up to Read Operation Power-Up to Write Operation i t n o Parameter u n 0 50 1 4 100 30 0 d e 4 4.7 0 50 4 100 4.7 a P 1.2 0.6 1.2 0.6 0.6 0 50 0.6 100 ts r Units kHz ns 200 1 µs µs µs µs µs µs ns ns 0.3 300 µs ns µs ns 1 300 Max. 1 1 Units ms ms Parameter Write Cycle Time Min. Typ. Max 10 Units ms The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address. © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 3 Doc No. 1049, Rev. D CAT24WC33/65 FUNCTIONAL DESCRIPTION The CAT24WC33/65 supports the I2C Bus data transmission protocol. This Inter-Integrated Circuit Bus protocol defines any device that sends data to the bus to be a transmitter and any device receiving data to be a receiver. The transfer is controlled by the Master device which generates the serial clock and all START and STOP conditions for bus access. The CAT24WC33/65 operates as a Slave device. Both the Master device and Slave device can operate as either transmitter or receiver, but the Master device controls which mode is activated. transfer all data into and out of the device. The SDA pin is an open drain output and can be wire-ORed with other open drain or open collector outputs. A0, A1, A2: Device Address Inputs These pins are hardwired or left unconnected (for hardware compatibility with CAT24WC16). When hardwired, up to eight CAT24WC33/65s may be addressed on a single bus system (refer to Device Addressing ). When the pins are left unconnected, the default values are zeros. PIN DESCRIPTIONS SCL: Serial Clock The serial clock input clocks all data transferred into or out of the device. SDA: Serial Data/Address The bidirectional serial data/address pin is used to Figure 1. Bus Timing tF tLOW SCL tSU:STA tHIGH WP: Write Protect This input, when tied to GND, allows write operations to the entire memory. For CAT24WC33/65 when this pin is tied to Vcc, the bottom 1/4 array of memory (locations 000H to 7FFH for the 24WC65 and locations 000H to 3FFH for 24WC33) is write protected . When left floating, memory is unprotected. tR SDA IN SDA OUT Figure 2. Write Cycle Timing SCL SDA Figure 3. Start/Stop Timing SDA i D c s SCL i t n o tHD:STA tHD:DAT tAA u n tLOW tDH tSU:DAT d e a P tSU:STO tBUF ts r 5020 FHD F03 8TH BIT BYTE n ACK tWR STOP CONDITION START CONDITION ADDRESS 5020 FHD F04 START BIT STOP BIT 5020 FHD F05 Doc. No. 1049, Rev. D 4 © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT24WC33/65 I2C BUS PROTOCOL The features of the I2C bus protocol are defined as follows: (1) Data transfer may be initiated only when the bus is not busy. (2) During a data transfer, the data line must remain stable whenever the clock line is high. Any changes in the data line while the clock line is high will be interpreted as a START or STOP condition. START Condition The START Condition precedes all commands to the device, and is defined as a HIGH to LOW transition of SDA when SCL is HIGH. The CAT24WC33/65 monitors the SDA and SCL lines and will not respond until this condition is met. STOP Condition A LOW to HIGH transition of SDA when SCL is HIGH determines the STOP condition. All operations must end with a STOP condition. compare to the hardwired input pins, A2, A1 and A0. The last bit of the slave address specifies whether a Read or Write operation is to be performed. When this bit is set to 1, a Read operation is selected, and when set to 0, a Write operation is selected. After the Master sends a START condition and the slave address byte, the CAT24WC33/65 monitors the bus and responds with an acknowledge (on the SDA line) when its address matches the transmitted slave address. The CAT24WC33/65 then performs a Read or Write operation depending on the state of the R/W bit. Acknowledge After a successful data transfer, each receiving device is required to generate an acknowledge. The Acknowledging device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data. The CAT24WC33/65 responds with an acknowledge after receiving a START condition and its slave address. If the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8-bit byte. DEVICE ADDRESSING The bus Master begins a transmission by sending a START condition. The Master sends the address of the particular slave device it is requesting. The four most significant bits of the 8-bit slave address are fixed as 1010 (Fig. 5). The next three bits (A2, A1, A0) are the device address bits; up to eight 32K/64K devices may to be connected to the same bus. These bits must Figure 4. Acknowledge Timing i D DATA OUTPUT FROM TRANSMITTER c s SCL FROM MASTER i t n o 1 START u n When the CAT24WC33/65 begins a READ mode it transmits 8 bits of data, releases the SDA line, and monitors the line for an acknowledge. Once it receives this acknowledge, the CAT24WC33/65 will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a STOP condition. The master must then issue a stop condition to return the CAT24WC33/65 to the standby power mode and place the device in a known state. d e 8 a P 9 ts r DATA OUTPUT FROM RECEIVER ACKNOWLEDGE 5020 FHD F06 Figure 5. Slave Address Bits 1 0 1 0 A2 A1 A0 R/W 5027 FHD F07 © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 5 Doc No. 1049, Rev. D CAT24WC33/65 WRITE OPERATIONS Byte Write In the Byte Write mode, the Master device sends the START condition and the slave address information (with the R/W bit set to zero) to the Slave device. After the Slave generates an acknowledge, the Master sends two 8-bit address words that are to be written into the address pointers of the CAT24WC33/65. After receiving another acknowledge from the Slave, the Master device transmits the data to be written into the addressed memory location. The CAT24WC33/65 acknowledges once more and the Master generates the STOP condition. At this time, the device begins an internal programming cycle to nonvolatile memory. While the cycle is in progress, the device will not respond to any request from the Master device. Page Write The CAT24WC33/65 writes up to 32/64 bytes of data, in a single write cycle, using the Page Write operation. CAT24WC33/65, Die Revision B = 32 Byte page. CAT24WC65, Die Revision D = 64 Byte page. The page write operation is initiated in the same manner as the byte write operation, however instead of terminating after the initial byte is transmitted, the Master is allowed to send up to 31/63 additional bytes. After each byte has been transmitted, CAT24WC33/65 will respond with an acknowledge, and internally increment the five low order address bits by one. The high order bits remain unchanged. Figure 6. Byte Write Timing If the Master transmits more than 32/64 bytes before sending the STOP condition, the address counter ‘wraps around’, and previously transmitted data will be overwritten. When all 32/64 bytes are received, and the STOP condition has been sent by the Master, the internal programming cycle begins. At this point, all received data is written to the CAT24WC33/65 in a single write cycle. Acknowledge Polling Disabling of the inputs can be used to take advantage of the typical write cycle time. Once the stop condition is issued to indicate the end of the host's write operation, CAT24WC33/65 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation. If CAT24WC33/65 is still busy with the write operation, no ACK will be returned. If CAT24WC33/65 has completed the write operation, an ACK will be returned and the host can then proceed with the next read or write operation. WRITE PROTECTION BUS ACTIVITY: MASTER Figure 7. Page Write Timing S T A R T BUS ACTIVITY: MASTER SDA LINE i D S c s SDA LINE S SLAVE ADDRESS A C K S T A R T i t n o SLAVE ADDRESS X XX * A C K A C K u n A C K DATA The Write Protection feature allows the user to protect against inadvertent programming of the memory array. If the WP pin is tied to VCC, the bottom 1/4 of the memory array (locations 000H to 7FFH for the 24WC65 and locations 000H to 3FFH for 24WC33) is protected and becomes read only. The CAT24WC33/65 will accept both slave and byte addresses, but the memory location d e A C K a P S T O P P A C K ts r BYTE ADDRESS A15–A8 A7–A0 DATA 24WC33/65 F08 BYTE ADDRESS A15–A8 A7–A0 X XX * A C K DATA n DATA n+31 S T O P P A C K A C K A C K A C K 24WC33/65 F09 * = Don't care bit for 24WC33 X= Don't care bit Doc. No. 1049, Rev. D 6 © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT24WC33/65 accessed is protected from programming by the device’s failure to send an acknowledge after the first byte of data is received. READ operation. The Master device first performs a ‘dummy’ write operation by sending the START condition, slave address and byte addresses of the location it wishes to read. After CAT24WC33/65 acknowledges, the Master device sends the START condition and the slave address again, this time with the R/W bit set to one. The CAT24WC33/65 then responds with its acknowledge and sends the 8-bit byte requested. The master device does not send an acknowledge but will generate a STOP condition. Sequential Read READ OPERATIONS The READ operation for the CAT24WC33/65 is initiated in the same manner as the write operation with one exception, that R/W bit is set to one. Three different READ operations are possible: Immediate/Current Address READ, Selective/Random READ and Sequential READ. Immediate/Current Address Read The CAT24WC33/65’s address counter contains the address of the last byte accessed, incremented by one. In other words, if the last READ or WRITE access was to address N, the READ immediately following would access data from address N+1. If N=E (where E=4095 for 24WC33 and E=8191 for 24WC65), then the counter will ‘wrap around’ to address 0 and continue to clock out data. After the CAT24WC33/65 receives its slave address information (with the R/W bit set to one), it issues an acknowledge, then transmits the 8 bit byte requested. The master device does not send an acknowledge, but will generate a STOP condition. Selective/Random Read The Sequential READ operation can be initiated by either the Immediate Address READ or Selective READ operations. After the CAT24WC33/65 sends the initial 8bit byte requested, the Master will respond with an acknowledge which tells the device it requires more data. The CAT24WC33/65 will continue to output an 8bit byte for each acknowledge sent by the Master. The operation will terminate when the Master fails to respond with an acknowledge, thus sending the STOP condition. The data being transmitted from CAT24WC33/65 is outputted sequentially with data from address N followed by data from address N+1. The READ operation address counter increments all of the CAT24WC33/65 address bits so that the entire memory array can be read during one operation. If more than E (where E=4095 for 24WC33 and E=8191 for 24WC65) bytes are read out, the counter will ‘wrap around’ and continue to clock out data bytes. Selective/Random READ operations allow the Master device to select at random any memory location for a Figure 8. Immediate Address Read Timing i D c s SCL SDA i t n o BUS ACTIVITY: MASTER SDA LINE S T A R T S 8 8TH BIT DATA OUT u n A C K d e DATA S T O P P N O A C K a P ts r SLAVE ADDRESS 9 NO ACK STOP 24WC33/65 F10 © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 7 Doc No. 1049, Rev. D CAT24WC33/65 Figure 9. Selective Read Timing S T A R T S A C K S T A R T S A C K A C K A C K N O A C K S T O P P BUS ACTIVITY: MASTER SDA LINE SLAVE ADDRESS BYTE ADDRESS A15–A8 A7–A0 XXX * SLAVE ADDRESS DATA * = Don't care for 24WC33 X= Don't care bit Figure 10. Sequential Read Timing BUS ACTIVITY: MASTER SDA LINE A C K A C K SLAVE ADDRESS DATA n DATA n+1 DATA n+2 i D Doc. No. 1049, Rev. D c s i t n o u n A C K d e A C K a P DATA n+x ts r 24WC33/65 F11 S T O P P N O A C K 5020 FHD F12 8 © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT24WC33/65 8-LEAD 300 MIL WIDE PLASTIC DIP (P, L) 0.245 (6.17) 0.295 (7.49) 0.355 (9.02) 0.400 (10.16) 0.120 (3.05) 0.150 (3.81) 0.180 (4.57) MAX 0.300 (7.62) 0.325 (8.26) 0.015 (0.38) 0.110 (2.79) 0.150 (3.81) 0.100 (2.54) BSC 0.045 (1.14) 0.060 (1.52) 0.014 (0.36) 0.022 (0.56) Notes: 1. Complies with JEDEC Publication 95 MS001 dimensions; however, some of the dimensions may be more stringent. 2. All linear dimensions are in inches and parenthetically in millimeters. 8-LEAD 150 MIL WIDE SOIC (J, W) i D c s i t n o u n 0.1497 (3.80) 0.1574 (4.00) 0 —8 d e 0.310 (7.87) 0.380 (9.65) a P ts r 0.2284 (5.80) 0.2440 (6.20) 0.1890 (4.80) 0.1968 (5.00) 0.0099 (0.25) X 45 0.0196 (0.50) 0.0532 (1.35) 0.0688 (1.75) 0.0075 (0.19) 0.0098 (0.25) 0.050 (1.27) BSC 0.013 (0.33) 0.020 (0.51) 0.0040 (0.10) 0.0098 (0.25) 0.016 (0.40) 0.050 (1.27) Notes: 1. Complies with JEDEC publication 95 MS-012 dimensions; however, some dimensions may be more stringent. 2. All linear dimensions are in inches and parenthetically in millimeters. © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 9 Doc No. 1049, Rev. D CAT24WC33/65 8-LEAD 210 MIL WIDE SOIC (K, X) 0.205 (5.20) 0.213 (5.40) 0.303 (7.70) 0.318 (8.10) 0.0267 (0.68) 0.0303 (0.77) 0.205 (5.15) 0.210 (5.35) 0.080 (2.03) MAX 0.046 (1.17) 0.054 (1.37) 0.0137 (0.35) 0.0177 (0.45) 4 REF Note: 1. All linear dimensions are in inches and parenthetically in millimeters. i D Doc. No. 1049, Rev. D c s i t n o u n d e 0.025 (0.65) a P 0.008 (0.20) ts r 10 © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT24WC33/65 ORDERING INFORMATION Prefix CAT Device # 24WC33 K Suffix I -1.8 TE13 Rev D(2) Optional Company ID Product Number 24WC33: 32K 24WC65: 64K Temperature Range Blank = Commercial (0˚ to 70˚C) I = Industrial (-40˚ to 85˚C) A = Automotive (-40˚ to 105˚C) * E = Extended (-40˚ to 125˚C) Tape & Reel Package P: PDIP K: SOIC (EIAJ) J: SOIC (JEDEC) L: PDIP (Lead free, Halogen free) X: SOIC (EIAJ, Lead free, Halogen free) W: SOIC (JEDEC, Lead free, Halogen free) Operating Voltage Blank: 2.5V - 5.5V 1.8: 1.8V - 5.5V Notes: (1) The device used in the above example is a CAT24WC33KI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 5.5 Volt Operating Voltage, Tape & Reel) (2) Product die revision letter is marked on top of the package as a suffix to the production date code (e.g., AYWWB). For additional information, please contact your Catalyst sales office. i D c s i t n o u n d e a P Die Revision 24WC33: B, D 24WC65: B, D ts r © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 11 Doc No. 1049, Rev. D REVISION HISTORY Date 7/8/2004 7/30/2004 10/31/2005 Rev. B C D Reason Added die revision to Ordering Information Updated DC Operating Charactristics and notes Update Ordering Information Copyrights, Trademarks and Patents Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: DPP ™ AE2 ™ Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000. 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Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete. i D c s i t n o u n d e a P ts r Catalyst Semiconductor, Inc. Corporate Headquarters 1250 Borregas Avenue Sunnyvale, CA 94089 Phone: 408.542.1000 Fax: 408.542.1200 www.catalyst-semiconductor.com Publication #: Revison: Issue date: 1049 D 10/31/05