CAT24WC66

CAT24WC66 64K-bit I2C Serial EEPROM with Partial Array Write Protection FEATURES 400kHz I2C Bus 1.8V to 5.5V supply voltage range Cascadable for up to eight devices 32-byte page write buffer Self-timed write cycle with auto-clear Schmitt trigger inputs for noise protection Write protection — Top 1/4 array protected when WP at VIH 1,000,000 program/erase cycles 100 year data retention Industrial and automotive temperature ranges RoHS-compliant packages DESCRIPTION The CAT24WC66 is a 64K-bit Serial CMOS EEPROM internally organized as 8192 words of 8 bits each. Catalyst’s advanced CMOS technology substantially reduces device power requirements. The CAT24WC66 features a 32-byte page write buffer. The device operates via the I2C bus serial interface and is available in 8-pin DIP or 8-pin SOIC packages. For Ordering Information details, see page 12. PIN CONFIGURATION DIP Package (L) A0 A1 A2 VSS 1 2 3 4 8 7 6 5 VCC WP SCL SDA SOIC Package (W, X) A0 A1 A2 VSS 1 2 3 4 8 7 6 5 VCC WP SCL SDA FUNCTIONAL SYMBOL VCC SCL A2, A1, A0 WP CAT24CW66 SDA PIN FUNCTION Pin Name A0, A1, A2 SDA SCL WP VCC VSS Function Device Address Inputs Serial Data/Address Serial Clock Write Protect Power Supply Ground VSS * Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol. © 2006 Catalyst Semiconductor, Inc. Characteristics subject to change without notice 1 Doc. No. 1037 Rev. J CAT24WC66 ABSOLUTE MAXIMUM RATINGS(1) Parameters Temperature Under Bias Storage Temperature Voltage on any Pin with Respect to Ground VCC with Respect to Ground Package Power Dissipation Capability (TA = 25°C) Lead Soldering Temperature (10 secs) Output Short Circuit Current (3) (2) Ratings –55 to +125 –65 to +150 –2.0 to VCC + 2.0 –2.0 to 7.0 1.0 300 100 Units ºC ºC V V W ºC mA REABILITY CHARACTERISTICS Symbol NEND(4) TDR(4) VZAP ILTH (4) (4)(5) Parameter Endurance Data Retention ESD Susceptibility Latch-up Reference Test Method MIL-STD-883, Test Method 1033 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 3015 JEDEC Standard 17 Min 1,000,000 100 2000 100 Max Units Cycles/Byte Years Volts mA D.C. OPERATING CHARACTERISTICS VCC = 1.8V to 5.5V, unless otherwise specified. Symbol ICC ISB(6) ILI ILO VIL VIH VOL1 VOL2 Parameter Power Supply Current Standby Current (VCC = 5V) Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage (VCC = +3.0V) Output Low Voltage(VCC = +1.8V) IOL = 3.0 mA IOL = 1.5 mA Test Conditions fSCL = 100kHz VIN = GND or VCC VIN = GND to VCC VOUT = GND to VCC -1 VCC x 0.7 Min Typ Max 3 1 10 10 VCC x 0.3 VCC + 0.5 0.4 0.5 Units mA µA µA µA V V V V CAPACITANCE TA = 25ºC, f = 1.0MHz, VCC = 5V Symbol CI/O(4) CIN (4) Parameter Input/Output Capacitance (SDA) Input Capacitance (A0, A1, A2, SCL, WP) Conditions VI/O = 0V VIN = 0V Min Typ Max 8 6 Units pF pF Notes: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. (2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns. (3) Output shorted for no more than one second. No more than one output shorted at a time. (4) This parameter is tested initially and after a design or process change that affects the parameter. (5) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V. (6) Maximum standby current (ISB) = 10µA for the Automotive and Extended Automotive temperature range. Doc. No. 1037 Rev. J 2 © 2006 Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT24WC66 AC CHARACTERISTICS VCC = 1.8V to 5.5V, unless otherwise specified. Output Load is 1TTL Gate and 100pF. Memory Read & Write Cycle Limits Symbol FSCL TI(1) tAA tBUF(1) tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF (1) (1) Parameter Clock Frequency Noise Suppression Time Constant at SCL, SDA Inputs SCL Low to SDA Data Out and ACK Out Time the Bus Must be Free Before a New Transmission Can Start Start Condition Hold Time Clock Low Period Clock High Period Start Condition Setup Time (for a Repeated Start Condition) Data In Hold Time Data In Setup Time SDA and SCL Rise Time SDA and SCL Fall Time Stop Condition Setup Time Data Out Hold Time 1.8V - 2.5V Min Max 100 200 3.5 4.7 4 4.7 4 4.7 0 50 1 300 4 100 4.5V - 5.5V Min Max 400 200 1 1.2 0.6 1.2 0.6 0.6 0 50 0.3 300 0.6 100 Units kHz ns µs µs µs µs µs µs ns ns µs ns µs ns tSU:STO tDH Power-Up Timing (1) (2) Symbol tPUR tPUW Parameter Power-Up to Read Operation Power-Up to Write Operation Min Typ Max 1 1 Units ms ms Notes: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. Write Cycle Limits Symbol tWR Parameter Write Cycle Time Min Typ Max 10 Units ms The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address. © 2006 Catalyst Semiconductor, Inc. Characteristics subject to change without notice 3 Doc. No. 1037 Rev. J CAT24WC66 FUNCTIONAL DESCRIPTION The CAT24WC66 supports the I2C Bus data transmission protocol. This Inter-Integrated Circuit Bus protocol defines any device that sends data to the bus to be a transmitter and any device receiving data to be a receiver. The transfer is controlled by the Master device which generates the serial clock and all START and STOP conditions for bus access. The CAT24WC66 operates as a Slave device. Both the Master device and Slave device can operate as either transmitter or receiver, but the Master device controls which mode is activated. pin is an open drain output and can be wire-ORed with other open drain or open collector outputs. A0, A1, A2: Device Address Inputs These pins are hardwired or left unconnected (for hardware compatibility with CAT24WC16). When hardwired, up to eight CAT24WC66 devices may be addressed on a single bus system (refer to Device Addressing). When the pins are left unconnected, the default values are zeros. WP: Write Protect This input, when tied to GND, allows write operations to the entire memory. When this pin is tied to VCC, the top 1/4 array of memory is write protected. When left floating, memory is unprotected. PIN DESCRIPTION SCL: Serial Clock The serial clock input clocks all data transferred into or out of the device. SDA: Serial Data/Address The bidirectional serial data/address pin is used to transfer all data into and out of the device. The SDA Figure 1. Bus Timming tF tLOW SCL tSU:STA SDA IN tAA SDA OUT tHD:STA tHD:DAT tHIGH tR tLOW tSU:DAT tSU:STO tDH tBUF Figure 2. Write Cycle Timing SC L SDA 8TH BIT BYTE n ACK tWR STOP CONDITION START CONDITION ADDRESS Figure 3. Start/Stop Timing SDA SCL START BIT Doc. No. 1037 Rev. J STOP BIT 4 © 2006 Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT24WC66 I2C BUS PROTOCOL The features of the I2C bus protocol are defined as follows: (1) Data transfer may be initiated only when the bus is not busy. (2) During a data transfer, the data line must remain stable whenever the clock line is high. Any changes in the data line while the clock line is high will be interpreted as a START or STOP condition. START Condition The START Condition precedes all commands to the device, and is defined as a HIGH to LOW transition of SDA when SCL is HIGH. The CAT24WC66 monitors the SDA and SCL lines and will not respond until this condition is met. STOP Condition A LOW to HIGH transition of SDA when SCL is HIGH determines the STOP condition. All operations must end with a STOP condition. whether a Read or Write operation is to be performed. When this bit is set to 1, a Read operation is selected, and when set to 0, a Write operation is selected. After the Master sends a START condition and the slave address byte, the CAT24WC66 monitors the bus and responds with an acknowledge (on the SDA line) when its address matches the transmitted slave address. The CAT24WC66 then performs a Read or ¯¯ Write operation depending on the state of the R/W bit. Acknowledge After a successful data transfer, each receiving device is required to generate an acknowledge. The Acknowledging device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data. The CAT24WC66 responds with an acknowledge after receiving a START condition and its slave address. If the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8-bit byte. When the CAT24WC66 begins a READ mode it transmits 8 bits of data, releases the SDA line, and monitors the line for an acknowledge. Once it receives this acknowledge, the CAT24WC66 will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a STOP condition. The master must then issue a stop condition to return the CAT24WC66 to the standby power mode and place the device in a known state. DEVICE ADDRESSING The bus Master begins a transmission by sending a START condition. The Master sends the address of the particular slave device it is requesting. The four most significant bits of the 8-bit slave address are fixed as 1010 (Fig. 5). The next three bits (A2, A1, A0) are the device address bits; up to eight 64K devices may to be connected to the same bus. These bits must compare to the hardwired input pins, A2, A1 and A0. The last bit of the slave address specifies Figure 4. Acknowledge Timing SCL FROM MASTER 1 8 9 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER START ACKNOWLEDGE Figure 5. Slave Address Bits 1 0 1 0 A2 A1 A0 R/W DEVICE ADDRESS © 2006 Catalyst Semiconductor, Inc. Characteristics subject to change without notice 5 Doc. No. 1037 Rev. J CAT24WC66 WRITE OPERATIONS Byte Write In the Byte Write mode, the Master device sends the START condition and the slave address information ¯¯ (with the R/W bit set to zero) to the Slave device. After the Slave generates an acknowledge, the Master sends two 8-bit address words that are to be written into the address pointers of the CAT24WC66. After receiving another acknowledge from the Slave, the Master device transmits the data to be written into the addressed memory location. The CAT24WC66 acknowledges once more and the Master generates the STOP condition. At this time, the device begins an internal programming cycle to nonvolatile memory. While the cycle is in progress, the device will not respond to any request from the Master device. Page Write The CAT24WC66 writes up to 32 bytes of data, in a single write cycle, using the Page Write operation. The page write operation is initiated in the same manner as the byte write operation, however instead of terminating after the initial byte is transmitted, the Master is allowed to send up to 31 additional bytes. After each byte has been transmitted, CAT24WC66 will respond with an acknowledge, and internally increment the five low order address bits by one. The high order bits remain unchanged. If the Master transmits more than 32 bytes before sending the STOP condition, the address counter Figure 6. Byte Write Timing S T A R T S A C K S T O P P A C K A C K A C K ‘wraps around’, and previously transmitted data will be overwritten. When all 32 bytes are received, and the STOP condition has been sent by the Master, the internal programming cycle begins. At this point, all received data is written to the CAT24WC66 in a single write cycle. Acknowledge Polling Disabling of the inputs can be used to take advantage of the typical write cycle time. Once the stop condition is issued to indicate the end of the host's write operation, CAT24WC66 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation. If CAT24WC66 is still busy with the write operation, no ACK will be returned. If CAT24WC66 has completed the write operation, an ACK will be returned and the host can then proceed with the next read or write operation. WRITE PROTECTION The Write Protection feature allows the user to protect against inadvertent programming of the memory array. If the WP pin is tied to VCC, the top 1/4 of the memory array (locations 1800H to 1FFF) is protected and becomes read only. The CAT24WC66 will accept both slave and byte addresses, but the memory location accessed is protected from programming by the device’s failure to send an acknowledge after the first byte of data is received. BUS ACTIVITY: MASTER SDA LINE SLAVE ADDRESS BYTE ADDRESS A15–A8 A7–A0 X XX DATA Figure 7. Page Write Timing S T A R T S A C K S T O P P A C K A C K A C K A C K A C K A C K BUS ACTIVITY: MASTER SDA LINE SLAVE ADDRESS BYTE ADDRESS A15–A8 A7–A0 X XX DATA DATA n DATA n+31 X= Don't care bit Doc. No. 1037 Rev. J 6 © 2006 Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT24WC66 READ OPERATIONS The READ operation for the CAT24WC66 is initiated in the same manner as the write operation with one ¯¯ exception, that R/W bit is set to one. Three different READ operations are possible: Immediate/Current Address READ, Selective/Random READ and Se– quential READ. Immediate/Current Address Read The CAT24WC66’s address counter contains the address of the last byte accessed, incremented by one. In other words, if the last READ or WRITE access was to address N, the READ immediately following would access data from address N+1. If N=E (where E=8191), then the counter will ‘wrap around’ to address 0 and continue to clock out data. After the CAT24WC66 receives its slave address information ¯¯ (with the R/W bit set to one), it issues an acknowledge, then transmits the 8 bit byte requested. The master device does not send an acknowledge, but will generate a STOP condition. Selective/Random Read Selective/Random READ operations allow the Master device to select at random any memory location for a READ operation. The Master device first performs a ‘dummy’ write operation by sending the START condition, slave address and byte addresses of the location it wishes to read. After CAT24WC66 acknowledges, the Master device sends the START condition ¯¯ and the slave address again, this time with the R/W bit set to one. The CAT24WC66 then responds with its acknowledge and sends the 8-bit byte requested. The master device does not send an acknowledge but will generate a STOP condition. Sequential Read The Sequential READ operation can be initiated by either the Immediate Address READ or Selective READ operations. After the CAT24WC66 sends the initial 8-bit byte requested, the Master will respond with an acknowledge which tells the device it requires more data. The CAT24WC66 will continue to output an 8-bit byte for each acknowledge sent by the Master. The operation will terminate when the Master fails to respond with an acknowledge, thus sending the STOP condition. The data being transmitted from CAT24WC66 is outputted sequentially with data from address N followed by data from address N+1. The READ operation address counter increments all of the CAT24WC66 address bits so that the entire memory array can be read during one operation. If more than E (where E=8191) bytes are read out, the counter will ‘wrap around’ and continue to clock out data bytes. Figure 8. Immediate Address Read Timing S T A R T S A C K N O A C K S T O P P BUS ACTIVITY: MASTER SDA LINE SLAVE ADDRESS DATA SCL 8 9 SDA 8TH BIT DATA OUT NO ACK STOP © 2006 Catalyst Semiconductor, Inc. Characteristics subject to change without notice 7 Doc. No. 1037 Rev. J CAT24WC66 Figure 9. Selective Read Timing S T A R T S A C K S T A R T S A C K A C K A C K N O A C K BUS ACTIVITY: MASTER SDA LINE SLAVE ADDRESS BYTE ADDRESS A15–A8 A7–A0 XXX SLAVE ADDRESS DATA S T O P P X= Don't care bit Figure 10. Sequential Read Timing BUS ACTIVITY: MASTER SDA LINE A C K A C K A C K A C K N O A C K SLAVE ADDRESS S T O P P DATA n DATA n+1 DATA n+2 DATA n+x Doc. No. 1037 Rev. J 8 © 2006 Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT24WC66 PACKAGE OUTLINES 8-LEAD 300 MIL WIDE PLASTIC DIP (L) E1 D E A2 A A1 L e b2 b eB SYMBOL A A1 A2 b b2 D E E1 e eB L Notes: (1) (2) (3) MIN 0.38 3.05 0.36 1.14 9.02 7.62 6.09 7.87 2.92 NOM MAX 4.57 3.81 0.56 1.77 10.16 8.25 7.11 9.65 3.81 0.46 7.87 6.35 2.54 BSC For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf. All dimensions are in millimeters. Complies with JEDEC Standard MS001 dimensions. Dimensioning and tolerancing per ANSI Y14.5M-1982. © 2006 Catalyst Semiconductor, Inc. Characteristics subject to change without notice 9 Doc. No. 1037 Rev. J CAT24WC66 8-LEAD 150 MIL SOIC (W) E1 E D A Ө1 e b A1 h x 45 C L SYMBOL A1 A b C D E E1 e h L Ө1 MIN 0.10 1.35 0.33 0.19 4.80 5.80 3.80 NOM MAX 0.25 1.75 0.51 0.25 5.00 6.20 4.00 1.27 BSC 0.25 0.40 0° 0.50 1.27 8° For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf Notes: (1) (2) All dimensions are in millimeters. Complies with JEDEC specification MS-012 dimensions. Doc. No. 1037 Rev. J 10 © 2006 Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT24WC66 8-LEAD 208 MIL SOIC (X) E b D A e A1 c Ө1 L SYMBOL A1 A b c D E E1 e L Ө1 MIN 0.05 0.36 0.19 5.13 7.75 5.13 NOM MAX 0.25 2.03 0.48 0.25 5.33 8.26 5.33 1.27 BSC 0.51 0° 0.76 8° For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf. Notes: 1.Compliant with EIAJ specification EDR-7320 2. All dimensions in millimeters © 2006 Catalyst Semiconductor, Inc. Characteristics subject to change without notice 11 Doc. No. 1037 Rev. J CAT24WC66 EXAMPLE OF ORDERING INFORMATION Prefix CAT Company ID Product Number 24WC66 Device # Suffix 24WC66 W I Temperature Range I = Industrial (-40ºC to 85ºC) A = Automotive (-40ºC to 105ºC) E = Extended (-40ºC to 125ºC) -1.8 – G T3 Rev C(4) Die Revision 24WC66: C Lead Finish Blank: Matte-Tin G: NiPdAu Package L: PDIP W: SOIC, JEDEC (5) X: SOIC, EIAJ Operating Voltage Blank: VCC = 2.5V to 5.5V 1.8: VCC = 1.8V to 5.5V Tape & Reel T: Tape & Reel (5) 2: 2000/Reel 3: 3000/Reel Notes: (1) All packages are RoHS-compliant (Lead-free, Halogen-free). (2) The standard lead finish is NiPdAu. (3) The device used in the above example is a CAT24W66WI-1.8–GT3 (SOIC, Industrial Temperature, 1.8 to 5.5V Operating Voltage, NiPdAu, Tape & Reel). (4) Product die revision letter is marked on top of the package as a suffix to the production date code (e.g. AYWWC). For additional information, please contact your Catalyst sales office. (5) For SOIC, EIAJ (X) package the standard lead finish is Matte-Tin. This package is available in 2000 pcs/reel, i.e. CAT24WC66XI-T2. (6) For additional package and temperature options, please contact your nearest Catalyst Semiconductor Sales office. Doc. No. 1037 Rev. J 12 © 2006 Catalyst Semiconductor, Inc. Characteristics subject to change without notice REVISION HISTORY Date 3/4/2004 04/03/04 7/22/2004 8/3/2004 03/10/2005 Rev. D E F G H Reason Added Commercial temp range in all areas Update Pin Configuration Update Ordering Information Eliminate data sheet designation Added Die Revision to Ordering Information Update Features Update DC Operating Characteristics table & notes Update Ordering Information Update Pin Configuration Update DC Operating Characteristics Update AC Characteristics Update Figure 5, 6 and 7 Added Package Outlines Update Example of Ordering Information Update 8-Lead 300 Mil Wide Plastic DIP (L) Package Outline 11/07/2006 I 11/10/2006 J Copyrights, Trademarks and Patents Trademarks and registered trademarks of Catalyst Semiconductor include ech of the following: Beyond Memory™, DPP™, EZDim™, MiniPot™, and Quad-Mode™ Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. 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Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete. Catalyst Semiconductor, Inc. Corporate Headquarters 2975 Stender Way Santa Clara, CA 95054 Phone: 408.542.1000 Fax: 408.542.1200 www.catsemi.com Document No: 1037 Revision: J Issue date: 11/10/06