CAT25C01VITE13

CAT25C01, CAT25C02, CAT25C04 1K/2K/4K SPI Serial CMOS EEPROM FEATURES I 10 MHz SPI compatible I 1.8 to 5.5 volt operation I 16-byte page write buffer I Hardware and software protection I Block write protection DESCRIPTION The CAT25C01/02/04 is a 1K/2K/4K Bit SPI Serial CMOS EEPROM internally organized as 128x8/256x8/ 512x8 bits. Catalyst’s advanced CMOS Technology substantially reduces device power requirements. The CAT25C01/02/04 features a 16-byte page write buffer. The device operates via the SPI bus serial interface and is enabled though a Chip Select (CS). In addition to the Chip Select, the clock input (SCK), data in (SI) and data out (SO) are required to access the device. The HOLD pin may be used to suspend any serial communication without resetting the serial sequence. The CAT25C01/ 02/04 is designed with software and hardware write protection features including Block Write protection. The device is available in 8-pin DIP, 8-pin SOIC and 8-pin TSSOP packages. – Protect 1/4, 1/2 or all of EEPROM array I Low power CMOS technology I SPI modes (0,0 & 1,1) I Industrial temperature range I 1,000,000 program/erase cycles I 100 year data retention I Self-timed write cycle I RoHS compliant “ ”&“ ” 8-pin PDIP, SOIC and TSSOP packages PIN CONFIGURATION PDIP (L) SOIC (V) TSSOP (Y) PIN FUNCTIONS Pin Name SO SCK WP VCC VSS CS SI i D c s CS 1 2 3 4 8 7 6 5 SO WP VSS i t n o VCC SCK SI HOLD u n FUNCTIONAL SYMBOL VCC d e SI CS WP a P ts r CAT25C01 CAT25C02 CAT25C04 SO HOLD SCK Function VSS Serial Data Output Serial Clock Write Protect +1.8V to +5.5V Power Supply Ground Chip Select Serial Data Input Suspends Serial Input HOLD © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 1 Doc. No. 1105, Rev. B CAT25C01, CAT25C02, CAT25C04 ABSOLUTE MAXIMUM RATINGS* Storage Temperature Voltage on Any Pin with Respect to Ground(1) -65°C to +150°C -0.5 V to +6.5 V * Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. RELIABILITY CHARACTERISTICS(2) Symbol NEND(*) TDR Parameter Endurance Data Retention Min 1,000,000 100 Units Program/ Erase Cycles (*) Page Mode, VCC = 5 V, 25°C D.C. OPERATING CHARACTERISTICS VCC = 1.8 V to 5.5 V, TA = -40°C to 85°C, unless otherwise specified. Symbol ICC ISB IL VIL VIH VOL1 VOL2 Parameter Supply Current Standby Current I/O Pin Leakage Test Conditions Read or Write at 5 MHz All I/O Pins at GND or VCC, CS = VCC Input Low Voltage Input High Voltage Output Low Voltage Output Low Voltage PIN IMPEDANCE CHARACTERISTICS TA = 25°C, f = 1 MHz, VCC = 5 V Symbol CIN (2) CIN(2) ZWPL ILWPH Note: (1) The DC input voltage on any pin should not be lower than -0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may undershoot to no less than -1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns. (2) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100 and JEDEC test methods. i D Parameter SDA I/O Pin Capacitance Input Capacitance (other pins) WP Input Low Impedance WP Input High Leakage c s i t n o Pin at GND or VCC VCC > 2.5 V, IOL = 3.0 mA VCC > 1.8 V, IOL = 1.0 mA u n d e Min a P Years Max 1 2 2 VCC x 0.3 0.4 0.2 ts r Units mA µA µA V V V V -0.5 VCC x 0.7 VCC + 0.5 Conditions Min Max 8 6 Units pF pF kΩ µA VIN = 0 V VIN = 0 V VIN < 0.5 V VIN > VCC x 0.7 5 70 2 Doc. No. 1105, Rev. B 2 © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT25C01, CAT25C02, CAT25C04 A.C. CHARACTERISTICS CAT25CXX-1.8 1.8V-5.5V SYMBOL PARAMETER tSU tH tWH tWL fSCK tLZ tRI(1) tFI(1) tHD tCD tWC(4) tV tHO tDIS tHZ tCS tCSS tCSH tWPS tWPH Data Setup Time Data Hold Time SCK High Time SCK Low Time Clock Frequency HOLD to Output Low Z Input Rise Time Input Fall Time HOLD Setup Time HOLD Hold Time Write Cycle Time Output Valid from Clock Low Output Hold Time Output Disable Time HOLD to Output High Z CS High Time CS Setup Time CS Hold Time WP Setup Time WP Hold Time 0 100 100 5 Min. 50 50 250 250 DC 1 50 2 2 40 40 Max. Min. 20 20 75 75 DC 5 50 2 2 CAT25CXX 2.5V-5.5V Max. 4.5V-5.5V Min. 20 20 40 40 DC 10 Max. ns ns ns ns Test UNITS Conditions 50 2 Power-Up Timing(1)(3) NOTE: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) AC Test Conditions: Input Pulse Voltages: 0.3VCC to 0.7VCC Input rise and fall times: ≤10ns Input and output reference voltages: 0.5VCC Output load: current source IOL max/IOH max; CL=50pF (3) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. (4) tWC is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle. i D Symbol tPUR tPUW c s Power-up to Read Operation Power-up to Write Operation i t n o 500 500 500 150 150 Parameter u n 0 250 150 100 100 100 50 50 250 d e 40 5 75 0 75 50 100 100 100 50 50 Max. 1 1 40 40 a P ns µs µs ns 2 ns 5 ms ns ns ns ns ns ns ns ns ns MHz ts r CL = 50pF (note 2) 75 50 Units ms ms © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 3 Doc. No. 1105, Rev. B CAT25C01, CAT25C02, CAT25C04 FUNCTIONAL DESCRIPTION The CAT25C01/02/04 supports the SPI bus data transmission protocol. The synchronous Serial Peripheral Interface (SPI) helps the CAT25C01/02/04 to interface directly with many of today’s popular microcontrollers. The CAT25C01/02/04 contains an 8-bit instruction register. (The instruction set and the operation codes are detailed in the instruction set table) After the device is selected with CS going low, the first byte will be received. The part is accessed via the SI pin, with data being clocked in on the rising edge of SCK. The first byte contains one of the six op-codes that define the operation to be performed. PIN DESCRIPTION SI: Serial Input SI is the serial data input pin. This pin is used to input all opcodes, byte addresses, and data to be written to the CAT25010/20/40. Input data is latched on the rising edge of the serial clock for SPI modes (0, 0 & 1, 1). SO: Serial Output SO is the serial data output pin. This pin is used to transfer data out of the CAT25C01/02/04. During a read cycle, data is shifted out on the falling edge of the serial clock for SPI modes (0,0 & 1,1). Figure 1. Sychronous Data Timing VIH CS VIL tCSS VIH SCK VIL tSU VIH tWH tH SI VIL VOH SO VOL HI-Z Note: Dashed Line= mode (1, 1) – – – – – INSTRUCTION SET Instruction WREN WRDI RDSR WRSR READ WRITE Note: (1) X=0 for CAT25C01, CAT25C02. X=A8 for CAT25C04. i D c s i t n o VALID IN u n tWL tRI tFI tV d e tHO tCSH a P tDIS HI-Z ts r tCS Opcode Operation Enable Write Operations Disable Write Operations Read Status Register Write Status Register Read Data from Memory Write Data to Memory 0000 0110 0000 0100 0000 0101 0000 0001 0000 X011(1) 0000 X010(1) Doc. No. 1105, Rev. B 4 © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT25C01, CAT25C02, CAT25C04 When WP is tied low and the WPEN bit in the status register is set to “1”, all write operations to the status register are inhibited. WP going low while CS is still low will interrupt a write to the status register. If the internal write cycle has already been initiated, WP going low will have no effect on any write operation to the status register. The WP pin function is blocked when the WPEN bit is set to 0. Figure 10 illustrates the WP timing sequence during a write operation. HOLD: Hold SCK: Serial Clock SCK is the serial clock pin. This pin is used to synchronize the communication between the microcontroller and the CAT25C01/02/04. Opcodes, byte addresses, or data present on the SI pin are latched on the rising edge of the SCK. Data on the SO pin is updated on the falling edge of the SCK for SPI modes (0,0 & 1,1) . CS: Chip Select CS is the Chip select pin. CS low enables the CAT25C01/ 02/04 and CS high disables the CAT25C01/02/04. CS high takes the SO output pin to high impedance and forces the devices into a Standby Mode (unless an internal write operation is underway) The CAT25C01/ 02/04 draws ZERO current in the Standby mode. A high to low transition on CS is required prior to any sequence being initiated. A low to high transition on CS after a valid write sequence is what initiates an internal write cycle. WP: Write Protect WP is the Write Protect pin. The Write Protect pin will allow normal read/write operations when held high. STATUS REGISTER 7 WPEN 6 1 5 1 4 1 The HOLD pin is used to pause transmission to the CAT25C01/20/40 while in the middle of a serial sequence without having to re-transmit entire sequence at a later time. To pause, HOLD must be brought low while SCK is low. The SO pin is in a high impedance state during the time the part is paused, and transitions on the SI pins will be ignored. To resume communication, HOLD is brought high, while SCK is low. (HOLD should be held high any time this function is not being used.) HOLD may be tied high directly to VCC or tied to VCC through a resistor. Figure 9 illustrates hold timing sequence. BLOCK PROTECTION BITS Status Register Bits BP1 BP0 0 0 1 0 1 WRITE PROTECT ENABLE OPERATION WPEN 0 0 1 1 X X WP X X Low Low High High WEL 0 1 0 1 0 1 Protected Blocks Protected Protected Protected Protected Protected Protected Unprotected Blocks Protected Writable Protected Writable Protected Writable Status Register Protected Writable Protected Protected Protected Writable i D 1 c s 0 1 i t n o Array Address Protected None CAT25C01: 60-7F CAT25C02: C0-FF CAT25C04: 180-1FF CAT25C01: 40-7F CAT25C02: 80-FF CAT25C04: 100-1FF CAT25C01: 00-7F CAT25C02: 00-FF CAT25C04: 000-1FF u n 3 BP1 d e 2 BP0 a P 1 WEL ts r 0 RDY Protection No Protection Quarter Array Protection Half Array Protection Full Array Protection © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 5 Doc. No. 1105, Rev. B CAT25C01, CAT25C02, CAT25C04 STATUS REGISTER The Status Register indicates the status of the device. The RDY (Ready) bit indicates whether the CAT25C01/ 02/04 is busy with a write operation. When set to 1 a write cycle is in progress and when set to 0 the device indicates it is ready. This bit is read only. The WEL (Write Enable) bit indicates the status of the write enable latch. When set to 1, the device is in a Write Enable state and when set to 0 the device is in a Write Disable state. The WEL bit can only be set by the WREN instruction and can be reset by the WRDI instruction. The BP0 and BP1 (Block Protect) bits indicate which blocks are currently protected. These bits are set by the user issuing the WRSR instruction. The user is allowed to protect quarter of the memory, half of the memory or the entire memory by setting these bits. Once protected, the user may only read from the protected portion of the array. These bits are non-volatile. The WPEN (Write Protect Enable) is an enable bit for the WP pin. The WP pin and WPEN bit in the status register control the programmable hardware write protect feature. Hardware write protection is enabled when WP is low and WPEN bit is set to high. The user cannot write Figure 2. WREN Instruction Timing CS to the status register, (including the block protect bits and the WPEN bit) and the block protected sections in the memory array when the chip is hardware write protected. Only the sections of the memory array that are not block protected can be written. Hardware write protection is disabled when either WP pin is high or the WPEN bit is zero. DEVICE OPERATION Write Enable and Disable The CAT25C01/02/04 contains a write enable latch. This latch must be set before any write operation. The device powers up in a write disable state when VCC is applied. WREN instruction will enable writes (set the latch) to the device. WRDI instruction will disable writes (reset the latch) to the device. Disabling writes will protect the device against inadvertent writes. READ Sequence The part is selected by pulling CS low. The 8-bit read instruction is transmitted to the CAT25C01/02/04, followed by the 8-bit address for CAT25C01/02/04 (for the CAT25C04, bit 3 of the read data instruction contains address A8). SCK SI SO Figure 3. WRDI Instruction Timing CS SCK i D Note: Dashed Line = mode (1, 1) c s i t n o 0 0 0 0 u n 0 1 1 d e 0 a P ts r HIGH IMPEDANCE SI 0 0 0 0 0 1 0 0 SO Note: Dashed Line = mode (1, 1) HIGH IMPEDANCE Doc. No. 1105, Rev. B 6 © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT25C01, CAT25C02, CAT25C04 Write enable state by pulling the CS low and then clocking the WREN instruction into CAT25C01/02/04. The CS must be brought high after the WREN instruction to enable writes to the device. If the write operation is initiated immediately after the WREN instruction without CS being brought high, the data will not be written to the array because the write enable latch will not have been properly set. Also, for a successful write operation the address of the memory location(s) to be programmed must be outside the protected address field location selected by the block protection level. Byte Write Once the device is in a Write Enable state, the user may proceed with a write sequence by setting the CS low, issuing a write instruction via the SI line, followed by the 8-bit address for CAT25C01/02/04 (for the 25C04, bit 3 of the read data instruction contains address A8). Programming will start after the CS is brought high. Figure 6 illustrates byte write sequence. After the correct read instruction and address are sent, the data stored in the memory at the selected address is shifted out on the SO pin. The data stored in the memory at the next address can be read sequentially by continuing to provide clock pulses. The internal address pointer is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached, the address counter rolls over to 0000h allowing the read cycle to be continued indefinitely. The read operation is terminated by pulling the CS high. To read the status register, RDSR instruction should be sent. The contents of the status register are shifted out on the SO line. The status register may be read at any time even during a write cycle. Read sequece is illustrated in Figure 4. Reading status register is illustrated in Figure 5. WRITE Sequence The CAT25C01/02/04 powers up in a Write Disable state. Prior to any write instructions, the WREN instruction must be sent to CAT25C01/02/04. The device goes into Figure 4. Read Instruction Timing CS 0 SK 1 2 3 4 5 6 7 8 9 10 OPCODE SI 0 0 0 0 0 X* SO *Please check the instruction set table for address X=0 for 25010, 25020 ; X=A8 for 25040 Figure 5. RDSR Instruction Timing CS SCK i D 0 0 Note: Dashed line = mode (1,1)---- c s 1 2 0 0 i t n o 0 1 1 HIGH IMPEDANCE BYTE ADDRESS A4 A3 A7 A6 A5 u n 11 12 13 A2 d e 14 15 16 A1 A0 MSB a P 19 20 21 DATA OUT ts r 22 17 18 D7 D6 D5 D4 D3 D2 D1 D0 3 4 5 6 7 8 9 10 11 12 13 14 OPCODE SI 0 0 1 0 1 DATA OUT SO HIGH IMPEDANCE 7 MSB 6 5 4 3 2 1 0 Note: Dashed Line= mode (1, 1) – – – – – © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 7 Doc. No. 1105, Rev. B CAT25C01, CAT25C02, CAT25C04 During an internal write cycle, all commands will be ignored except the RDSR (Read Status Register) instruction. The Status Register can be read to determine if the write cycle is still in progress. If Bit 0 of the Status Register is set at 1, write cycle is in progress. If Bit 0 is set at 0, the device is ready for the next instruction. Page Write The CAT25C01/02/04 features page write capability. After the initial byte, the host may continue to write up to 16 bytes of data to the CAT25C01/02/04. After each byte of data received, lower order address bits are internally incremented by one; the high order bits of address will remain constant. The only restriction is that the X (X=16 for CAT25C01/02/04) bytes must reside on the same page. If the address counter reaches the end of the page and clock continues, the counter will “roll over” to the first address of the page and overwrite any data that may have been written. The CAT25C01/02/04 is automatically returned to the write disable state at the completion of the write cycle. Figure 8 illustrates the page write sequence. To write to the status register, the WRSR instruction should be sent. Only Bit 2, Bit 3 and Bit 7 of the status register can be written using the WRSR instruction. Figure 7 illustrates the sequence of writing to status register. Figure 6. Write Instruction Timing CS 0 SK OPCODE 1 2 3 4 5 6 7 8 13 14 15 16 17 18 19 20 21 22 23 SI 0 0 0 0 X* 00 SO HIGH IMPEDANCE Note: Dashed Line= mode (1, 1) – – – – – *X=0 for 25010, 25020 ; X=A8 for 25040 Figure 7. WRSR Timing CS SCK SI i D 0 0 c s 1 2 0 0 0 i t n o 1 0 A7 4 5 6 OPCODE BYTE ADDRESS u n 8 9 7 MSB A0 D7 D6 D5 D4 D3 D2 D1 D0 d e DATA IN a P ts r 3 7 10 11 12 13 14 15 DATA IN 0 0 0 1 6 5 4 3 2 1 0 SO HIGH IMPEDANCE Note: Dashed Line= mode (1, 1) – – – – – Doc. No. 1105, Rev. B 8 © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT25C01, CAT25C02, CAT25C04 DESIGN CONSIDERATIONS The CAT25C01/02/04 powers up in a write disable state and in a low power standby mode. A WREN instruction must be issued to perform any writes to the device after power up. Also,on power up CS should be brought low to enter a ready state and receive an instruction. After a successful byte/page write or status register write, the CAT25C01/02/04 goes into a write disable mode. CS must be set high after the proper number of clock cycles to start an internal write cycle. Access to the array during an internal write cycle is ignored and program- ming is continued. On power up, SO is in a high impedance. If an invalid op code is received, no data will be shifted into the CAT25C01/02/04, and the serial output pin (SO) will remain in a high impedance state until the falling edge of CS is detected again. When powering down, the supply should be taken down to 0V, so that the CAT25C01/02/04 will be reset when power is ramped back up. If this is not possible, then, following a brown-out episode, the CAT25C01/02/04 can be reset by refreshing the contents of the Status Register (See Application Note AN10). Figure 8. Page Write Instruction Timing CS 0 SK 1 2 3 4 5 6 7 8 13 14 15 16-23 24-31 16+(N-1)x8-1..16+(N-1)x8 16+Nx8-1 OPCODE BYTE ADDRESS 0 1 0 A7 A0 SI 0 0 0 0 0 X* Data Byte 1 SO HIGH IMPEDANCE Note: Dashed Line= mode (1, 1) – – – – – *X=0 for CAT25C01, CAT25C02; X=A8 for CAT25C04 Figure 9. HOLD Timing CS SCK HOLD Note: Dashed Line= mode (1, 1) – – – – – Figure 10. WP Timing i D SO CS SCK WP c s i t n o tCD tHD tHZ u n tHD t WPS d e DATA IN Data Byte 2 Data Byte 3 Data Byte N 0 7..1 a P ts r tCD HIGH IMPEDANCE tLZ t WPH WP Note: Dashed Line= mode (1, 1) – – – – – © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 9 Doc. No. 1105, Rev. B CAT25C01, CAT25C02, CAT25C04 8-LEAD 300 MIL WIDE PLASTIC DIP (L) E1 D A2 A A1 L e b2 b SYMBOL A A1 A2 b b2 D D2 E E1 e eB L MIN 0.120 0.015 0.115 0.014 0.045 0.355 0.300 0.300 0.240 Notes: 1. Complies with JEDEC Standard MS001. 2. All dimensions are in inches. 3. Dimensioning and tolerancing per ANSI Y14.5M-1982 i D c s 0.115 0.310 0.250 0.100 BSC 0.130 i t n o NOM MAX 0.210 0.130 0.018 0.060 0.365 0.195 0.022 0.070 0.400 0.325 0.325 0.280 0.430 0.150 u n d e a P eB E ts r 24C02_8-LEAD_DIP_(300P).eps Doc. No. 1105, Rev. B 10 © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT25C01, CAT25C02, CAT25C04 8-LEAD 150 MIL WIDE SOIC (V) E1 E D A θ1 e b A1 SYMBOL A1 A2 b C D E E1 e f θ1 MIN Notes: 1. Complies with JEDEC specification MS-012 dimensions. 2. All linear dimensions in millimeters. i D c s 0.0040 0.0532 0.013 0.0075 0.1890 02284 0.149 0.0099 0° i t n o NOM MAX 0.0098 0.0688 0.020 0.0098 0.1968 0.2440 0.1574 0.0196 8° 0.050 BSC u n d e L a P C 24C02_8-LEAD_SOIC.eps ts r © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 11 Doc. No. 1105, Rev. B CAT25C01, CAT25C02, CAT25C04 8-LEAD TSSOP (Y) D 8 5 SEE DETAIL A E E1 E/2 1 4 PIN #1 IDENT. θ1 A2 A e SYMBOL A A1 A2 b c D E E1 e L θ1 MIN 0.05 0.80 0.19 0.09 2.90 6.30 4.30 Notes: 1. All dimensions in millimeters. i D c s 0.50 0.00 i t n o A1 b u n d e L a P GAGE PLANE ts r c 0.25 SEATING PLANE SEE DETAIL A NOM MAX 1.20 0.15 1.05 0.30 0.20 3.10 6.50 4.50 0.75 8.00 0.90 3.00 6.4 4.40 0.65 BSC 0.60 Doc. No. 1105, Rev. B 12 © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT25C01, CAT25C02, CAT25C04 ORDERING INFORMATION Prefix CAT Device # 25C04 Suffix V I Temperature Range I = Industrial (-40°C to +85°C) -1.8 TE13 Optional Company ID Product Number 25C04: 4K 25C02: 2K 25C01: 1K Tape & Reel Package L: PDIP (Lead-free, Halogen-free, NiPdAu lead plating) V: SOIC, JEDEC (Lead-free, Halogen-free, NiPdAu lead plating) Y: TSSOP (Lead-free, Halogen-free, NiPdAu lead plating) Operating Voltage Blank (VCC = 2.5V to 5.5V) 1.8 (VCC = 1.8V to 5.5V) Notes: (1) The device used in the above example is a CAT25C04VI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 5.5 Volt Operating Voltage, Tape & Reel) i D c s i t n o u n d e a P ts r © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 13 Doc. No. 1105, Rev. B CAT25C01, CAT25C02, CAT25C04 PACKAGE MARKING 8-Lead PDIP 8-Lead SOIC VV 25C04LI YYWWC CSI 25C04L I YY WW C VV = Catalyst Semiconductor, Inc. = Device Code = Temperature Range = Production Year = Production Week = Product Revision = Voltage Range 1.8V - 5.5V = 18 2.5V - 5.5V = Blank VV 25C04VI YYWWC CSI 25C04V I YY WW C VV 8-Lead TSSOP YMCV Notes: (1) The circle on the package marking indicates the location of Pin 1. i D Y M C 25Y04 I V = Production Year = Production Month = Die Revision = Device Code = Industrial Temperature Range = Voltage Range 1.8V - 5.5V = 8 2.5V - 5.5V = Blank c s 25Y04 i t n o u n d e = Catalyst Semiconductor, Inc. = Device Code = Temperature Range = Production Year = Production Week = Product Revision = Voltage Range 1.8V - 5.5V = 18 2.5V - 5.5V = Blank a P ts r Doc. No. 1105, Rev. B 14 © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice REVISION HISTORY Date 10/13/05 Rev. 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Corporate Headquarters 1250 Borregas Avenue Sunnyvale, CA 94089 Phone: 408.542.1000 Fax: 408.542.1200 www.catalyst-semiconductor.com Publication #: Revison: Issue date: 1105 B 12/23/05