CAT25C33GVSATE13

CAT25C33/65 32K/64K-Bit SPI Serial CMOS EEPROM FEATURES s 10 MHz SPI compatible s 1.8 to 6.0 volt operation s Hardware and software protection s Low power CMOS technology s SPI modes (0,0 &1,1) s Commercial, industrial, automotive and extended s 1,000,000 program/erase cycles s 100 year data tetention s Self-timed write cycle s 8-pin DIP/SOIC and 14-pin TSSOP s 64-byte page write buffer s Block write protection temperature ranges – Protect first page, last page, any 1/4 or lower 1/2 of EEPROM array DESCRIPTION The CAT25C33/65 is a 32K/64K-Bit SPI Serial CMOS EEPROM internally organized as 4Kx8/8Kx8 bits. Catalyst’s advanced CMOS Technology substantially reduces device power requirements. The CAT25C33/ 65 features a 64-byte page write buffer. The device operates via the SPI bus serial interface and is enabled though a Chip Select (CS). In addition to the Chip Select, the clock input (SCK), data in (SI) and data out (SO) are PIN CONFIGURATION SOIC Package (S, V, GV) CS SO WP VSS 1 2 3 4 8 7 6 5 VCC HOLD SCK SI DIP Package (P, L, GL) CS SO WP VSS 1 2 3 4 8 7 6 5 VCC HOLD SCK SI PIN FUNCTIONS Pin Name SO SCK WP i D VCC VSS CS SI HOLD NC c s Ground i t n o CS SO NC NC NC WP VSS TSSOP Package (U14, Y14) 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC HOLD NC NC NC SCK SI u n required to access the device. The HOLD pin may be used to suspend any serial communication without resetting the serial sequence. The CAT25C32/64 is designed with software and hardware write protection features including Block write protection. The device is available in 8-pin DIP, 8-pin SOIC, 14-pin TSSOP and 20-pin TSSOP packages. d e a P CONTROL LOGIC ts r BLOCK DIAGRAM SENSE AMPS SHIFT REGISTERS WORD ADDRESS BUFFERS COLUMN DECODERS SO SI CS WP HOLD SCK I/O CONTROL SPI CONTROL LOGIC BLOCK PROTECT LOGIC XDEC E2PROM ARRAY Function Serial Data Output Serial Clock Write Protect +1.8V to +6.0V Power Supply STATUS REGISTER DATA IN STORAGE HIGH VOLTAGE/ TIMING CONTROL Chip Select Serial Data Input Suspends Serial Input No Connect © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 1 Doc. No. 1000, Rev. H CAT25C33/65 ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias ................. –55°C to +125°C Storage Temperature ....................... –65°C to +150°C Voltage on any Pin with Respect to VSS1) ................... –2.0V to +VCC +2.0V VCC with Respect to VSS ................................ –2.0V to +7.0V Package Power Dissipation Capability (Ta = 25°C) ................................... 1.0W Lead Soldering Temperature (10 secs) ............ 300°C Output Short Circuit Current(2) ........................ 100 mA RELIABILITY CHARACTERISTICS Symbol NEND TDR ILTH (3) (3) *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Parameter Endurance Data Retention ESD Susceptibility Latch-up Min. 1,000,000 100 2000 100 Typ. Max. VZAP(3) (3)(4) D.C. OPERATING CHARACTERISTICS VCC = +1.8V to +6.0V, unless otherwise specified. Symbol ICC1 ICC2 ISB(5) ILI ILO VIL(3) VIH(3) VOL1 VOH1 VOL2 VOH2 Parameter Power Supply Current (Operating Write) Power Supply Current (Operating Read) Power Supply Current (Standby) Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage Note: (1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns. (2) Output shorted for no more than one second. No more than one output shorted at a time. (3) These parameter are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100 and JEDEC test methods. (4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V. (5) Maximum standby current (ISB ) = 10µA for the Automotive and Extended Automotive temperature range. i D c s i t n o Min. u n Limits Typ. d e Max. 10 2 1 2 3 a P Cycles/Byte Years Volts mA ts r Units Units mA mA µA µA µA V V V V V V Test Conditions VCC = 5V @ 10MHz SO=open; CS=Vss VCC = 5.0V FCLK = 10MHz CS = VCC VIN = VSS or VCC VOUT = 0V to VCC, CS = 0V -1 VCC x 0.7 VCC - 0.8 VCC x 0.3 VCC + 0.5 0.4 4.5V≤VCC