CAT28C257PA-15T

CAT28C257 256K-Bit CMOS PARALLEL EEPROM FEATURES ■ Fast read access times: 120/150 ns ■ Low power CMOS dissipation: ■ Automatic page write operation: H GEN FR ALO EE LE A D F R E ETM –Active: 25 mA max. –Standby: 150 µA max. ■ Simple write operation: –1 to 128 Bytes in 5ms –Page load timer ■ End of write detection: –On-chip address and data latches –Self-timed write cycle with auto-clear ■ Fast write cycle time: –Toggle bit –DATA polling ■ Hardware and software write protection ■ 100,000 Program/erase cycles ■ 100 Year data retention ■ Commercial, industrial and automotive –5ms max ■ CMOS and TTL compatible I/O temperature ranges DESCRIPTION The CAT28C257 is a fast, low power, 5V-only CMOS Parallel EEPROM organized as 32K x 8-bits. It requires a simple interface for in-system programming. On-chip address and data latches, self-timed write cycle with autoclear and VCC power up/down write protection eliminate additional timing and protection hardware. DATA Polling and Toggle status bits signal the start and end of the selftimed write cycle. Additionally, the CAT28C257 features hardware and software write protection. The CAT28C257 is manufactured using Catalyst’s advanced CMOS floating gate technology. It is designed to endure 100,000 program/erase cycles and has a data retention of 100 years. The device is available in JEDEC approved 28-pin DIP or 32-pin PLCC packages. BLOCK DIAGRAM 32,768 x 8 EEPROM ARRAY 128 BYTE PAGE REGISTER A7–A14 ADDR. BUFFER & LATCHES INADVERTENT WRITE PROTECTION ROW DECODER VCC HIGH VOLTAGE GENERATOR CE OE WE CONTROL LOGIC I/O BUFFERS TIMER DATA POLLING AND TOGGLE BIT COLUMN DECODER I/O0–I/O7 A0–A6 ADDR. BUFFER & LATCHES © 2004 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 1 Doc. No. 1015, Rev. D CAT28C257 PIN CONFIGURATION DIP Package (P, L) A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 PLCC Package (N, G) NC VCC WE A7 A12 A14 A13 A6 A5 A4 A3 A2 A1 A0 NC I/O0 4 3 2 1 32 31 30 5 29 6 28 7 27 8 26 9 25 TOP VIEW 10 24 11 23 12 22 13 21 14 15 16 17 18 19 20 I/O1 I/O2 VSS NC I/O3 I/O4 I/O5 A8 A9 A11 NC OE A10 CE I/O7 I/O6 PIN FUNCTIONS Pin Name A0–A14 I/O0–I/O7 CE OE Function Address Inputs Data Inputs/Outputs Chip Enable Output Enable Pin Name WE VCC VSS NC Function Write Enable 5V Supply Ground No Connect Doc. No. 1015, Rev. D 2 CAT28C257 ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias .................. -55°C to +125°C Storage Temperature ........................ -65°C to +150°C Voltage on Any Pin with Respect to Ground(2) ............ -2.0V to +VCC + 2.0V VCC with Respect to Ground ................ -2.0V to +7.0V Package Power Dissipation Capability (Ta = 25°C) ................................... 1.0W Lead Soldering Temperature (10 secs) ............ 300°C Output Short Circuit Current(3) ........................ 100 mA RELIABILITY CHARACTERISTICS Symbol NEND (1) *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Parameter Endurance Data Retention Test Method MIL-STD-883, Test Method 1033 MIL-STD-883, Test Method 1008 Min 104 or 105 100 2000 100 Typ Max Units Cycles/Byte Years Volts mA TDR(1) VZAP(1) ILTH(1)(4) ESD Susceptibility MIL-STD-883, Test Method 3015 Latch-Up JEDEC Standard 17 D.C. OPERATING CHARACTERISTICS VCC = 5V ±10%, unless otherwise specified. Symbol ICC ICCC(5) ISB ISBC(6) ILI ILO VIH(6) VIL(5) VOH VOL VWI Parameter VCC Current (Operating, TTL) Test Conditions CE = OE = VIL, f=6MHz All I/O’s Open Min Typ 30 25 1 150 –10 –10 2 –0.3 IOH = –400µA IOL = 2.1mA 3.5 2.4 0.4 Max mA mA mA µA 10 10 VCC +0.3 0.8 µA µA V V V V V Units VCC Current (Operating, CMOS) CE = OE = VILC, f=6MHz All I/O’s Open VCC Current (Standby, TTL) VCC Current (Standby, CMOS) Input Leakage Current Output Leakage Current High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Write Inhibit Voltage CE = VIH, All I/O’s Open CE = VIHC, All I/O’s Open VIN = GND to VCC VOUT = GND to VCC, CE = VIH Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns. (3) Output shorted for no more than one second. No more than one output shorted at a time. (4) Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC +1V. (5) VILC = –0.3V to +0.3V. (6) VIHC = VCC –0.3V to VCC +0.3V. 3 Doc. No. 1015, Rev. D CAT28C257 MODE SELECTION Mode Read Byte Write (WE Controlled) Byte Write (CE Controlled) Standby, and Write Inhibit Read and Write Inhibit H X CE L L L X H WE H OE L H H X H I/O DOUT DIN DIN High-Z High-Z Power ACTIVE ACTIVE ACTIVE STANDBY ACTIVE CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V Symbol CI/O(1) CIN (1) Test Input/Output Capacitance Input Capacitance Conditions VI/O = 0V VIN = 0V Min Typ Max 10 6 Units pF pF A.C. CHARACTERISTICS, Read Cycle VCC=5V + 10%, Unless otherwise specified 28C257-12 Symbol tRC tCE tAA tOE tLZ (1) 28C257-15 Max Min 150 120 120 50 150 150 70 0 0 50 50 50 50 0 Typ Max Units ns ns ns ns ns ns ns ns ns Parameter Read Cycle Time CE Access Time Address Access Time OE Access Time CE Low to Active Output OE Low to Active Output CE High to High-Z Output OE High to High-Z Output Output Hold from Address Change Min 120 Typ 0 0 tOLZ(1) tHZ(1)(2) tOHZ(1)(2) tOH (1) 0 Power-Up Timing Symbol tPUR tPUW Parameter Power-Up to Read Power-Up to Write 5 Min Typ Max 100 10 Units µs ms Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) Output floating (High-Z) is defined as the state when the external data line is no longer driven by the output buffer. Doc. No. 1015, Rev. D 4 CAT28C257 A.C. CHARACTERISTICS, Write Cycle VCC=5V±10%, unless otherwise specified 28C257-12 Symbol tWC tAS tAH tCS tCH tCW(3) tOES tOEH tWP(3) tDS tDH tINIT(1) tBLC(1)(4) Parameter Write Cycle Time Address Setup Time Address Hold Time CE Setup Time CE Hold Time CE Pulse Time OE Setup Time OE Hold Time WE Pulse Width Data Setup Time Data Hold Time Write Inhibit Period After Power-up Byte Load Cycle Time 0 50 0 0 100 0 0 100 50 0 5 0.1 0 10 100 5 0.1 10 100 Min Typ Max 5 0 50 0 0 100 0 0 100 50 Min 28C257-15 Typ Max 5 Units ms ns ns ns ns ns ns ns ns ns ns ms µs Figure 1. A.C. Testing Input/Output Waveform(2) VCC - 0.3V INPUT PULSE LEVELS 0.0 V 0.8 V 2.0 V REFERENCE POINTS Figure 2. A.C. Testing Load Circuit (example) 1.3V 1N914 3.3K DEVICE UNDER TEST OUT CL = 100 pF CL INCLUDES JIG CAPACITANCE Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) Input rise and fall times (10% and 90%) < 10 ns. (3) A write pulse of less than 20ns duration will not initiate a write cycle. (4) A timer of duration tBLC max. begins with every LOW to HIGH transition of WE. If allowed to time out, a page or byte write will begin; however a transition from HIGH to LOW within tBLC max. stops the timer. 5 Doc. No. 1015, Rev. D CAT28C257 DEVICE OPERATION Read Data stored in the CAT28C257 is transferred to the data bus when WE is held high, and both OE and CE are held low. The data bus is set to a high impedance state when either CE or OE goes high. This 2-line control architecture can be used to eliminate bus contention in a system environment. Byte Write A write cycle is executed when both CE and WE are low, and OE is high. Write cycles can be initiated using either WE or CE, with the address input being latched on the falling edge of WE or CE, whichever occurs last. Data, conversely, is latched on the rising edge of WE or CE, whichever occurs first. Once initiated, a byte write cycle automatically erases the addressed byte and the new data is written within 5 ms. Figure 3. Read Cycle tRC ADDRESS tCE CE tOE OE VIH WE tLZ tOLZ DATA OUT HIGH-Z tOH DATA VALID tAA tOHZ tHZ DATA VALID Figure 4. Byte Write Cycle [WE Controlled] ADDRESS tAS tCS CE tAH tCH 28C256 F06 tWC OE tOES WE tBLC DATA OUT HIGH-Z tWP tOEH DATA IN DATA VALID tDS tDH Doc. No. 1015, Rev. D 6 CAT28C257 Page Write The page write mode of the CAT28C257 (essentially an extended BYTE WRITE mode) allows from 1 to 128 bytes of data to be programmed within a single EEPROM write cycle. This effectively reduces the byte-write time by a factor of 128. Following an initial WRITE operation (WE pulsed low, for tWP, and then high) the page write mode can begin by issuing sequential WE pulses, which load the address and data bytes into a128 byte temporary buffer. The page address where data is to be written, specified by bits A7 to A14, is latched on the last falling edge of WE. Each byte within the page is defined by address bits A0 Figure 5. Byte Write Cycle [CE Controlled] ADDRESS tAS tAH tCW CE tOEH OE tCS WE HIGH-Z DATA OUT tOES tCH tBLC to A6 (which can be loaded in any order) during the first and subsequent write cycles. Each successive byte load cycle must begin within tBLC MAX of the falling edge of the preceding WE pulse. There is no page write window limitation as long as WE is pulsed low within tBLC MAX. Upon completion of the page write sequence, WE must stay high a minimum of tBLC MAX for the internal automatic program cycle to commence. This programming cycle consists of an erase cycle, which erases any data that existed in each addressed cell, and a write cycle, which writes new data back into the cell. A page write will only write data to the locations that were addressed and will not rewrite the entire page. tWC DATA IN DATA VALID tDS tDH Figure 6. Page Mode Write Cycle OE CE t WP WE t BLC ADDRESS t WC I/O BYTE 0 BYTE 1 BYTE 2 BYTE n BYTE n+1 LAST BYTE BYTE n+2 7 Doc. No. 1015, Rev. D CAT28C257 DATA Polling DATA polling is provided to indicate the completion of write cycle. Once a byte write or page write cycle is initiated, attempting to read the last byte written will output the complement of that data on I/O7 (I/O0–I/O6 are indeterminate) until the programming cycle is complete. Upon completion of the self-timed write cycle, all I/O’s will output true data during a read cycle. Toggle Bit In addition to the DATA Polling feature of the CAT28C257, the device offers an additional method for determining the completion of a write cycle. While a write cycle is in progress, reading data from the device will result in I/O6 toggling between one and zero. However, once the write is complete, I/O6 stops toggling and valid data can be read from the device. Figure 7. DATA Polling ADDRESS CE WE tOEH OE tWC I/O7 DIN = X DOUT = X DOUT = X tOE tOES Figure 8. Toggle Bit WE CE tOEH OE tOE tOES I/O6 (1) tWC (1) Note: (1) Beginning and ending state of I/O6 is indeterminate. Doc. No. 1015, Rev. D 8 CAT28C257 HARDWARE DATA PROTECTION The following is a list of hardware data protection features that are incorporated into the CAT28C257. (1) VCC sense provides for write protection when VCC falls below 3.5V min. (2) A power on delay mechanism, tINIT (see AC characteristics), provides a 5 to 10 ms delay before a write sequence, after VCC has reached 3.5V min. (3) Write inhibit is activated by holding any one of OE low, CE high or WE high. (4) Noise pulses of less than 20 ns on the WE or CE inputs will not result in a write cycle. SOFTWARE DATA PROTECTION The CAT28C257 features a software controlled data protection scheme which, once enabled, requires a data algorithm to be issued to the device before a write can be performed. The device is shipped from Catalyst with the software protection NOT ENABLED (the CAT28C257 is in the standard operating mode). Figure 9. Write Sequence for Activating Software Data Protection WRITE DATA: ADDRESS: AA 5555 Figure 10. Write Sequence for Deactivating Software Data Protection WRITE DATA: ADDRESS: AA 5555 WRITE DATA: ADDRESS: 55 2AAA WRITE DATA: ADDRESS: 55 2AAA WRITE DATA: ADDRESS: A0 5555 WRITE DATA: ADDRESS: 80 5555 SOFTWARE DATA (12) (1) PROTECTION ACTIVATED WRITE DATA: ADDRESS: AA 5555 WRITE DATA: XX WRITE DATA: ADDRESS: 55 2AAA TO ANY ADDRESS WRITE LAST BYTE TO LAST ADDRESS W R I T E DATA : ADDRESS: 20 5555 Note: (1) Write protection is activated at this point whether or not any more writes are completed. Writing to addresses must occur within tBLC Max., after SDP activation. 9 Doc. No. 1015, Rev. D CAT28C257 To activate the software data protection, the device must be sent three write commands to specific addresses with specific data (Figure 9). This sequence of commands (along with subsequent writes) must adhere to the page write timing specifications (Figure 11). Once this is done, all subsequent byte or page writes to the device must be preceded by this same set of write commands. The data protection mechanism is activated until a deactivate sequence is issued regardless of power on/off transitions. This gives the user added inadvertent write protection on power-up in addition to the hardware protection provided. Figure 11. Software Data Protection Timing DATA ADDRESS CE tWP WE tBLC AA 5555 55 2AAA A0 5555 BYTE OR PAGE WRITES ENABLED tWC To allow the user the ability to program the device with an EEPROM programmer (or for testing purposes) there is a software command sequence for deactivating the data protection. The six step algorithm (Figure 10) will reset the internal protection circuitry, and the device will return to standard operating mode (Figure 12 provides reset timing). After the sixth byte of this reset sequence has been issued, standard byte or page writing can commence. Figure 12. Resetting Software Data Protection Timing DATA ADDRESS CE DEVICE UNPROTECTED WE AA 5555 55 2AAA 80 5555 AA 5555 55 2AAA 20 5555 tWC SDP RESET Doc. No. 1015, Rev. D 10 CAT28C257 ORDERING INFORMATION Prefix CAT Device # 28C257 Suffix N I -90 T Optional Company ID Product Number Temperature Range Blank = Commercial (0°C to +70°C) I = Industrial (-40°C to +85°C) A = Automotive (-40°C to +105°C)* Package P: PDIP N: PLCC L: PDIP (Lead free, Halogen free) G: PLCC (Lead free, Halogen free) Speed 12: 120ns 15: 150ns Tape & Reel * -40°C to +125°C is available upon request Notes: (1) The device used in the above example is a CAT28C257NI-90T (100,000 Cycle Endurance, PLCC, Industrial temperature, 200 ns Access Time, Tape & Reel). 11 Doc. No. 1015, Rev. D REVISION HISTORY Date 3/29/2004 04/19/04 Revision Comments D D Added Green packages in all areas. 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Corporate Headquarters 1250 Borregas Avenue Sunnyvale, CA 94089 Phone: 408.542.1000 Fax: 408.542.1200 www.catalyst-semiconductor.com Publication #: Revison: Issue date: 1015 D 4/19/04