CAT28F001PA-90BT

CAT28F001 1 Megabit CMOS Boot Block Flash Memory FEATURES I Fast Read Access Time: 90/120 ns I On-Chip Address and Data Latches I Blocked Architecture Licensed Intel second source H GEN FR ALO EE LE A D F R E ETM I Deep Powerdown Mode I I I I I — One 8 KB Boot Block w/ Lock Out • Top or Bottom Locations — Two 4 KB Parameter Blocks — One 112 KB Main Block Low Power CMOS Operation 12.0V ± 5% Programming and Erase Voltage Automated Program & Erase Algorithms High Speed Programming Commercial, Industrial and Automotive Temperature Ranges I I I I I I — 0.05 µA ICC Typical — 0.8 µA IPP Typical Hardware Data Protection Electronic Signature 100,000 Program/Erase Cycles and 10 Year Data Retention JEDEC Standard Pinouts: — 32 pin DIP — 32 pin PLCC — 32 pin TSOP Reset/Deep Power Down Mode "Green" Package Options Available DESCRIPTION The CAT28F001 is a high speed 128K X 8 bit electrically erasable and reprogrammable Flash memory ideally suited for applications requiring in-system or after sale code updates. The CAT28F001 has a blocked architecture with one 8 KB Boot Block, two 4 KB Parameter Blocks and one 112 KB Main Block. The Boot Block section can be at the top or bottom of the memory map and includes a reprogramming write lock out feature to guarantee data integrity. It is designed to contain secure code which will bring up the system minimally and download code to other locations of CAT28F001. The CAT28F001 is designed with a signature mode which allows the user to identify the IC manufacturer and device type. The CAT28F001 is also designed with onChip Address Latches, Data Latches, Programming and Erase Algorithms. The CAT28F001 is manufactured using Catalyst’s advanced CMOS floating gate technology. It is designed to endure 100,000 program/erase cycles and has a data retention of 10 years. The device is available in JEDEC approved 32-pin plastic DIP, PLCC or TSOP packages. BLOCK DIAGRAM I/O0–I/O7 ADDRESS COUNTER I/O BUFFERS WRITE STATE MACHINE RP WE COMMAND REGISTER PROGRAM VOLTAGE SWITCH CE, OE LOGIC DATA LATCH SENSE AMP ERASE VOLTAGE SWITCH STATUS REGISTER CE OE ADDRESS LATCH Y-GATING Y-DECODER 8K-BYTE BOOT BLOCK 4K-BYTE PARAMETER BLOCK 4K-BYTE PARAMETER BLOCK 112K-BYTE MAIN BLOCK A0–A16 VOLTAGE VERIFY SWITCH X-DECODER COMPARATOR © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 1 Doc. No. 1078, Rev. I CAT28F001 PIN CONFIGURATION DIP Package (P, L) VPP A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC WE RP A14 A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 PLCC Package (N, G) A16 VPP VCC WE A12 A15 RP 4 3 2 1 32 31 30 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 5 6 7 8 9 10 11 12 29 28 27 26 25 24 23 A14 A13 A8 A9 A11 OE A10 I/O7 22 28F001 F02 CE 13 21 14 15 16 17 18 19 20 VSS I/O3 I/O1 I/O2 I/O4 I/O5 I/O6 TSOP Package (Standard Pinout) (T, H) A11 A9 A8 A13 A14 RP WE VCC VPP A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 VSS I/O2 I/O1 I/O0 A0 A1 A2 A3 PIN FUNCTIONS Pin Name A0–A16 I/O0–I/O7 CE OE WE VCC VSS VPP RP Input Type Input I/O Input Input Input Function Address Inputs for memory addressing Data Input/Output Chip Enable Output Enable Write Enable Voltage Supply Ground Program/Erase Voltage Supply Power Down Doc. No. 1078, Rev. I 2 CAT28F001 ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias ................... –55°C to +95°C Storage Temperature ....................... –65°C to +150°C Voltage on Any Pin with Respect to Ground(1) ........... –2.0V to +VCC + 2.0V (Except A9, RP, OE, VCC and VPP) Voltage on Pin A9, RP AND OE with Respect to Ground(1) ................... –2.0V to +13.5V VPP with Respect to Ground during Program/Erase(1) .............. –2.0V to +14.0V VCC with Respect to Ground(1) ............ –2.0V to +7.0V Package Power Dissipation Capability (TA = 25°C) .................................. 1.0 W Lead Soldering Temperature (10 secs) ............ 300°C Output Short Circuit Current(2) ........................ 100 mA *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. RELIABILITY CHARACTERISTICS Symbol NEND (3) Parameter Endurance Data Retention ESD Susceptibility Latch-Up Min. 100K 10 2000 100 Max. Units Cycles/Byte Years Volts mA Test Method MIL-STD-883, Test Method 1033 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 3015 JEDEC Standard 17 TDR(3) VZAP(3) ILTH(3)(4) CAPACITANCE TA = 25°C, f = 1.0 MHz Limits Symbol CIN(3) COUT (3) Test Input Pin Capacitance Output Pin Capacitance VPP Supply Capacitance Min Max. 8 12 25 Units pF pF pF Conditions VIN = 0V VOUT = 0V VPP = 0V CVPP(3) Note: (1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns. (2) Output shorted for no more than one second. No more than one output shorted at a time. (3) This parameter is tested initially and after a design or process change that affects the parameter. (4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V. 3 Doc. No. 1078, Rev. I CAT28F001 D.C. OPERATING CHARACTERISTICS VCC = +5V ±10%, unless otherwise specified Limits Symbol ILI ILO ISB1 ISB2 IPPD ICC1 ICC2(1) ICC3(1) IPPS IPP1 IPP2 (1) Parameter Input Leakage Current Output Leakage Current VCC Standby Current CMOS VCC Standby Current TTL VPP Deep Powerdown Current VCC Active Read Current VCC Programming Current VCC Erase Current VPP Standby Current VPP Read Current VPP Programming Current VPP Erase Current Input Low Level Output Low Level Input High Level Output High Level A9 Signature Voltage A9 Signature Current VCC Deep Powerdown Current VCC Erase Suspend Current VPP Erase Suspend Current Min. Max. ±1.0 ±10 100 1.5 1.0 30 20 20 ±10 200 200 30 30 Unit µA µA µA mA µA mA mA mA µA µA µA mA mA V V V V Test Conditions VIN = VCC or VSS VCC = 5.5V VOUT = VCC or VSS, VCC = 5.5V CE = VCC ±0.2V = RP VCC = 5.5V CE = RP = VIH, VCC = 5.5V RP = GND±0.2V VCC = 5.5V, CE = VIL, IOUT = 0mA, f = 8 MHz VCC = 5.5V, Programming in Progress VCC = 5.5V, Erase in Progress VPP < VCC VPP > VCC VPP = VPPH VPP = VPPH, Programming in Progress VPP = VPPH, Erase in Progress IOL = 5.8mA, VCC = 4.5V IOH = 2.5mA, VCC = 4.5V A9 = VID A9 = VID RP = GND±0.2V Erase Suspended CE = VIH Erase Suspended VPP=VPPH IPP3(1) VIL VOL VIH VOH VID IID ICCD ICCES IPPES –0.5 2.0 2.4 11.5 0.8 0.45 VCC+0.5 13.0 500 1.0 10 300 V µA µA mA µA Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. Doc. No. 1078, Rev. I 4 CAT28F001 SUPPLY CHARACTERISTICS Limits Symbol VLKO VCC VPPL VPPH VHH Parameter VCC Erase/Write Lock Voltage VCC Supply Voltage VPP During Read Operations VPP During Erase/Program RP, OE Unlock Voltage Min 2.5 4.5 0 11.4 11.4 5.5 6.5 12.6 12.6 Max. Unit V V V V V A.C. CHARACTERISTICS, Read Operation VCC = +5V ±10%, unless otherwise specified JEDEC Symbol tAVAV tELQV tAVQV tGLQV tGLQX tELQX tGHQZ tEHQZ tPHQV Standard Symbol tRC tCE tACC tOE tOH tOLZ tLZ tDF tHZ (1)(6) (1)(6) (1)(2) (1)(2) Parameter Read Cycle Time CE Access Time Address Access Time OE Access Time Output Hold from Address OE/CE Change OE to Output in Low-Z CE to Output in Low-Z OE High to Output High-Z CE High to Output High-Z RP High to Output Delay 28F001-90(7) Min Max 90 90 90 35 0 0 0 30 35 600 28F001-12(7) Min Max 120 120 120 50 0 0 0 30 55 600 Units ns ns ns ns ns ns ns ns ns ns tPWH Figure 1. A.C. Testing Input/Output Waveform(3)(4)(5) VCC - 0.3V INPUT PULSE LEVELS 0.0 V 0.8 V 2.0 V REFERENCE POINTS Figure 2. Highspeed A.C. Testing Input/Output Waveform(3)(4)(5) 3.0 V INPUT PULSE LEVELS 0.0 V 1.5 V REFERENCE POINTS Testing Load Circuit (example) 1.3V 1N914 Testing Load Circuit (example) 1.3V 1N914 3.3K DEVICE UNDER TEST OUT CL = 100 pF CL INCLUDES JIG CAPACITANCE 3.3K DEVICE UNDER TEST OUT CL = 30 pF CL INCLUDES JIG CAPACITANCE Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) Output floating (High-Z) is defined as the state where the external data line is no longer driven by the output buffer. (3) Input Rise and Fall Times (10% to 90%) < 10 ns. (4) Input Pulse Levels = 0.45V and 2.4V. For High Speed Input Pulse Levels 0.0V and 3.0V. (5) Input and Output Timing Reference = 0.8V and 2.0V. For High Speed Input and Output Timing Reference = 1.5V. (6) Low-Z is defined as the state where the external data may be driven by the output buffer but may not be valid. (7) For load and reference points, see Fig. 1 5 Doc. No. 1078, Rev. I CAT28F001 A.C. CHARACTERISTICS, Program/Erase Operation VCC = +5V ±10% JEDEC Symbol tAVAV tAVWH tWHAX tDVWH tWHDX tELWL tWHEH tWLWH tWHWL tWHGL tPHWL tPHHWH tVPWH tWHQV1 tWHQV2 tWHQV3 tWHQV4 tQVVL tQVPH tPHBR (1) Standard Symbol tWC tAS tAH tDS tDH tCS tCH tWP tWPH — tPS (1) Parameter Write Cycle Time Address Setup to WE Going High Address Hold Time from WE Going High Data Setup Time to WE Going High Data Hold Time from WE Going High CE Setup Time to WE Going Low CE Hold Time from WE Going High WE Pulse Width WE High Pulse Width Write Recovery Time Before Read RP High Recovery to WE Going Low RP VHH Setup to WE Going High VPP Setup to WE Going High Duration of Programming Operations Duration of Erase Operations (Boot) Duration of Erase Operations (Parameter) Duration of Erase Operations (Main) 28F001-90 Min Max 90 40 10 40 10 0 0 40 10 0 480 100 100 15 1.3 1.3 3 0 0 100 480 480 28F001-12 Min Max 120 40 10 40 10 0 0 40 10 0 480 100 100 15 1.3 1.3 3 0 0 100 480 480 Units ns ns ns ns ns ns ns ns ns µs ns ns ns µs Sec Sec Sec ns ns ns ns ns tPHS(1) tVPS(1) — — — — tVPH — — — (1) (1) VPP Hold from Valid Status Reg Data RP VHH Hold from Status Reg Data Boot Block Relock Delay OE VHH Setup to WE Going Low OE VHH Hold from WE High tPHH tGHHWL tWHGH Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. Doc. No. 1078, Rev. I 6 CAT28F001 ERASE AND PROGRAMMING PERFORMANCE 28F001-90 Parameter Boot Block Erase Time Boot Block Program Time Parameter Block Erase Time Parameter Block Program Time Main Block Erase Time Main Block Program Time Chip Erase Time Chip Program Time Min Typ 2.10 0.15 2.10 0.07 3.80 2.10 10.10 2.39 Max 14.9 0.52 14.6 0.26 20.9 7.34 65 8.38 Min 28F001-12 Typ 2.10 0.15 2.10 0.07 3.80 2.10 10.10 2.39 Max 14.9 0.52 14.6 0.26 20.9 7.34 65 8.38 Units Sec Sec Sec Sec Sec Sec Sec Sec FUNCTION TABLE(1) Pins Mode Read Output Disable Standby Signature (MFG) Signature (Device) Write Cycle Deep Power Down WRITE COMMAND TABLE Commands are written into the command register in one or two write cycles. Write cycles also internally latch addresses and data required for programming and erase operations. Mode Read Array/Reset Program Setup/ Program Read Status Reg. Clear Status Reg. Erase Setup/Erase Confirm Erase Suspend/ Erase Resume Read Sig (Mfg) Read Sig (Dev) First Bus Cycle Operation Address DIN Write Write Write Write Write Write Write Write X AIN X X Block ad X X X FFH 40H 10H 70H 50H 20H B0H 90H 90H Write Write Read Read Block ad X 0000H 0001H D0H D0H 31H 94H-28F001T 95H-28F001B Write Read AIN X DIN St. Reg. Data Operation Second Bus Cycle Address DIN DOUT RP VIH VIH VIH VIH VIH VIH VIL CE VIL VIL VIH VIL VIL VIL X OE VIL VIH X VIL VIL VIH X WE VIH VIH X VIH VIH VIL X VPP X X X X X X X I/O DOUT High-Z High-Z 31H 94H-28F001T 95H-28F001B DIN HIGH-Z A0 = VIL, A9 = 12V A0 = VIH, A9 = 12V During Write Cycle Notes Note: (1) Logic Levels: X = Logic ‘Do not care’ (VIH, VIL, VPPL, VPPH) 7 Doc. No. 1078, Rev. I CAT28F001 READ OPERATIONS Read Mode The CAT28F001 memory can be read from any of its Blocks (Boot Block, Main Block or Parameter Block), Status Register and Signature Information by sending the Read Command Mode to the Command Register. CAT28F001 automatically resets to Read Array mode upon initial device power up or after exit from deep power down. A Read operation is performed with both CE and OE low and with RP and OE high. Vpp can be either high or low. The data retrieved from the I/O pins reflects the contents of the memory location corresponding to the state of the 17 address pins. The respective timing waveforms for the read operation are shown in Figure 3. Refer to the AC Read characteristics for specific timing parameters. Signature Mode The signature mode allows the user to identify the IC manufacturer and the type of the device while the device resides in the target system. This mode can be activated in either of two ways; through the conventional method of applying a high voltage (12V) to address pin A9 or by sending an instruction to the command register (see Write Operations). The conventional method is entered as a regular read mode by driving the CE and OE low (with WE high), and Figure 3. A.C. Timing for Read Operation POWER UP STANDBY DEVICE AND ADDRESS SELECTION OUPUTS ENABLED DATA VALID STANDBY POWER DOWN applying the required high voltage on address pin A9 while the other address line are held at VIL. A Read cycle from address 0000H retrieves the binary code for the IC manufacturer on outputs I/O7 to I/O0: Catalyst Code = 0011 0001 (31H) A Read cycle from address 0001H retrieves the binary code for the device on outputs I/O7 to I/O0: CAT28F001T = 1001 0100 (94H) CAT28F001B = 1001 0101 (95H) Standby Mode With CE at a logic-high level, the CAT28F001 is placed in a standby mode where most of the device circuitry is disabled, thereby substantially reducing power consumption. The outputs are placed in a high-impendance state independent of the OE status. Deep Power-Down When RP is at logic-low level, the CAT28F001 is placed in a Deep Power-Down mode where all the device circuitry are disabled, thereby reducing the power consumption to 0.25µW. ADDRESSES ADDRESS STABLE tAVAV (tRC) CE (E) tEHQZ OE (G) tGHQZ (tDF) WE (W) tGLQX (tOLZ) tELQX (tLZ) tGLQV (tOE) tELQV (tCE) tOH HIGH-Z DATA (I/O) tAVQV (tACC) tPHQV (tPWH) OUTPUT VALID HIGH-Z RP (P) Doc. No. 1078, Rev. I 8 CAT28F001 WRITE OPERATIONS The following operations are initiated by observing the sequence specified in the Write Command Table. Read Array The device can be put into a Read Array Mode by initiating a write cycle with FFH on the data bus. The device is also in a standard Read Array Mode after the initial device power up and when comes out of the Deep Power-Down mode. Signature Mode An alternative method for reading device signature (see Read Operations Signature Mode), is initiated by writing the code 90H into the command register. A read cycle from address 0000H with CE and OE low (and WE high) will output the device signature. Catalyst Code = Catalyst Code = 0011 0001 (31H) A Read cycle from address 0001H retrieves the binary code for the device on outputs I/O7 to I/O0: CAT28F001T = 1001 0100 (94H) CAT28F001B = 1001 0101 (95H) To terminate the operations, it is necessary to write another valid command into the register. STATUS REGISTER The 28F001 contains an 8-bit Status Register. The Status Register is polled to check for write or erase completion or any related errors. The Status Register may be read at any time by issuing a Read Status Register (70H) command. All subsequent read operations output data from the Status Register, until another valid command is issued. The contents of the Status Register are latched on the falling edge of OE or CE , whichever occurs last in the read cycle. OE or CE must be toggled to VIH before further reads to update the status register latch. The Erase Status (SR.5) and Program Status (SR.4) are set to 1 by the WSM and can only be reset issuing Clear Status Register (50H) These two bits can be polled for failures, thus allowing more flexibility to the designer when using the CAT28F001. Also, VPP Status (SR.3) when set to 1 must be reset by system software before any further byte programs or block erases are attempted. ERASE SETUP/ERASE CONFIRM Erase is executed one block at a time, initiated by a two cycle command sequence. The two cycle command sequence provides added security against accidental block erasure. During the first write cycle, a Command 20H (Erase Setup) is first written to the Command Register, followed by the Command D0H (Erase Confirm). These commands require both appropriate command data and an address within Block to be erased. Also, Block erasure can only occur when VPP= VPPH. Block preconditioning, erase and verify are all handled internally by the Write State Machine, invisible to the system. After receiving the two command erase sequence the CAT28F001 automatically outputs Status Register data when read (Fig.5). The CPU can detect the completion of the erase event by checking if the SR.7 of the Status Register is set. SR.5 will indicate whether the erase was successful. If an erase error is detected, the Status Register should be cleared. The device will be in the Status Register Read Mode until another command is issued. ERASE SUSPEND/ERASE RESUME The Erase Suspend Command allows erase sequence interruption in order to read data from another block of memory. Once the erase sequence is started, writing the Erase Suspend command (B0H) to the Command Register requests that the WSM suspend the erase sequence at a predetermined point in the erase algorithm. The CAT28F001 continues to output Status Register data when read, after the Erase Suspend command is written to it. Polling the WSM Status and Erase Suspend Status bits will determine when the erase operation has been suspended (both will be set to “1s”). The device may now be given a Read ARRAY Command, which allows any locations 'not within the block being erased' to be read. Also, you can either perform a Read Status Register or resume the Erase Operation by sending Erase Resume (D0H), at which time the WSM will continue with the erase sequence. The Erase Suspend Status and WSM Status bits of the Status Register will be cleared. PROGRAM SETUP/PROGRAM COMMANDS Programming is executed by a two-write sequence. The program Setup command (40H) is written to the Command Register, followed by a second write specifying the address and data (latched on the rising edge of WE) to be programmed. The WSM then takes over, controlling the program and verify algorithms internally. After the two-command program sequence is written to it, the CAT28F001 automatically outputs Status Register data when read (see figure 4; Byte Program Flowchart). The CPU can detect the completion of the program event by analyzing the WSM Status bit of the Status Register. Only the Read Status Register Command is valid while programming is active. 9 Doc. No. 1078, Rev. I CAT28F001 WSMS 7 ESS 6 ES 5 PS 4 VPPS 3 R 2 R 1 R 0 SR.7 = WRITE STATE MACHINE STATUS 1 = Ready 0 = Busy SR.6 = ERASE SUSPEND STATUS 1 = Erase Suspended 0 = Erase in Progress/Completed SR.5 = ERASE STATUS 1 = Error in Block Erasure 0 = Successful Block Erase SR.4 = PROGRAM STATUS 1 = Error in Byte Program 0 = Successful Byte Program SR.3 = VPP STATUS 1 = VPP Low Detect; Operation Abort 0 = VPP Okay SR.2 -SR.0 = RESERVED FOR FUTURE ENHANCEMENTS These bits are reserved for future use and should be masked out when polling the Status Register. NOTES: The Write State Machine Status Bit must first be checked to determine program or erase completion, before the Program or Erase Status bits are checked for success. If the Program AND Erase Status bits are set to “1s” during an erase attempt, an improper command sequence was entered. Attempt the operation again. If VPP low status is detected, the Status Register must be cleared before another program or erase operation is attempted. The VPP Status bit, unlike an A/D converter, does not provide continuous indication of VPP level. The WSM interrogates the VPP level only after the program or erase command sequences have been entered and informs the system if VPP has not been switched on. The VPP Status bit is not guaranteed to report accurate feedback between VPPL and VPPH. When the Status Register indicates that programming is complete, the Program Status bit should be checked. If program error is detected, the Status Register should be cleared. The internal WSM verify only detects errors for “1s” that do not successfully program to “0s”. The Command Register remains in Read Status Register mode until further commands are issued to it. If erase/byte program is attempted while VPP = VPPL, the Status bit (SR.5/SR.4) will be set to “1”. Erase/Program attempts while VPPL < VPP < VPPH produce spurious results and should not be attempted. EMBEDDED ALGORITHMS The CAT28F001 integrates the Quick Pulse programming algorithm on-chip, using the Command Register, Status Register and Write State Machine (WSM). Onchip integration dramatically simplifies system software and provides processor-like interface timings to the Command and Status Registers. WSM operation, internal program verify, and VPP high voltage presence are monitored and reported via appropriate Status Register bits. Figure 4 shows a system software flowchart for device programming. As above, the Quick Erase algorithm is now implemented internally, including all preconditioning of block data. WSM operation, erase verify and VPP high voltage presence are monitored and reported through the Status Register. Additionally, if a command other than Erase Confirm is written to the device after Erase Setup has been written, both the Erase Status and Program Status bits will be set to “1”. When issuing the Erase Setup and Erase Confirm commands, they should be written to an address within the address range of the block to be erased. Figure 5 shows a system software flowchart for block erase. The entire sequence is performed with VPP at VPPH. Abort occurs when RP transitions to VIL, or VPP drops to VPPL. Although the WSM is halted, byte data is partially programmed or Block data is partially erased at the location where it was aborted. Block erasure or a repeat of byte programming will initialize this data to a known value. BOOT BLOCK PROGRAM AND ERASE The boot block is intended to contain secure code which will minimally bring up a system and control programming and erase of other blocks of the device, if needed. Therefore, additional “lockout” protection is provided to guarantee data integrity. Boot block program and erase operations are enabled through high voltage VHH on either RP or OE, and the normal program and erase command sequences are used. Reference the AC Waveforms for Program/Erase. If boot block program or erase is attempted while RP is at VIH, either the Program Status or Erase Status bit will be set to “1”, reflective of the operation being attempted and indicating boot block lock. Program/erase attempts while VIH < RP < VHH produce spurious results and should not be attempted. 10 Doc. No. 1078, Rev. I CAT28F001 IN-SYSTEM OPERATION For on-board programming, the RP pin is the most convenient means of altering the boot block. Before issuing Program or Erase confirms commands, RP must transition to VHH. Hold RP at this high voltage throughout the program or erase interval (until after Status Register confirm of successful completion). At this time, it can return to VIH or VIL. Figure 4 Byte Programming Flowchart START Bus Operation Command Program Setup Comments Data = 40H Address = Bytes to be Programmed WRITE 40H, BYTE ADDRESS Write WRITE BYTE ADDRESS/DATA Write Program Data to be programmed Address = Byte to be Programmed READ STATUS REGISTER Read Status Register Data. Toggle OE or CE to update Status Register Check SR.7 1 = Ready, 0 = Busy SR.7 = 1? YES FULL STATUS CHECK IF DESIRED NO Standby Repeat for subsequent bytes. Full Status check can be done after each byte or after a sequence of bytes. BYTE PROGRAM COMPLETED Write FFH after the last byte programming operation to reset the device to Read Array Mode. FULL STATUS CHECK PROCEDURE STATUS REGISTER DATA READ (SEE ABOVE) Bus Operation Command Comments Check SR.3 1 = VPP Low Detect SR.3 = 0? YES SR.4 = 0? YES BYTE PROGRAM SUCCESSFUL NO VPP RANGE ERROR Standby NO BYTE PROGRAM ERROR Standby Check SR.3 1 = Byte Program Error SR.3 MUST be cleared, if set during a program attempt, before further attempts are allowed by the Write State Machine. SR.3 is only cleared by the Clear Status Register Command, in case where multiple bytes are programmed before full status is checked. If error is detected, clear the Status Register before attempting retry or other error recovery. 11 Doc. No. 1078, Rev. I CAT28F001 Figure 5 Block Erase Flowchart START Bus Operation Write Command Erase Setup Comments Data = 20H Address = Within Block to be erased WRITE 20H, BLOCK ADDRESS WRITE D0H BLOCK ADDRESS Write Erase Data - D0H Address = Within Block to be erased Status Register Data. Toggle OE or CE to update Status Register Check SR.7 1 = Ready, 0 = Busy READ STATUS REGISTER NO SR.7 = 1? YES FULL STATUS CHECK IF DESIRED NO SUSPEND ERASE? Read ERASE SUSPEND LOOP YES Standby Repeat for subsequent blocks. Full Status check can be done after each block or after a sequence of blocks. Write FFH after the last block erase operation to reset the device to Read Array Mode. BLOCK ERASE COMPLETED FULL STATUS CHECK PROCEDURE STATUS REGISTER DATA READ (SEE ABOVE) Bus Operation VPP RANGE ERROR Command Comments Check SR.3 1 = VPP Low Detect SR.3 = 0? YES SR.4,5 = 1? NO SR.5 = 0? NO Standby YES COMMAND SEQUENCE ERROR Standby Check SR.4 Both 1 = Command Sequence Error NO BLOCK ERASE ERROR Standby Check SR.5 1 = Block Erase Error BLOCK ERASE SUCCESSFUL SR.3 MUST be cleared, if set during a erase attempt, before further attempts are allowed by the Write State Machine. SR.3 is only cleared by the Clear Status Register Command, in cases where multiple blocks are erased before full status is checked. If error is detected, clear the Status Register before attempting retry or other error recovery. Doc. No. 1078, Rev. I 12 CAT28F001 Figure 6 Block Erase Suspend/Resume Flowchart START Bus Operation Command Write Erase Suspend Comments Data = B0H WRITE B0H Standby/ Ready READ STATUS REGISTER Read Status Register Check SR.7 1 = Ready, 0 = Busy Toggle OE or CE to Update Status Register SR.7 = 1? YES NO Standby SR.6 = 1? YES WRITE FFH NO ERASE HAS COMPLETED Check SR.6 1 = Suspended Write Read Array Data = FFH Read DONE READING? YES NO Read array data from block other than that being erased. Write Erase Resume Data = D0H WRITE D0H CONTINUE ERASE 13 Doc. No. 1078, Rev. I CAT28F001 Figure 7. A.C. Timing for Program/Erase Operation VCC POWER-UP & STANDBY WRITE WRITE PROGRAM OR VALID ADDRESS & DATA (PROGRAM) AUTOMATED PROGRAM ERASE SETUP COMMAND OR ERASE DELAY OR ERASE CONFIRM COMMAND READ STATUS REGISTER DATA WRITE READ ARRAY COMMAND VIH ADDRESSES (A) VIL VIH CE (E) VIL VIH OE (G) VIL VIH WE (W) VIL VIH DATA (I/O) VIL VHH 6.5V VIH VIL VPPH VPP (V) VPPL VIH VIL tVPWH tQVVL tPHWL tPHHWH tDVWH HIGH Z DIN DIN VALID SRD tQVPH DIN tWLWH tWHDX tWHWL tWHQV 1, 2, 3, 4 tELWL tWHEH AIN tAVAV tAVWH AIN tWHAX tWHGL RP (P) POWER UP/DOWN PROTECTION The CAT28F001 offers protection against inadvertent programming during VPP and VCC power transitions. When powering up the device there is no power-on sequencing necessary. In other words, VPP and VCC may power up in any order. Additionally VPP may be hardwired to VPPH independent of the state of VCC and any power up/down cycling. The internal command register of the CAT28F001 is reset to the Read Mode on power up. POWER SUPPLY DECOUPLING To reduce the effect of transient power supply voltage spikes, it is good practice to use a 0.1µF ceramic capacitor between VCC and VSS and VPP and VSS. These high-frequency capacitors should be placed as close as possible to the device for optimum decoupling. Doc. No. 1078, Rev. I 14 CAT28F001 ALTERNATE CE-CONTROLLED WRITES VCC = +5V ±10%, unless otherwise specified JEDEC Symbol tAVAV tAVEH tEHAX tDVEH tEHDX tWLEL tEHWH tELEH tEHEL tEHGL tPHEL tPHHEH tVPEH tEHQV1 tEHQV2 tEHQV3 tEHQV4 tQVVL tQVPH tPHBR(1) tGHHWL tWHGH Standard Symbol tWC tAS tAH tDS tDH tWS tWH tCP tEPH — tPS(1) tPHS tVPS — — — — tVPH(1) tPHH(1) — — — (1) (1) Parameter Write Cycle Time Address Setup to CE Going High Address Hold Time from CE Going High Data Setup Time to CE Going High Data Hold Time from CE Going High WE Setup Time to CE Going Low WE Hold Time from CE Going High CE Pulse Width CE High Pulse Width Write Recovery Time Before Read RP High Recovery to CE Going Low RP VHH Setup to CE Going High VPP Setup to CE Going High Duration of Programming Operations Duration of Erase Operations (Boot) Duration of Erase Operations (Parameter) Duration of Erase Operations (Main) VPP Hold from Valid Status Reg Data RP VHH Hold from Status Reg Data Boot Block Relock Delay OE VHH Setup to WE Going Low OE VHH Hold from WE High 28F001-90 Min Max 90 40 10 40 10 0 0 40 10 0 480 100 100 15 1.3 1.3 3 0 0 100 480 480 28F001-12 Min Max 120 40 10 40 10 0 0 40 10 0 480 100 100 15 1.3 1.3 3 0 0 100 480 480 Units ns ns ns ns ns ns ns ns ns µs ns ns ns µs Sec Sec Sec ns ns ns ns ns Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. 15 Doc. No. 1078, Rev. I CAT28F001 Figure 8. Alternate Boot Block Access Method Using OE WRITE PROGRAM OR ERASE SETUP COMMAND WRITE VALID ADDRESS AND DATA (PROGRAM) OR ERASE CONFIRM COMMAND AUTOMATED PROGRAM OR ERASE DELAY READ STATUS REGISTER DATA OE VHH VIH VIL tGHHWL tWHGH WE VIH VIL DATA VIH VIL DIN DIN VALID SR DATA Figure 9. Alternate AC Waveform for Write Operations VCC POWER-UP & STANDBY WRITE WRITE PROGRAM OR VALID ADDRESS & DATA (PROGRAM) AUTOMATED PROGRAM ERASE SETUP COMMAND OR ERASE DELAY OR ERASE CONFIRM COMMAND READ STATUS REGISTER DATA WRITE READ ARRAY COMMAND VIH ADDRESSES VIL VIH WE (W) VIL VIH OE (a) VIL VIH CE (E) VIL VIH DATA I/O VIL VHH 6.5V VIH VIL VPPH VPP (V) VPPL VIH VIL tVPEH tQVVL tPHEL tPHHEH tDVEH HIGH Z DIN DIN VALID SRD tQVPH DIN tELEH tEHDX tEHEL tEHQV 1, 2, 3, 4 tWLEL tEHWH AIN tAVAV tAVEH AIN tEHAX tEHGL RP (P) Doc. No. 1078, Rev. I 16 CAT28F001 ORDERING INFORMATION Prefix CAT Device # 28F001 Suffix P I -90 B T Optional Company ID Product Number Temperature Range Blank = Commercial (0˚ - 70˚C) I = Industrial (-40˚ - 85˚C) A = Automotive (-40˚ - 105˚C)* Package N: PLCC P: PDIP T: TSOP(8mmx20mm) G: PLCC (Lead free, Halogen free) L: PDIP (Lead free, Halogen free) H: TSOP (Lead free, Halogen free) Boot Block B: Bottom T: Top Tape & Reel Speed 90: 90 ns 12: 120 ns * -40˚ to +125˚C is available upon request Note: (1) The device used in the above example is a CAT28F001PI-90BT (PDIP, Industrial Temperature, 90ns access time, Bottom Boot Block, Tape & Reel) 17 Doc. No. 1078, Rev. I REVISION HISTORY Date 04/20/04 Revision Comments G Delete data sheet designation Update Features Update Pin Configuration Update Ordering Information Update A. C. Tables Update Erase Table Update Alternate Table Update Ordering Information Update Revision History Update Rev Number Update Ordering Information Update Ordering Information 09/21/04 03/29/05 H I Copyrights, Trademarks and Patents Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: DPP ™ AE2 ™ Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000. 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Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete. Catalyst Semiconductor, Inc. Corporate Headquarters 1250 Borregas Avenue Sunnyvale, CA 94089 Phone: 408.542.1000 Fax: 408.542.1200 www.catalyst-semiconductor.com Publication #: Revison: Issue date: 1078 I 03/29/05