CAT28F512NA-12T

CAT28F512 512K-Bit CMOS Flash Memory Licensed Intel second source FEATURES I Fast Read Access Time: 90/120/150 ns I Low Power CMOS Dissipation: H GEN FR ALO EE LE A D F R E ETM I Commercial, Industrial and Automotive Temperature Ranges I Stop Timer for Program/Erase I On-Chip Address and Data Latches I JEDEC Standard Pinouts: –Active: 30 mA max (CMOS/TTL levels) –Standby: 1 mA max (TTL levels) –Standby: 100 µA max (CMOS levels) I High Speed Programming: –10 µs per byte –1 Sec Typ Chip Program I 12.0V ± 5% Programming and Erase Voltage –32-pin DIP –32-pin PLCC –32-pin TSOP ( 8 x 20) I 100,000 Program/Erase Cycles I 10 Year Data Retention I "Green" Package Options Available I Electronic Signature DESCRIPTION The CAT28F512 is a high speed 64K x 8-bit electrically erasable and reprogrammable Flash memory ideally suited for applications requiring in-system or after-sale code updates. Electrical erasure of the full memory contents is achieved typically within 0.5 second. It is pin and Read timing compatible with standard EPROM and EEPROM devices. Programming and Erase are performed through an operation and verify algorithm. The instructions are input via the I/O bus, using a two write cycle scheme. Address and Data are latched to free the I/O bus and address bus during the write operation. The CAT28F512 is manufactured using Catalyst’s advanced CMOS floating gate technology. It is designed to endure 100,000 program/erase cycles and has a data retention of 10 years. The device is available in JEDEC approved 32-pin plastic DIP, 32-pin PLCC or 32-pin TSOP packages. BLOCK DIAGRAM I/O0–I/O7 I/O BUFFERS ERASE VOLTAGE SWITCH WE COMMAND REGISTER PROGRAM VOLTAGE SWITCH CE, OE LOGIC DATA LATCH SENSE AMP CE OE ADDRESS LATCH Y-GATING Y-DECODER 524,288 BIT MEMORY ARRAY A0–A15 X-DECODER VOLTAGE VERIFY SWITCH © 2004 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 1 Doc. No. 1084, Rev. H CAT28F512 PIN CONFIGURATION PIN FUNCTIONS Pin Name A0–A15 Type Input I/O Input Input Input Function Address Inputs for memory addressing Data Input/Output Chip Enable Output Enable Write Enable Voltage Supply Ground Program/Erase Voltage Supply DIP Package (P, L) PLCC Package (N, G) I/O0–I/O7 VPP NC A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC WE N/C A14 A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 28F512 F01 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 A12 A15 NC VPP VCC WE N/C CE OE 29 28 27 26 25 24 23 22 A14 A13 A8 A9 A11 OE A10 CE I/O7 4 5 6 7 8 9 10 11 12 3 2 1 32 31 30 WE VCC VSS VPP 13 21 14 15 16 17 18 19 20 I/O1 I/O2 VSS I/O3 TSOP Package (Standard Pinout 8mm x 20mm) (T, H) A11 A9 A8 A13 A14 NC WE VCC VPP NC A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 VSS I/O2 I/O1 I/O0 A0 A1 A2 A3 TSOP Package (Reverse Pinout) (TR, HR) OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 VSS I/O2 I/O1 I/O0 A0 A1 A2 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A11 A9 A8 A13 A14 NC WE VCC VPP NC A15 A12 A7 A6 A5 A4 28F512 F03 I/O4 I/O5 I/O6 Doc. No. 1084, Rev. H 2 CAT28F512 ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias ................... –55°C to +95°C Storage Temperature ....................... –65°C to +150°C Voltage on Any Pin with Respect to Ground(1) ........... –2.0V to +VCC + 2.0V Voltage on Pin A9 with Respect to Ground(1) ................... –2.0V to +13.5V VPP with Respect to Ground during Program/Erase(1) .............. –2.0V to +14.0V VCC with Respect to Ground(1) ............ –2.0V to +7.0V Package Power Dissipation Capability (TA = 25°C) .................................. 1.0 W Lead Soldering Temperature (10 secs) ............ 300°C Output Short Circuit Current(2) ........................ 100 mA RELIABILITY CHARACTERISTICS Symbol NEND (3) *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Parameter Endurance Data Retention ESD Susceptibility Latch-Up Min. 100K 10 2000 100 Max. Units Cycles/Byte Years Volts mA Test Method MIL-STD-883, Test Method 1033 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 3015 JEDEC Standard 17 TDR(3) VZAP(3) ILTH(3)(4) CAPACITANCE TA = 25°C, f = 1.0 MHz Limits Symbol CIN (3) Test Input Pin Capacitance Output Pin Capacitance VPP Supply Capacitance Min Max. 6 10 25 Units pF pF pF Conditions VIN = 0V VOUT = 0V VPP = 0V COUT(3) CVPP (3) Note: (1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns. (2) Output shorted for no more than one second. No more than one output shorted at a time. (3) This parameter is tested initially and after a design or process change that affects the parameter. (4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V. 3 Doc. No. 1084, Rev. H CAT28F512 D.C. OPERATING CHARACTERISTICS VCC = +5V ±10%, unless otherwise specified. Limits Symbol ILI ILO ISB1 ISB2 ICC1 ICC2(1) ICC3(1) ICC4(1) IPPS IPP1 IPP2(1) IPP3(1) IPP4(1) VIL VILC VOL VIH VIHC VOH1 VOH2 VID IID(1) VLO Parameter Input Leakage Current Output Leakage Current VCC Standby Current CMOS VCC Standby Current TTL VCC Active Read Current VCC Programming Current VCC Erase Current VCC Prog./Erase Verify Current VPP Standby Current VPP Read Current VPP Programming Current VPP Erase Current VPP Prog./Erase Verify Current Input Low Level TTL Input Low Level CMOS Output Low Level Input High Level TTL Input High Level CMOS Output High Level TTL Output High Level CMOS A9 Signature Voltage A9 Signature Current VCC Erase/Prog. Lockout Voltage 2.5 2 VCC*0.7 2.4 VCC–0.4 11.4 13 200 –0.5 –0.5 Min. Max. ±1 ±1 100 1 30 15 15 15 ±10 200 30 30 5 0.8 0.8 0.45 VCC+0.5 VCC+0.5 Unit µA µA µA mA mA mA mA mA µA µA mA mA mA V V V V V V V V µA V IOH = –2.5mA, VCC = 4.5V IOH = –400µA, VCC = 4.5V A9 = VID A9 = VID IOL = 5.8mA, VCC = 4.5V Test Conditions VIN = VCC or VSS VCC = 5.5V, OE = VIH VOUT = VCC or VSS, VCC = 5.5V, OE = VIH CE = VCC ±0.5V, VCC = 5.5V CE = VIH, VCC = 5.5V VCC = 5.5V, CE = VIL, IOUT = 0mA, f = 6 MHz VCC = 5.5V, Programming in Progress VCC = 5.5V, Erasure in Progress VCC = 5.5V, Program or Erase Verify in Progress VPP = VPPL VPP = VPPH VPP = VPPH, Programming in Progress VPP = VPPH, Erasure in Progress VPP = VPPH, Program or Erase Verify in Progress Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. Doc. No. 1084, Rev. H 4 CAT28F512 SUPPLY CHARACTERISTICS Limits Symbol VCC VPPL VPPH Parameter VCC Supply Voltage VPP During Read Operations VPP During Read/Erase/Program Min 4.5 0 11.4 Max. 5.5 6.5 12.6 Unit V V V A.C. CHARACTERISTICS, Read Operation VCC = +5V ±10%, unless otherwise specified. JEDEC Standard Symbol tAVAV tELQV tAVQV tGLQV tAXQX tGLQX tELQX tGHQZ tEHQZ tWHGL(1) Symbol tRC tCE tACC tOE tOH Parameter Read Cycle Time CE Access Time Address Access Time OE Access Time Output Hold from Address OE/CE Change 0 0 0 20 30 6 6 28F512-90 Min. Max. 90 90 90 35 0 0 0 30 40 6 28F512-12 28F512-15 Min. Max. Min. Max. Unit 120 120 120 50 0 0 0 35 45 150 150 150 55 ns ns ns ns ns ns ns ns ns µs tOLZ(1)(6) OE to Output in Low-Z tLZ(1)(6) tDF(1)(2) tDF(1)(2) CE to Output in Low-Z OE High to Output High-Z CE High to Output High-Z Write Recovery Time Before Read Figure 1. A.C. Testing Input/Output Waveform(3)(4)(5) 2.4 V INPUT PULSE LEVELS 0.45 V 0.8 V 2.0 V REFERENCE POINTS Figure 2. A.C. Testing Load Circuit (example) 1.3V 1N914 3.3K DEVICE UNDER TEST OUT CL = 100 pF CL INCLUDES JIG CAPACITANCE Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) Output floating (High-Z) is defined as the state where the external data line is no longer driven by the output buffer. (3) Input Rise and Fall Times (10% to 90%) < 10 ns. (4) Input Pulse Levels = 0.45V and 2.4V. (5) Input and Output Timing Reference = 0.8V and 2.0V. (6) Low-Z is defined as the state where the external data may be driven by the output buffer but may not be valid. 5 Doc. No. 1084, Rev. H CAT28F512 A.C. CHARACTERISTICS, Program/Erase Operation VCC = +5V ±10%, unless otherwise specified. JEDEC Symbol tAVAV tAVWL tWLAX tDVWH tWHDX tELWL tWHEH tWLWH tWHWL tWHWH1(2) tWHWH2 tWHGL tGHWL tVPEL (2) Standard Symbol tWC tAS tAH tDS tDH tCS tCH tWP tWPH Parameter Write Cycle Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time CE Setup Time CE Hold Time WE Pulse Width WE High Pulse Width Program Pulse Width Erase Pulse Width Write Recovery Time Before Read Read Recovery Time Before Write VPP Setup Time to CE 28F512-90 90 0 40 40 10 0 0 40 20 10 9.5 6 0 100 28F512-12 120 0 40 40 10 0 0 40 20 10 9.5 6 0 100 28F512-15 150 0 40 40 10 0 0 40 20 10 9.5 6 0 100 ns ns ns ns ns ns ns ns ns µs ms µs µs ns Min. Max. Min. Max. Min. Max. Unit ERASE AND PROGRAMMING PERFORMANCE(1) 28F512-90 Parameter Chip Erase Time(3)(5) Chip Program Time(3)(4) Min. Typ. 0.5 1 Max. 10 6 28F512-12 Min. Typ. 0.5 1 Max. 10 6 28F512-15 Min. Typ. 0.5 1 Max. 10 6 Unit sec sec Note: (1) Please refer to Supply characteristics for the value of VPPH and VPPL. The VPP supply can be either hardwired or switched. If VPP is switched, VPPL can be ground, less than VCC + 2.0V or a no connect with a resistor tied to ground. (2) Program and Erase operations are controlled by internal stop timers. (3) ‘Typicals’ are not guaranteed, but based on characterization data. Data taken at 25°C, 12.0V VPP. (4) Minimum byte programming time (excluding system overhead) is 16 µs (10 µs program + 6 µs write recovery), while maximum is 400 µs/ byte (16 µs x 25 loops). Max chip programming time is specified lower than the worst case allowed by the programming algorithm since most bytes program significantly faster than the worst case byte. (5) Excludes 00H Programming prior to Erasure. Doc. No. 1084, Rev. H 6 CAT28F512 FUNCTION TABLE(1) Pins Mode Read Output Disable Standby Signature (MFG) Signature (Device) Program/Erase Write Cycle Read Cycle WRITE COMMAND TABLE Commands are written into the command register in one or two write cycles. The command register can be altered only when VPP is high and the instruction byte is latched on the rising edge of WE. Write cycles also internally latch addresses and data required for programming and erase operations. Pins First Bus Cycle Mode Set Read Read Sig. (MFG) Read Sig. (Device) Erase Erase Verify Program Program Verify Reset Operation Write Write Write Write Write Write Write Write Address X X X X AIN X X X DIN 00H 90H 90H 20H A0H 40H C0H FFH Operation Read Read Read Write Read Write Read Write Second Bus Cycle Address AIN 00 01 X X AIN X X FFH DIN DOUT 20H DOUT DIN DOUT DOUT 31H B8H CE VIL VIL VIH VIL VIL VIL VIL VIL OE VIL VIH X VIL VIL VIH VIH VIL WE VIH VIH X VIH VIH VIL VIL VIH VPP VPPL X VPPL X X VPPH VPPH VPPH I/O DOUT High-Z High-Z 31H B8H DIN DIN DOUT A0 = VIL, A9 = 12V A0 = VIH, A9 = 12V See Command Table During Write Cycle During Write Cycle Notes Note: (1) Logic Levels: X = Logic ‘Do not care’ (VIH, VIL, VPPL, VPPH) 7 Doc. No. 1084, Rev. H CAT28F512 READ OPERATIONS Read Mode A Read operation is performed with both CE and OE low and with WE high. VPP can be either high or low, however, if VPP is high, the Set READ command has to be sent before reading data (see Write Operations). The data retrieved from the I/O pins reflects the contents of the memory location corresponding to the state of the 16 address pins. The respective timing waveforms for the read operation are shown in Figure 3. Refer to the AC Read characteristics for specific timing parameters. Signature Mode The signature mode allows the user to identify the IC manufacturer and the type of device while the device resides in the target system. This mode can be activated in either of two ways; through the conventional method of applying a high voltage (12V) to address pin A9 or by sending an instruction to the command register (see Write Operations). The conventional mode is entered as a regular READ mode by driving the CE and OE pins low (with WE high), and applying the required high voltage on address pin A9 while all other address lines are held at VIL. A Read cycle from address 0000H retrieves the binary code for the IC manufacturer on outputs I/O0 to I/O7: CATALYST Code = 00110001 (31H) A Read cycle from address 0001H retrieves the binary code for the device on outputs I/O0 to I/O7. 28F512 Code = 1011 1000 (B8H) Standby Mode With CE at a logic-high level, the CAT28F512 is placed in a standby mode where most of the device circuitry is disabled, thereby substantially reducing power consumption. The outputs are placed in a high-impedance state. Figure 3. A.C. Timing for Read Operation POWER UP STANDBY DEVICE AND ADDRESS SELECTION OUPUTS ENABLED DATA VALID STANDBY POWER DOWN ADDRESSES ADDRESS STABLE tAVAV (tRC) CE (E) tEHQZ (tDF) OE (G) tWHGL tGHQZ (tDF) tGLQV (tOE) tELQV (tCE) tGLQX (tOLZ) tELQX (tLZ) tAXQX (tOH) WE (W) HIGH-Z DATA (I/O) tAVQV (tACC) OUTPUT VALID HIGH-Z Doc. No. 1084, Rev. H 8 CAT28F512 WRITE OPERATIONS The following operations are initiated by observing the sequence specified in the Write Command Table. Read Mode The device can be put into a standard READ mode by initiating a write cycle with 00H on the data bus. The subsequent read cycles will be performed similar to a standard EPROM or EEPROM Read. Signature Mode An alternative method for reading device signature (see Read Operations Signature Mode), is initiated by writing the code 90H into the command register while keeping VPP high. A read cycle from address 0000H with CE and OE low (and WE high) will output the device signature. CATALYST Code = 00110001 (31H) A Read cycle from address 0001H retrieves the binary code for the device on outputs I/O0 to I/O7. 28F512 Code = 1011 1000 (B8H) Figure 4. A.C. Timing for Erase Operation VCC POWER-UP & STANDBY SETUP ERASE COMMAND ERASE COMMAND ERASING Erase Mode During the first Write cycle, the command 20H is written into the command register. In order to commence the erase operation, the identical command of 20H has to be written again into the register. This two-step process ensures against accidental erasure of the memory contents. The final erase cycle will be stopped at the rising edge of WE, at which time the Erase Verify command (A0H) is sent to the command register. During this cycle, the address to be verified is sent to the address bus and latched when WE goes low. An integrated stop timer allows for automatic timing control over this operation, eliminating the need for a maximum erase timing specification. Refer to AC Characteristics (Program/Erase) for specific timing parameters. ERASE VERIFY COMMAND ERASE VCC POWER-DOWN/ VERIFICATION STANDBY ADDRESSES tWC tWC tAS CE (E) tCS tCH OE (G) tGHWL tWPH WE (W) tWP tDS HIGH-Z DATA (I/O) DATA IN = 20H tDH tDS tWP tDH tWP tDS tDH DATA IN = A0H tLZ tCE VCC 5.0V 0V VPP VPPH VPPL tVPEL VALID DATA OUT tOE tOLZ tOH tWHWH2 tWHGL tDF tCH tCS tCH tEHQZ tWC tAH tRC DATA IN = 20H 9 Doc. No. 1084, Rev. H CAT28F512 Figure 5. Chip Erase Algorithm(1) START ERASURE BUS OPERATION COMMAND COMMENTS APPLY VPPH VPP RAMPS TO VPPH (OR VPP HARDWIRED) ALL BYTES SHALL BE PROGRAMMED TO 00 BEFORE AN ERASE OPERATION INITIALIZE ADDRESS PROGRAM ALL BYTES TO 00H STANDBY INITIALIZE ADDRESS INITIALIZE PLSCNT = 0 PLSCNT = PULSE COUNT WRITE ERASE SETUP COMMAND WRITE ERASE ACTUAL ERASE NEEDS 10ms PULSE, DATA = 20H DATA = 20H WRITE ERASE COMMAND WRITE ERASE DATA = 20H TIME OUT 10ms WAIT WRITE ERASE VERIFY COMMAND WRITE ERASE VERIFY ADDRESS = BYTE TO VERIFY 40H; DATA = 20H; A0H STOPS ERASE OPERATION TIME OUT 6µs INCREMENT ADDRESS READ DATA FROM DEVICE NO DATA = FFH? YES NO LAST ADDRESS? YES WRITE READ COMMAND WRITE READ NO INC PLSCNT 1000 = 3000 ? YES STANDBY READ WAIT READ BYTE TO VERIFY ERASURE COMPARE OUTPUT TO FF INCREMENT PULSE COUNT DATA = 00H RESETS THE REGISTER FOR READ OPERATION VPP RAMPS TO VPPL (OR VPP HARDWIRED) APPLY VPPL APPLY VPPL STANDBY ERASURE COMPLETED ERASE ERROR Note: (1) The algorithm MUST BE FOLLOWED to ensure proper and reliable operation of the device. Doc. No. 1084, Rev. H 10 CAT28F512 Erase-Verify Mode The Erase-verify operation is performed on every byte after each erase pulse to verify that the bits have been erased. Programming Mode The programming operation is initiated using the programming algorithm of Figure 7. During the first write cycle, the command 40H is written into the command register. During the second write cycle, the address of the memory location to be programmed is latched on the falling edge of WE, while the data is latched on the rising edge of WE. The program operation terminates with the next rising edge of WE. An integrated stop timer allows for automatic timing control over this operation, eliminating the need for a maximum program timing specification. Refer to AC Characteristics (Program/Erase) for specific timing parameters. Program-Verify Mode A Program-verify cycle is performed to ensure that all bits have been correctly programmed following each byte programming operation. The specific address is already latched from the write cycle just completed, and stays latched until the verify is completed. The Programverify operation is initiated by writing C0H into the command register. An internal reference generates the necessary high voltages so that the user does not need to modify VCC. Refer to AC Characteristics (Program/ Erase) for specific timing parameters. Figure 6. A.C. Timing for Programming Operation PROGRAM VCC POWER-UP SETUP PROGRAM LATCH ADDRESS COMMAND & DATA VERIFY & STANDBY PROGRAMMING COMMAND PROGRAM VCC POWER-DOWN/ VERIFICATION STANDBY ADDRESSES tWC tAS CE (E) tCS tCH OE (G) tGHWL tWPH WE (W) tWP tDS HIGH-Z DATA (I/O) DATA IN = 40H tDH tDS tWP tDH tWP tDS tDH DATA IN = C0H tLZ tCE VCC 5.0V 0V VPP VPPH VPPL tVPEL VALID DATA OUT tOE tOLZ tOH tWHWH1 tWHGL tDF tCH tCS tCH tEHQZ tAH tWC tRC DATA IN 11 Doc. No. 1084, Rev. H CAT28F512 Figure 7. Programming Algorithm(1) START PROGRAMMING BUS OPERATION COMMAND COMMENTS APPLY VPPH STANDBY VPP RAMPS TO VPPH (OR VPP HARDWIRED) INITIALIZE ADDRESS INITIALIZE ADDRESS PLSCNT = 0 INITIALIZE PULSE COUNT PLSCNT = PULSE COUNT WRITE SETUP PROG. COMMAND 1ST WRITE CYCLE WRITE SETUP DATA = 40H WRITE PROG. CMD ADDR AND DATA 2ND WRITE CYCLE PROGRAM VALID ADDRESS AND DATA TIME OUT 10µs WAIT WRITE PROGRAM VERIFY COMMAND 1ST WRITE CYCLE PROGRAM VERIFY DATA = C0H TIME OUT 6µs WAIT READ DATA FROM DEVICE NO VERIFY DATA ? YES INCREMENT ADDRESS NO LAST ADDRESS? YES WRITE READ COMMAND NO INC PLSCNT = 25 ? YES READ READ BYTE TO VERIFY PROGRAMMING STANDBY COMPARE DATA OUTPUT TO DATA EXPECTED 1ST WRITE CYCLE READ DATA = 00H SETS THE REGISTER FOR READ OPERATION VPP RAMPS TO VPPL (OR VPP HARDWIRED) APPLY VPPL APPLY VPPL STANDBY PROGRAMMING COMPLETED PROGRAM ERROR Note: (1) The algorithm MUST BE FOLLOWED to ensure proper and reliable operation of the device. Doc. No. 1084, Rev. H 12 CAT28F512 Abort/Reset An Abort/Reset command is available to allow the user to safely abort an erase or program sequence. Two consecutive program cycles with FFH on the data bus will abort an erase or a program operation. The abort/ reset operation can interrupt at any time in a program or erase operation and the device is reset to the Read Mode. POWER UP/DOWN PROTECTION The CAT28F512 offers protection against inadvertent programming during VPP and VCC power transitions. When powering up the device there is no power-on sequencing necessary. In other words, VPP and VCC may power up in any order. Additionally VPP may be hardwired to VPPH independent of the state of VCC and any power up/down cycling. The internal command register of the CAT28F512 is reset to the Read Mode on power up. POWER SUPPLY DECOUPLING To reduce the effect of transient power supply voltage spikes, it is good practice to use a 0.1µF ceramic capacitor between VCC and VSS and VPP and VSS. These high-frequency capacitors should be placed as close as possible to the device for optimum decoupling. Figure 8. Alternate A.C. Timing for Program Operation PROGRAM VCC POWER-UP SETUP PROGRAM LATCH ADDRESS COMMAND & DATA VERIFY & STANDBY PROGRAMMING COMMAND PROGRAM VCC POWER-DOWN/ VERIFICATION STANDBY ADDRESSES tWC tAVEL WE (E) tWLEL tEHWH OE (G) tGHEL CE (W) tEHDX DATA IN = 40H tELEH tDVEH DATA IN tELEH tEHDX tDVEH DATA IN = C0H tLZ tCE VCC 5.0V 0V VPP VPPH VPPL tVPEL VALID DATA OUT tOE tEHDX tOLZ tOH tEHEH tEHEL tEHGL tDF tWLEL tEHWH tWLEL tEHWH tEHQZ tELAX tWC tRC tDVEH HIGH-Z DATA (I/O) 13 Doc. No. 1084, Rev. H CAT28F512 ALTERNATE CE-CONTROLLED WRITES CE JEDEC Standard Symbol Symbol tAVAV tAVEL tELAX tDVEH tEHDX tEHGL tGHEL tWLEL tEHWH tELEH tEHEL tVPEL tWC tAS tAH tDS tDH tWS tCP tCPH Parameter Write Cycle Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time Write Recovery Time Before Read Read Recovery Time Before Write WE Setup Time Before CE WE Hold Time After CE Write Pulse Width Write Pulse Width High VPP Setup Time to CE Low 28F512-90 90 0 40 40 10 6 0 0 0 40 20 100 28F512-12 120 0 40 40 10 6 0 0 0 40 20 100 28F512-15 Unit ns ns ns ns ns µs µs ns ns ns ns ns 120 0 40 40 10 6 0 0 0 40 20 100 Min. Max. Min. Max. Min. Max. ORDERING INFORMATION Prefix CAT Device # 28F512 N Suffix I -90 T Product Number Temperature Range Blank = Commercial (0˚C to +70˚C) I = Industrial (-40˚C to +85˚C) A = Automotive (-40˚C to +105˚C)* Tape & Reel T: 500/Reel Optional Company ID Package N: PLCC P: PDIP T: TSOP (8mmx20mm) TR: TSOP (Reverse Pinout) G: PLCC (Lead free, Halogen free) L: PDIP (Lead free, Halogen free) H: TSOP (Lead free, Halogen free) HR: TSOP (Reverse Pinout) (Lead free, Halogen free) Speed 90: 90ns 12: 120ns 15: 150ns * -40˚C to +125˚C is available upon request Notes: (1) The device used in the above example is a CAT28F512NI-90T (PLCC, Industrial Temperature, 90ns Access Time, Tape & Reel) Doc. No. 1084, Rev. H 14 REVISION HISTORY Date 04/20/04 Revision Comments G Added Green packages in all areas. Delete data sheet designation Update Features Update Description Update Pin Configuration Update Write Operations Update Ordering Information Update Revision History Update Rev Number 07/02/04 H Update Ordering Information Copyrights, Trademarks and Patents Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: DPP ™ AE2 ™ Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000. 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Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete. Catalyst Semiconductor, Inc. Corporate Headquarters 1250 Borregas Avenue Sunnyvale, CA 94089 Phone: 408.542.1000 Fax: 408.542.1200 www.catalyst-semiconductor.com Publication #: Revison: Issue date: 1084 H 7/2/04