CAT28LV256H13E-30T

CAT28LV256 256K-Bit CMOS PARALLEL E2PROM FEATURES s 3.0V to 3.6V Supply s Read Access Times: 200/250/300 ns s Low Power CMOS Dissipation: s CMOS and TTL Compatible I/O s Automatic Page Write Operation: H GEN FR ALO EE LE A D F R E ETM – Active: 15 mA Max. – Standby: 150 µA Max. s Simple Write Operation: – 1 to 64 Bytes in 10ms – Page Load Timer s End of Write Detection: – On-Chip Address and Data Latches – Self-Timed Write Cycle with Auto-Clear s Fast Write Cycle Time: – Toggle Bit – DATA Polling DATA s Hardware and Software Write Protection s 100,000 Program/Erase Cycles s 100 Year Data Retention – 10ms Max. s Commercial, Industrial and Automotive Temperature Ranges DESCRIPTION The CAT28LV256 is a fast, low power, low voltage CMOS Parallel E2PROM organized as 32K x 8-bits. It requires a simple interface for in-system programming. On-chip address and data latches, self-timed write cycle with auto-clear and VCC power up/down write protection eliminate additional timing and protection hardware. DATA Polling and Toggle status bits signal the start and end of the self-timed write cycle. Additionally, the CAT28LV256 features hardware and software write protection. The CAT28LV256 is manufactured using Catalyst’s advanced CMOS floating gate technology. It is designed to endure 100,000 program/erase cycles and has a data retention of 100 years. The device is available in JEDEC– approved 28-pin DIP, 28-pin TSOP or 32-pin PLCC packages. BLOCK DIAGRAM A6–A14 ADDR. BUFFER & LATCHES INADVERTENT WRITE PROTECTION ROW DECODER 32,768 x 8 E2PROM ARRAY 64 BYTE PAGE REGISTER VCC HIGH VOLTAGE GENERATOR CE OE WE CONTROL LOGIC I/O BUFFERS TIMER DATA POLLING AND TOGGLE BIT COLUMN DECODER 28LV256 F01 I/O0–I/O7 A0–A5 ADDR. BUFFER & LATCHES © 2004 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 1 Doc. No. 1071, Rev. B CAT28LV256 PIN CONFIGURATION DIP Package (P, L) PLCC Package (N, G) A7 A12 A14 NC VCC WE A13 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 A6 A5 A4 A3 A2 A1 A0 NC I/O0 5 6 7 8 9 4 3 2 1 32 31 30 29 28 27 TOP VIEW 26 25 24 23 A8 A9 A11 NC OE A10 CE I/O7 I/O6 10 11 12 22 13 21 14 15 16 17 18 19 20 I/O1 I/O2 VSS NC I/O3 I/O4 I/O5 28 27 26 25 24 23 22 21 20 19 18 17 16 15 TSOP Top View (8mm X 13.4mm) (T13, H13) OE A11 A9 A8 A13 WE VCC A14 A12 A7 A6 A5 A4 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 PIN FUNCTIONS Pin Name A0–A14 I/O0–I/O7 CE OE Function Address Inputs Data Inputs/Outputs Chip Enable Output Enable Pin Name WE VCC VSS NC Function Write Enable 3.0 to 3.6 V Supply Ground No Connect Doc. No. 1071, Rev. B 2 CAT28LV256 ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias ................. –55°C to +125°C Storage Temperature ....................... –65°C to +150°C Voltage on Any Pin with Respect to Ground(2) ........... –2.0V to +VCC + 2.0V VCC with Respect to Ground ............... –2.0V to +7.0V Package Power Dissipation Capability (Ta = 25°C) ................................... 1.0W Lead Soldering Temperature (10 secs) ............ 300°C Output Short Circuit Current(3) ........................ 100 mA RELIABILITY CHARACTERISTICS Symbol NEND (1) *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Parameter Endurance Data Retention ESD Susceptibility Latch-Up Min. 100,000 100 2000 100 Max. Units Cycles/Byte Years Volts mA Test Method MIL-STD-883, Test Method 1033 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 3015 JEDEC Standard 17 TDR(1) VZAP (1) ILTH(1)(4) CAPACITANCE TA = 25°C, f = 1.0 MHz Symbol CI/O(1) CIN(1) Test Input/Output Capacitance Input Capacitance Max. 10 6 Units pF pF Conditions VI/O = 0V VIN = 0V MODE SELECTION Mode Read Byte Write (WE Controlled) Byte Write (CE Controlled) Standby, and Write Inhibit Read and Write Inhibit H X CE L L L X H WE H OE L H H X H I/O DOUT DIN DIN High-Z High-Z Power ACTIVE ACTIVE ACTIVE STANDBY ACTIVE Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns. (3) Output shorted for no more than one second. No more than one output shorted at a time. (4) Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC +1V. 3 Doc. No. 1071, Rev. B CAT28LV256 D.C. OPERATING CHARACTERISTICS VCC = 3.0V to 3.6V, unless otherwise specified Limits Symbol ICC ISBC(2) ILI ILO VIH(2) VIL VOH VOL VWI Parameter VCC Current (Operating, TTL) VCC Current (Standby, CMOS) Input Leakage Current Output Leakage Current High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Write Inhibit Voltage 2 –1 –5 2 –0.3 2 0.3 Min. Typ. Max. 15 150 1 5 VCC +0.3 0.6 Units mA µA µA µA V V V V V IOH = –100µA IOL = 1.0mA Test Conditions CE = OE = VIL, f = 1/tRC min, All I/O’s Open CE = VIHC, All I/O’s Open VIN = GND to VCC VOUT = GND to VCC, CE = VIH A.C. CHARACTERISTICS, Read Cycle VCC = 3.0V to 3.6V, unless otherwise specified 28LV256-20 Symbol tRC tCE tAA tOE tLZ(1) tOLZ(1) tHZ(1)(3) tOHZ(1)(3) tOH(1) Parameter Read Cycle Time CE Access Time Address Access Time OE Access Time CE Low to Active Output OE Low to Active Output CE High to High-Z Output OE High to High-Z Output Output Hold from Address Change 0 0 0 50 50 0 Min. 200 200 200 80 0 0 55 55 0 Max. 28LV256-25 Min. 250 250 250 100 0 0 60 60 Max. 28LV256-30 Min. 300 300 300 110 Max. Units ns ns ns ns ns ns ns ns ns Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) VIHC = VCC –0.3V to VCC +0.3V. (3) Output floating (High-Z) is defined as the state when the external data line is no longer driven by the output buffer. Doc. No. 1071, Rev. B 4 CAT28LV256 Figure 1. A.C. Testing Input/Output Waveform(2) VCC - 0.3V INPUT PULSE LEVELS 0.0 V 0.6 V 28LV256 F04 2.0 V REFERENCE POINTS Figure 2. A.C. Testing Load Circuit (example) Vcc 1.8K DEVICE UNDER TEST 1.3K OUTPUT CL = 100 pF CL INCLUDES JIG CAPACITANCE 28LV256 F05 A.C. CHARACTERISTICS, Write Cycle VCC = 3.0V to 3.6V, unless otherwise specified 28LV256-20 Symbol tWC tAS tAH tCS tCH tCW(3) tOES tOEH tWP(3) tDS tDH tINIT(1) tBLC(1)(4) Parameter Write Cycle Time Address Setup Time Address Hold Time CE Setup Time CE Hold Time CE Pulse Time OE Setup Time OE Hold Time WE Pulse Width Data Setup Time Data Hold Time Write Inhibit Period After Power-up Byte Load Cycle Time 0 100 0 0 150 0 0 150 50 0 5 0.15 10 100 Min. Max. 10 28LV256-25 Min. Max. 10 0 100 0 0 150 0 0 150 50 0 5 0.15 10 100 28LV256-30 Min. Max. Units 10 0 100 0 0 150 0 0 150 50 0 5 0.15 10 100 ms ns ns ns ns ns ns ns ns ns ns ms µs Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) Input rise and fall times (10% and 90%) < 10 ns. (3) A write pulse of less than 20ns duration will not initiate a write cycle. (4) A timer of duration tBLC max. begins with every LOW to HIGH transition of WE. If allowed to time out, a page or byte write will begin; however a transition from HIGH to LOW within tBLC max. stops the timer. 5 Doc. No. 1071, Rev. B CAT28LV256 DEVICE OPERATION Read Data stored in the CAT28LV256 is transferred to the data bus when WE is held high, and both OE and CE are held low. The data bus is set to a high impedance state when either CE or OE goes high. This 2-line control architecture can be used to eliminate bus contention in a system environment. Byte Write A write cycle is executed when both CE and WE are low, and OE is high. Write cycles can be initiated using either WE or CE, with the address input being latched on the falling edge of WE or CE, whichever occurs last. Data, conversely, is latched on the rising edge of WE or CE, whichever occurs first. Once initiated, a byte write cycle automatically erases the addressed byte and the new data is written within 10 ms. Figure 3. Read Cycle tRC ADDRESS tCE CE tOE OE VIH WE tLZ tOLZ DATA OUT HIGH-Z tOH DATA VALID tAA 28LV256 F06 tOHZ tHZ DATA VALID Figure 4. Byte Write Cycle [WE Controlled] ADDRESS tAS tCS CE tAH tCH tWC OE tOES WE tBLC DATA OUT HIGH-Z tWP tOEH DATA IN DATA VALID tDS tDH 28LV256 F07 Doc. No. 1071, Rev. B 6 CAT28LV256 Page Write The page write mode of the CAT28LV256 (essentially an extended BYTE WRITE mode) allows from 1 to 64 bytes of data to be programmed within a single E2PROM write cycle. This effectively reduces the byte-write time by a factor of 64. Following an initial WRITE operation (WE pulsed low, for tWP, and then high) the page write mode can begin by issuing sequential WE pulses, which load the address and data bytes into a 64 byte temporary buffer. The page address where data is to be written, specified by bits A6 to A14, is latched on the last falling edge of WE. Each byte within the page is defined by address bits A0 to A5 Figure 5. Byte Write Cycle [CE Controlled] ADDRESS tAS tAH tCW CE tOEH OE tCS WE HIGH-Z DATA OUT tOES tCH tBLC (which can be loaded in any order) during the first and subsequent write cycles. Each successive byte load cycle must begin within tBLC MAX of the rising edge of the preceding WE pulse. There is no page write window limitation as long as WE is pulsed low within tBLC MAX. Upon completion of the page write sequence, WE must stay high a minimum of tBLC MAX for the internal automatic program cycle to commence. This programming cycle consists of an erase cycle, which erases any data that existed in each addressed cell, and a write cycle, which writes new data back into the cell. A page write will only write data to the locations that were addressed and will not rewrite the entire page. tWC DATA IN DATA VALID tDS tDH 28LV256 F08 Figure 6. Page Mode Write Cycle OE CE t WP WE t BLC ADDRESS t WC I/O BYTE 0 BYTE 1 BYTE 2 BYTE n BYTE n+1 LAST BYTE BYTE n+2 28LV256 F09 7 Doc. No. 1071, Rev. B CAT28LV256 DATA Polling DATA polling is provided to indicate the completion of write cycle. Once a byte write or page write cycle is initiated, attempting to read the last byte written will output the complement of that data on I/O7 (I/O0–I/O6 are indeterminate) until the programming cycle is complete. Upon completion of the self-timed write cycle, all I/O’s will output true data during a read cycle. Figure 7. DATA Polling ADDRESS Toggle Bit In addition to the DATA Polling feature, the device can determine the completion of a write cycle, while a write cycle is in progress, by reading data from the device. This results in I/O6 toggling between one and zero. Once the write is complete, however, I/O6 stops toggling and valid data can be read from the device. CE WE tOEH OE tWC I/O7 DIN = X DOUT = X DOUT = X 28LV256 F10 tOE tOES Figure 8. Toggle Bit WE CE tOEH OE tOE tOES I/O6 (1) tWC (1) 28LV256 F11 Note: (1) Beginning and ending state of I/O6 is indeterminate. Doc. No. 1071, Rev. B 8 CAT28LV256 HARDWARE DATA PROTECTION The following hardware data protection features are incorporated into the CAT28LV256. (1) VCC sense provides write protection when VCC falls below 2.0V min. (2) A power on delay mechanism, tINIT (see AC characteristics), provides a 5 to 10 ms delay before a write sequence, after VCC has reached 2.4V min. (3) Write inhibit is activated by holding any one of OE low, CE high, or WE high. Figure 9. Write Sequence for Activating Software Data Protection WRITE DATA: ADDRESS: AA 5555 (4) Noise pulses of less than 20 ns on the WE or CE inputs will not result in a write cycle. SOFTWARE DATA PROTECTION The CAT28LV256 features a software controlled data protection scheme which, once enabled, requires a data algorithm to be issued to the device before a write can be performed. The device is shipped from Catalyst with the software protection NOT ENABLED (the CAT28LV256 is in the standard operating mode). Figure 10. Write Sequence for Deactivating Software Data Protection WRITE DATA: ADDRESS: AA 5555 WRITE DATA: ADDRESS: 55 2AAA WRITE DATA: ADDRESS: 55 2AAA WRITE DATA: ADDRESS: A0 5555 WRITE DATA: ADDRESS: 80 5555 SOFTWARE DATA (1) PROTECTION ACTIVATED WRITE DATA: ADDRESS: AA 5555 WRITE DATA: XX WRITE DATA: ADDRESS: 55 2AAA TO ANY ADDRESS WRITE LAST BYTE TO LAST ADDRESS 28LV256 F12 WRITE DATA: ADDRESS: 20 5555 28LV256 F13 Note: (1) Write protection is activated at this point whether or not any more writes are completed. Writing to addresses must occur within tBLC Max., after SDP activation. 9 Doc. No. 1071, Rev. B CAT28LV256 To activate the software data protection, the device must be sent three write commands to specific addresses with specific data (Figure 9). This sequence of commands (along with subsequent writes) must adhere to the page write timing specifications (Figure 11). Once this is done, all subsequent byte or page writes to the device must be preceded by this same set of write commands. The data protection mechanism is activated until a deactivate sequence is issued, regardless of power on/off transitions. This gives the user added inadvertent write protection on power-up in addition to the hardware protection provided. To allow the user the ability to program the device with an E2PROM programmer (or for testing purposes) there is a software command sequence for deactivating the data protection. The six step algorithm (Figure 10) will reset the internal protection circuitry, and the device will return to standard operating mode (Figure 12 provides reset timing). After the sixth byte of this reset sequence has been issued, standard byte or page writing can commence. Figure 11. Software Data Protection Timing DATA ADDRESS CE tWP WE tBLC AA 5555 55 2AAA A0 5555 BYTE OR PAGE WRITES ENABLED tWC Figure 12. Resetting Software Data Protection Timing DATA ADDRESS CE DEVICE UNPROTECTED WE AA 5555 55 2AAA 80 5555 AA 5555 55 2AAA 20 5555 tWC SDP RESET Doc. No. 1071, Rev. B 10 CAT28LV256 ORDERING INFORMATION Prefix CAT Device # 28LV256 Suffix N I -25 T Optional Company ID Product Number Package P: PDIP N: PLCC T13: TSOP (8mmx13.4mm) L: PDIP (Lead free, Halogen free) G: PLCC (Lead free, Halogen free) H13: TSOP (Lead free, Halogen free) Speed 20: 200ns* 25: 250ns 30: 300ns Tape & Reel T: 500/Reel Temperature Range Blank = Commercial (0˚C to +70˚C) I = Industrial (-40˚C to +85˚C) A = Automotive (-40˚ to +105˚C) E = Extended (-40˚C to +125˚C) * Commercial and industrial temperature range only. Notes: (1) The device used in the above example is a CAT28LV256NI-25T (100,000 Cycle Endurance, PLCC, Industrial temperature, 250 ns Access Time, Tape & Reel). 11 Doc. No. 1071, Rev. B REVISION HISTORY Date 2/3/2004 Rev. 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Corporate Headquarters 1250 Borregas Avenue Sunnyvale, CA 94089 Phone: 408.542.1000 Fax: 408.542.1200 www.catalyst-semiconductor.com Publication #: Revison: Issue date: Type: 1071 B 2/27/04 Final