CAT28LV65PI-25T

CAT28LV65 64K-Bit CMOS PARALLEL EEPROM FEATURES s 3.0V to 3.6V supply s Read access times: s CMOS and TTL compatible I/O s Automatic page write operation: H GEN FR ALO EE LE A D F R E ETM – 150/200/250ns s Low power CMOS dissipation: – 1 to 32 bytes in 5ms – Page load timer s End of write detection: – Active: 8 mA max. – Standby: 100 µA max. s Simple write operation: – On-chip address and data latches – Self-timed write cycle with auto-clear s Fast write cycle time: – Toggle bit – DATA polling DATA – RDY/BUSY s Hardware and software write protection s 100,000 program/erase cycles s 100 year data retention – 5ms max. s Commercial, industrial and automotive temperature ranges DESCRIPTION The CAT28LV65 is a low voltage, low power, CMOS parallel EEPROM organized as 8K x 8-bits. It requires a simple interface for in-system programming. On-chip address and data latches, self-timed write cycle with auto-clear and VCC power up/down write protection eliminate additional timing and protection hardware. DATA Polling, RDY/BUSY and Toggle status bit signal the start and end of the self-timed write cycle. Additionally, the CAT28LV65 features hardware and software write protection. The CAT28LV65 is manufactured using Catalyst’s advanced CMOS floating gate technology. It is designed to endure 100,000 program/erase cycles and has a data retention of 100 years. The device is available in JEDEC approved 28-pin DIP, 28-pin TSOP, 28-pin SOIC or 32pin PLCC packages. BLOCK DIAGRAM A5–A12 ADDR. BUFFER & LATCHES INADVERTENT WRITE PROTECTION ROW DECODER 8,192 x 8 E2PROM ARRAY 32 BYTE PAGE REGISTER VCC HIGH VOLTAGE GENERATOR CE OE WE CONTROL LOGIC I/O BUFFERS TIMER DATA POLLING, RDY/BUSY & TOGGLE BIT COLUMN DECODER I/O0–I/O7 A0–A4 RDY/BUSY ADDR. BUFFER & LATCHES © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 1 Doc. No. 1024, Rev. D CAT28LV65 PIN CONFIGURATION DIP Package (P, L) RDY/BUSY A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE NC A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 SOIC Package (J, W) (K, X) RDY/BUSY A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE NC A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 PLCC Package (N, G) A7 A12 RDY/BUSY NC VCC WE NC TSOP Top View (8mm x 13.4mm) (T13, H13) OE A11 A9 A8 NC WE Vcc RDY/BUSY A12 A7 A6 A5 A4 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A10 CE I/07 I/06 I/05 I/04 I/03 GND I/O2 I/O1 I/O0 A0 A1 A2 4 3 2 1 32 31 30 A6 A5 A4 A3 A2 A1 A0 NC I/O0 5 6 7 8 9 10 29 28 27 26 25 24 A8 A9 A11 NC OE A10 CE I/O7 I/O6 TOP VIEW 11 23 12 22 13 21 14 15 16 17 18 19 20 I/O1 I/O2 VSS NC I/O3 I/O4 I/O5 PIN FUNCTIONS Pin Name A0–A12 I/O0–I/O7 CE OE RDY/BSY Function Address Inputs Data Inputs/Outputs Chip Enable Output Enable Ready/Busy Status Pin Name WE VCC VSS NC Function Write Enable 3.0 to 3.6 V Supply Ground No Connect Doc. No. 1024, Rev. D 2 CAT28LV65 ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias ................. –55°C to +125°C Storage Temperature ....................... –65°C to +150°C Voltage on Any Pin with Respect to Ground(2) ........... –2.0V to +VCC + 2.0V VCC with Respect to Ground ............... –2.0V to +7.0V Package Power Dissipation Capability (Ta = 25°C) ................................... 1.0W Lead Soldering Temperature (10 secs) ............ 300°C Output Short Circuit Current(3) ........................ 100 mA *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. RELIABILITY CHARACTERISTICS Symbol NEND (1) Parameter Endurance Data Retention ESD Susceptibility Latch-Up Min. 105 100 2000 100 Max. Units Cycles/Byte Years Volts mA Test Method MIL-STD-883, Test Method 1033 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 3015 JEDEC Standard 17 TDR(1) VZAP(1) ILTH(1)(4) MODE SELECTION Mode Read Byte Write (WE Controlled) Byte Write (CE Controlled) Standby, and Write Inhibit Read and Write Inhibit H X CE L L L X H WE H OE L H H X H I/O DOUT DIN DIN High-Z High-Z Power ACTIVE ACTIVE ACTIVE STANDBY ACTIVE CAPACITANCE TA = 25°C, f = 1.0 MHz Symbol CI/O (1) Test Input/Output Capacitance Input Capacitance Max. 10 6 Units pF pF Conditions VI/O = 0V VIN = 0V CIN(1) Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns. (3) Output shorted for no more than one second. No more than one output shorted at a time. (4) Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC +1V. 3 Doc. No. 1024, Rev. D CAT28LV65 D.C. OPERATING CHARACTERISTICS Vcc = 3.0V to 3.6V, unless otherwise specified. Limits Symbol ICC ISBC(3) ILI ILO VIH(3) VIL VOH VOL VWI Parameter VCC Current (Operating, TTL) VCC Current (Standby, CMOS) Input Leakage Current Output Leakage Current High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Write Inhibit Voltage 2 –1 –5 2 –0.3 2 0.3 Min. Typ. Max. 8 100 1 5 VCC +0.3 0.6 Units mA µA µA µA V V V V V IOH = –100µA IOL = 1.0mA Test Conditions CE = OE = VIL, f = 1/tRC min, All I/O’s Open CE = VIHC, All I/O’s Open VIN = GND to VCC VOUT = GND to VCC, CE = VIH A.C. CHARACTERISTICS, Read Cycle Vcc = 3.0V to 3.6V, unless otherwise specified. 28LV65-15 Symbol tRC tCE tAA tOE tLZ(1) tOLZ(1) tHZ(1)(2) tOHZ (1)(2) 28LV65-20 Min. 200 Max. 28LV65-25 Min. 250 Max. Units ns 250 250 100 0 0 ns ns ns ns ns 55 55 0 ns ns ns Parameter Read Cycle Time CE Access Time Address Access Time OEAccess Time CE Low to Active Output OE Low to Active Output CE High to High-Z Output OE High to High-Z Output Output Hold from Address Change Min. 150 Max. 150 150 70 0 0 50 50 0 0 0 0 200 200 80 50 50 tOH(1) Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) Output floating (High-Z) is defined as the state when the external data line is no longer driven by the output buffer. (3) VIHC = VCC –0.3V to VCC +0.3V. Doc. No. 1024, Rev. D 4 CAT28LV65 Figure 1. A.C. Testing Input/Output Waveform(4) VCC - 0.3 V INPUT PULSE LEVELS 0.0 V 0.6 V 2.0 V REFERENCE POINTS Figure 2. A.C. Testing Load Circuit (example) Vcc 1.8 K DEVICE UNDER TEST OUTPUT 1. 3K CL= 100 pF CL INCLUDES JIG CAPACITANCE A.C. CHARACTERISTICS, Write Cycle Vcc = 3.0V to 3.6V, unless otherwise specified. 28LV65-15 Symbol tWC tAS tAH tCS tCH tCW(2) tOES tOEH tWP(2) tDS tDH tINIT(1) tBLC (1)(3) 28LV65-20 Min Max 5 0 100 0 0 150 10 10 150 100 0 28LV65-25 Min Max 5 0 100 0 0 150 10 10 150 100 0 Units ms ns ns ns ns ns ns ns ns ns ns 10 100 220 ms µs ns Parameter Write Cycle Time Address Setup Time0 Address Hold Time CE Setup Time CE Hold Time CE Pulse Time OE Setup Time OE Hold Time WE Pulse Width Data Setup Time Data Hold Time Write Inhibit Period After Power-up Byte Load Cycle Time WE Low to RDY/Busy Low Min Max 5 0 100 0 0 110 0 0 110 60 0 5 0.05 10 100 220 5 0.1 10 100 220 5 0.1 tRB Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) A write pulse of less than 20ns duration will not initiate a write cycle. (3) A timer of duration tBLC max. begins with every LOW to HIGH transition of WE. If allowed to time out, a page or byte write will begin; however a transition from HIGH to LOW within tBLC max. stops the timer. (4) Input rise and fall times (10% and 90%) < 10 ns. 5 Doc. No. 1024, Rev. D CAT28LV65 DEVICE OPERATION Read Data stored in the CAT28LV65 is transferred to the data bus when WE is held high, and both OE and CE are held low. The data bus is set to a high impedance state when either CE or OE goes high. This 2-line control architecture can be used to eliminate bus contention in a system environment. Byte Write A write cycle is executed when both CE and WE are low, and OE is high. Write cycles can be initiated using either WE or CE, with the address input being latched on the falling edge of WE or CE, whichever occurs last. Data, conversely, is latched on the rising edge of WE or CE, whichever occurs first. Once initiated, a byte write cycle automatically erases the addressed byte and the new data is written within 5 ms. Figure 3. Read Cycle ADDRESS tRC tCE CE tOE OE VIH WE tLZ tOLZ DATA OUT HIGH-Z tOH DATA VALID tAA tOHZ tHZ DATA VALID Figure 4. Byte Write Cycle [WE Controlled] ADDRESS tAS tCS CE tAH tCH tWC OE tOES WE tRB RDY/BUSY HIGH-Z tBLC HIGH-Z tWP tOEH DATA OUT HIGH-Z DATA IN DATA VALID tDS tDH Doc. No. 1024, Rev. D 6 CAT28LV65 Page Write The page write mode of the CAT28LV65 (essentially an extended BYTE WRITE mode) allows from 1 to 32 bytes of data to be programmed within a single EEPROM write cycle. This effectively reduces the byte-write time by a factor of 32. Following an initial WRITE operation (WE pulsed low, for tWP, and then high) the page write mode can begin by issuing sequential WE pulses, which load the address and data bytes into a 32 byte temporary buffer. The page address where data is to be written, specified by bits A5 to A12, is latched on the last falling edge of WE. Each byte within the page is defined by address bits A0 to A4 Figure 5. Byte Write Cycle [CE Controlled] tWC ADDRESS tAS tAH tCW CE tOEH OE tCS WE tRB RDY/BUSY HIGH-Z HIGH-Z tOES tCH tBLC (which can be loaded in any order) during the first and subsequent write cycles. Each successive byte load cycle must begin within tBLC MAX of the rising edge of the preceding WE pulse. There is no page write window limitation as long as WE is pulsed low within tBLC MAX. Upon completion of the page write sequence, WE must stay high a minimum of tBLC MAX for the internal automatic program cycle to commence. This programming cycle consists of an erase cycle, which erases any data that existed in each addressed cell, and a write cycle, which writes new data back into the cell. A page write will only write data to the locations that were addressed and will not rewrite the entire page. DATA OUT HIGH-Z DATA IN DATA VALID tDS tDH Figure 6. Page Mode Write Cycle OE CE t WP WE t BLC ADDRESS t WC I/O BYTE 0 BYTE 1 BYTE 2 BYTE n BYTE n+1 LAST BYTE BYTE n+2 Doc. No. 1024, Rev. D 7 CAT28LV65 DATA Polling DATA polling is provided to indicate the completion of write cycle. Once a byte write or page write cycle is initiated, attempting to read the last byte written will output the complement of that data on I/O7 (I/O0–I/O6 are indeterminate) until the programming cycle is complete. Upon completion of the self-timed write cycle, all I/O’s will output true data during a read cycle. Toggle Bit In addition to the DATA Polling feature, the device offers an additional method for determining the completion of a write cycle. While a write cycle is in progress, reading data from the device will result in I/O6 toggling between one and zero. However, once the write is complete, I/O6 stops toggling and valid data can be read from the device. Ready/BUSY (RDY/BUSY) The RDY/BUSY pin is an open drain output which indicates device status during programming. It is pulled low during the write cycle and released at the end of programming. Several devices may be OR-tied to the same RDY/BUSY line. Figure 7. DATA Polling ADDRESS CE WE tOEH OE tWC I/O7 DIN = X DOUT = X DOUT = X 28LV65 F11 tOE tOES Figure 8. Toggle Bit WE CE tOEH OE tOE tOES I/O6 (1) tWC (1) Note: (1) Beginning and ending state of I/O6 is indeterminate. Doc. No. 1024, Rev. D 8 CAT28LV65 HARDWARE DATA PROTECTION The following is a list of hardware data protection features that are incorporated into the CAT28LV65. (1) VCC sense provides for write protection when VCC falls below 2.0V min. (2) A power on delay mechanism, tINIT (see AC characteristics), provides a 5 to 10 ms delay before a write sequence, after VCC has reached 2.40V min. (3) Write inhibit is activated by holding any one of OE low, CE high or WE high. (4) Noise pulses of less than 20 ns on the WE or CE inputs will not result in a write cycle. SOFTWARE DATA PROTECTION The CAT28LV65 features a software controlled data protection scheme which, once enabled, requires a data algorithm to be issued to the device before a write can be performed. The device is shipped from Catalyst with the software protection NOT ENABLED (the CAT28LV65 is in the standard operating mode). Figure 9. Write Sequence for Activating Software Data Protection WRITE DATA: ADDRESS: AA 1555 Figure 10. Write Sequence for Deactivating Software Data Protection WRITE DATA: ADDRESS: AA 1555 WRITE DATA: ADDRESS: 55 0AAA WRITE DATA: ADDRESS: 55 0AAA WRITE DATA: ADDRESS: A0 1555 WRITE DATA: ADDRESS: 80 1555 (1) SOFTWARE DATA (12) PROTECTION ACTIVATED WRITE DATA: ADDRESS: AA 1555 WRITE DATA: XX WRITE DATA: ADDRESS: 55 0AAA TO ANY ADDRESS WRITE LAST BYTE TO LAST ADDRESS WRITE DATA: ADDRESS: 20 1555 Note: (1) Write protection is activated at this point whether or not any more writes are completed. Writing to addresses must occur within tBLC Max., after SDP activation. 9 Doc. No. 1024, Rev. D CAT28LV65 To activate the software data protection, the device must be sent three write commands to specific addresses with specific data (Figure 9). This sequence of commands (along with subsequent writes) must adhere to the page write timing specifications (Figure 11). Once this is done, all subsequent byte or page writes to the device must be preceded by this same set of write commands. The data protection mechanism is activated until a deactivate sequence is issued regardless of power on/off transitions. This gives the user added inadvertent write protection on power-up in addition to the hardware protection provided. Figure 11. Software Data Protection Timing DATA ADDRESS CE AA 1555 55 0AAA To allow the user the ability to program the device with an EEPROM programmer (or for testing purposes) there is a software command sequence for deactivating the data protection. The six step algorithm (Figure 10) will reset the internal protection circuitry, and the device will return to standard operating mode (Figure 12 provides reset timing). After the sixth byte of this reset sequence has been issued, standard byte or page writing can commence. A0 1555 BYTE OR PAGE WRITES ENABLED tWC tWP WE tBLC Figure 12. Resetting Software Data Protection Timing DATA ADDRESS CE DEVICE UNPROTECTED WE AA 1555 55 0AAA 80 1555 AA 1555 55 0AAA 20 1555 tWC SDP RESET Doc. No. 1024, Rev. D 10 CAT28LV65 ORDERING INFORMATION Prefix CAT Device # 28LV65 Suffix N I -25 T Optional Company ID Product Number Temperature Range Blank = Commercial (0˚C to +70˚C) I = Industrial (-40˚C to +85˚C) A = Automotive (-40˚ to +105˚C)* Speed 15: 150ns 20: 200ns 25: 250ns Tape & Reel Package P: PDIP J: SOIC (JEDEC) K: SOIC (EIAJ) N: PLCC T13: TSOP (8mmx13.4mm) L: PDIP (Lead free, Halogen free) W: SOIC (JEDEC) (Lead free, Halogen free) X: SOIC (EIAJ) (Lead free, Halogen free) G: PLCC (Lead free, Halogen free) H13: TSOP (8mmx13.4mm) (Lead free, Halogen free) * -40˚C to +125˚C is available upon request Notes: (1) The device used in the above example is a CAT28LV65NI-25T (PLCC, Industrial temperature, 250 ns Access Time, Tape & Reel). 11 Doc. No. 1024, Rev. D REVISION HISTORY Date 03/29/04 04/20/04 Revision Comments B C Added Green packages in all areas Delete data sheet designation Update Ordering Information Update Revision History Update Rev Number 03/29/05 D Update A.C Characteristics, Write Cycle Copyrights, Trademarks and Patents Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: DPP ™ AE2 ™ Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000. CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES. Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur. Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete. Catalyst Semiconductor, Inc. Corporate Headquarters 1250 Borregas Avenue Sunnyvale, CA 94089 Phone: 408.542.1000 Fax: 408.542.1200 www.catalyst-semiconductor.com Publication #: Revison: Issue date: 1024 D 03/29/05