CAT525LI

CAT525 Quad Digitally Programmable Potentiometer (DPP™) with 256 Taps and Microwire Interface FEATURES Four 8-bit DPPs configured as programmable voltage sources in DAC-like applications Independent reference inputs Buffered wiper outputs Non-volatile NVRAM memory wiper storage Output voltage range includes both supply rails 4 independently addressable buffered output wipers 1 LSB accuracy, high resolution Serial Microwire-like interface Single supply operation: 2.7V - 5.5V Setting read-back without effecting outputs For Ordering Information details, see page 15. DESCRIPTION The CAT525 is a quad 8-bit digitally programmable potentiometer (DPP™) configured for programmable voltage and DAC-like applications. Intended for final calibration of products such as camcorders, fax machines and cellular telephones on automated high volume production lines and systems capable of self calibration, it is also well suited for applications were equipment requiring periodic adjustment is either difficult to access or located in a hazardous environment. The CAT525 offers four independently programmable DPPs each having its own reference inputs and each capable of rail to rail output swing. The wipers are buffered by rail to rail op amps. Wiper settings, stored in non-volatile NVRAM memory, are not lost when the device is powered down and are automatically reinstated when power is returned. Each wiper can be dithered to test new output values without effecting the stored settings and stored settings can be read back without disturbing the DPP’s output. Control of the CAT525 is accomplished with a simple 3wire, Microwire-like serial interface. A Chip Select pin allows several CAT525's to share a common serial interface and communications back to the host controller is via a single serial data line thanks to the ¯¯¯¯ CAT525’s Tri-Stated Data Output pin. A RDY/BSY output working in concert with an internal low voltage detector signals proper operation of non-volatile NVRAM Memory Erase/ Write cycle. The CAT525 is available in the 0°C to 70°C com– mercial and -40°C to 85°C industrial operating temperature ranges and offered in 20-pin plastic DIP and surface mount packages. APPLICATIONS Automated product calibration Remote control adjustment of equipment Offset, gain and zero adjustments in selfcalibrating and adaptive control systems Tamper-proof calibrations DAC (with memory) substitute PIN CONFIGURATION PDIP 20-Lead (L) SOIC 20-Lead (W) VREFH2 VREFH1 VDD CLK RDY/¯¯¯¯ BSY CS DI DO PROG GND 1 2 3 4 5 6 7 8 9 10 CAT525 20 19 18 17 16 15 14 13 12 11 VREFH3 VREFH4 VOUT1 VOUT2 VOUT3 VOUT4 VREFL4 VREFL3 VREFL2 VREFL1 © Catalyst Semiconductor, Inc. Characteristics subject to change without notice 1 Doc. No. MD-2001 Rev. H CAT525 FUNCTIONAL DIAGRAM VREFH1 VREFH3 VREFH2 VREFH4 2 RDY/BSY 5 1 20 19 + PROG PROGRAM CONTROL 18 WIPER CONTROL REGISTERS AND NVRAM 9 VOUT1 – + – + – + 24kΩ (ea) 15 16 17 VOUT2 CLK CS DI DATA CONTROLLER 4 6 7 VOUT3 VOUT4 – H.V. CHARGE PUMP SERIAL DATA OUTPUT REGISTER 8 DO 11 12 13 14 VREFL2 VREFL4 VREFL1 VREFL3 Doc. No. MD-2001 Rev. H 2 © Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT525 ABSOLUTE MAXIMUM RATINGS Parameters Supply Voltage* VDD to GND Inputs CLK to GND CS to GND DI to GND ¯¯¯¯ RDY/BSY to GND PROG to GND VREFH to GND VREFL to GND Ratings -0.5 to +7 -0.5 to VDD +0.5 -0.5 to VDD +0.5 -0.5 to VDD +0.5 -0.5 to VDD +0.5 -0.5 to VDD +0.5 -0.5 to VDD +0.5 -0.5 to VDD +0.5 Units V Parameters Outputs D0 to GND VOUT 1– 4 to GND Operating Ambient Temperature Commercial (‘C’ or Blank suffix) Industrial (‘I’ suffix) Junction Temperature Storage Temperature Lead Soldering (10 sec max) Ratings -0.5 to VDD +0.5 -0.5 to VDD +0.5 0 to +70 -40 to +85 +150 -65 to +150 +300 Units V V °C °C °C °C °C V V V V V V V RELIABILITY CHARACTERISTICS Symbol VZAP(2) ILTH(2)(3) Parameter ESD Susceptibility Latch-Up Test Method MIL-STD-883, Test Method 3015 JEDEC Standard 17 Min 2000 100 Max Units V mA POWER SUPPLY Symbol IDD1 IDD2 VDD Parameter Supply Current (Read) Supply Current (Write) Operating Voltage Range Conditions Normal Operating Programming, VDD = 5V VDD = 3V Min — — — 2.7 Typ 400 1600 1000 — Max 600 2500 1600 5.5 Units µA µA µA V LOGIC INPUTS Symbol IIH IIL VIH VIL Parameter Input Leakage Current Input Leakage Current High Level Input Voltage Low Level Input Voltage Conditions VIN = VDD VIN = 0V Min — — 2 0 Typ — — — — Max 10 -10 VDD 0.8 Units µA µA V V LOGIC OUTPUTS Symbol VOH VOL Parameter High Level Output Voltage Low Level Output Voltage Conditions IOH = -40µA IOL = 1 mA, VDD = +5V IOL = 0.4 mA, VDD = +3V Min VDD -0.3 — — Typ — — — Max — 0.4 0.4 Units V V V Notes: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. (2) This parameter is tested initially and after a design or process change that affects the parameter. (3) Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC + 1V. © Catalyst Semiconductor, Inc. Characteristics subject to change without notice 3 Doc. No. MD-2001 Rev. H CAT525 POTENTIOMETER CHARACTERISTICS VDD = +2.7V to +5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified Symbol RPOT Parameter Potentiometer Resistance RPOT to RPOT Match Pot Resistance Tolerance Voltage on VREFH pin Voltage on VREFL pin Resolution INL DNL ROUT IOUT TCRPOT CH/CL Integral Linearity Error Differential Linearity Error Buffer Output Resistance Buffer Output Current TC of Pot Resistance Potentiometer Capacitances 300 8/8 2.7 0 0.4 0.5 0.25 1 0.5 10 3 — Conditions Min Typ 24 ±0.5 ±1 ±20 VDD VDD - 2.7 Max Units kΩ % % V V % LSB LSB Ω mA ppm/ºC pF AC ELECTRICAL CHARACTERISTICS VDD = +2.7V to +5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified Symbol Digital tCSMIN tCSS tCSH tDIS tDIH tDO1 tDO0 tHZ tLZ tBUSY tPS tPROG tCLKH tCLKL fC Analog tDS DPP Settling Time to 1 LSB CLOAD = 10 pF, VDD = +5V CLOAD = 10 pF, VDD = +3V — — 3 6 10 10 µs µs Minimum CS Low Time CS Setup Time CS Hold Time DI Setup Time DI Hold Time Output Delay to 1 Output Delay to 0 Output Delay to High-Z Output Delay to Low-Z Erase/Write Cycle Time PROG Setup Time Minimum Pulse Width Minimum CLK High Time Minimum CLK Low Time Clock Frequency CL = 100pF (1) Parameter Conditions Min 150 100 0 50 50 — — — — — 150 700 500 300 DC Typ — — — — — — — 400 400 4 — — — — — Max — — — — — 150 150 — — 5 — — — — 1 Units ns ns ns ns ns ns ns ns ns ms ns ns ns ns MHz Notes: (1) All timing measurements are defined at the point of signal crossing VDD / 2. (2) These parameters are periodically sampled and are not 100% tested. Doc. No. MD-2001 Rev. H 4 © Catalyst Semiconductor, Inc. Characteristics subject to change without notice TIMING MIN/MAX FROM TO to 1 2 3 4 5 PARAM NAME t CLK H t CLK H Rising CLK edge tofalling CLK edge Min CLK t CLK L Falling CLK edge to CLKrising edge t CSH Falling CLK edge f r last data bit (DI) o to falling CS edge Rising CS edge to ne rising CLK edge xt © Catalyst Semiconductor, Inc. Characteristics subject to change without notice A.C. TIMING DIAGRAM Min Min Min t CSS t CSS t CLK L t CSH CS t CSMIN t DIS t CSMIN Falling CS edge torising CS edge Data valid to first rising CLK edge after CS = high Min Min t DIS DI 5 t DIH t DIH t DO0 t LZ Rising CLK edge to end of datavalid Rising CLK edge to D0 = lo w Rising CS edge to D0 becoming high low impedance (activ output) e Min Max (Max) t LZ t DO0 DO t DO1 t HZ t DO1 t HZ Rising CLK edge to D0 = high Falling CS edge to D0 becoming high impedance (T ri-State) Max (Max) PROG t PS t PROG t PS Rising PROG edge to next falling CLK edge Min t PROG Rising PROG edge to falling PROG edge t BUSY Falling CLK edge after PR OG=H to rising RD Y/BSY edge t BUSY Min RDY/BSY Max CAT525 Doc. No. MD-2001 Rev. H to 2 1 3 4 5 CAT525 PIN DESCRIPTION Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Name VREFH2 VREFH1 VDD CLK ¯¯¯¯ RDY/BSY CS DI DO PROG GND VREFL1 VREFL2 VREFL3 VREFL4 VOUT4 VOUT3 VOUT2 VOUT1 VREFH4 VREFH3 Function Maximum DPP 2 output voltage Maximum DPP 1 output voltage Power supply positive Clock input pin Ready/Busy output Chip select Serial data input pin Serial data output pin Non-volatile Memory Programming Enable Input Power supply ground Minimum DPP 1 output voltage Minimum DPP 2 output voltage Minimum DPP 3 output voltage Minimum DPP 4 output voltage DPP 4 output DPP 3 output DPP 2 output DPP 1 output Maximum DPP 4 output voltage Maximum DPP 3 output voltage CDPP/DPP addressing is as follows: DPP OUTPUT VOUT1 VOUT2 VOUT3 VOUT4 A0 0 1 0 1 A1 0 0 1 1 DEVICE OPERATION The CAT525 is a quad 8-bit configured digitally programmable potentiometer (DPP/CDPP) whose outputs can be programmed to any one of 256 individual voltage steps. Once programmed, these output settings are retained in non-volatile memory and will not be lost when power is removed from the chip. Upon power up the DPPs return to the settings stored in non-volatile memory. Each confitured DPP can be written to and read from independently without effecting the output voltage during the read or write cycle. Each output can also be adjusted without altering the stored output setting, which is useful for testing new output settings before storing them in memory. DIGITAL INTERFACE The CAT525 employs a 3 wire serial, Microwire-like control interface consisting of Clock (CLK), Chip Select (CS) and Data In (DI) inputs. For all operations, address and data are shifted in LSB first. In addition, all digital data must be preceded by a logic “1” as a start bit. The DPP address and data are clocked into the DI pin on the clock’s rising edge. Doc. No. MD-2001 Rev. H When sending multiple blocks of information a minimum of two clock cycles is required between the last block sent and the next start bit. Multiple devices may share a common input data line by selectively activating the CS control of the desired IC. Data Outputs (DO) can also share a common line because the DO pin is Tri-Stated and returns to a high impedance when not in use. CHIP SELECT Chip Select (CS) enables and disables the CAT525’s read and write operations. When CS is high data may be read to or from the chip, and the Data Output (DO) pin is active. Data loaded into the DPP wiper control registers will remain in effect until CS goes low. Bringing CS to a logic low returns all DPP outputs to the settings stored in non-volatile memory and switches DO to its high impedance Tri-State mode. Because CS functions like a reset the CS pin has been desensitized with a 30ns to 90ns filter circuit to prevent noise spikes from causing unwanted resets and the loss of volatile data. 6 © Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT525 CLOCK The CAT525’s clock controls both data flow in and out of the IC and non-volatile memory cell programming. Serial data is shifted into the DI pin and out of the DO pin on the clock’s rising edge. While it is not necessary for the clock to be running between data transfers, the clock must be operating in order to write to non-volatile memory, even though the data being saved may already be resident in the DPP wiper control register. No clock is necessary upon system power-up. The CAT525’s internal power-on reset circuitry loads data from non-volatile memory to the DPPs without using the external clock. As data transfers are edge triggered clean clock transitions are necessary to avoid falsely clocking data into the control registers. Standard CMOS and TTL logic families work well in this regard and it is recommended that any mechanical switches used for breadboarding or device evaluation purposes be debounced by a flip-flop or other suitable debouncing circuit. VREF VREF, the voltage applied between pins VREFH & VREFL, sets the configured DPP’s Zero to Full Scale output range where VREFL = Zero and VREFH = Full Scale. VREF can span the full power supply range or just a fraction of it. In typical applications VREFH & VREFL are connected across the power supply rails. When using less than the full supply voltage be mindfull of the limits placed on VREFH and VREFL as specified in the References section of DC Electrical Characteristics. ¯¯¯¯¯ READY/BUSY When saving data to non-volatile memory, the ¯¯¯¯ Ready/Busy ouput (RDY/BSY ) signals the start and duration of the erase/write cycle. Upon receiving a ¯¯¯¯ command to store data (PROG goes high) RDY/BSY goes low and remains low until the programming cycle is complete. During this time the CAT525 will ignore any data appearing at DI and no data will be output on DO. ¯¯¯¯ RDY/BSY is internally ANDed with a low voltage detector circuit monitoring VDD. If VDD is below the minimum value required for EEPROM programming, ¯¯¯¯ RDY/BSY will remain high following the program command indicating a failure to record the desired data in non-volatile memory. DATA OUTPUT Data is output serially by the CAT525, LSB first, via the Data Out (DO) pin following the reception of a start bit and two address bits by the Data Input (DI). DO becomes active whenever CS goes high and resumes its high impedance Tri-State mode when CS returns low. Tri-Stating the DO pin allows several 525s to share a single serial data line and simplifies interfacing multiple 525s to a microprocessor. WRITING TO MEMORY Programming the CAT525’s non-volatile memory is accomplished through the control signals: Chip Select (CS) and Program (PROG). With CS high, a start bit followed by a two bit DPP address and eight data bits are clocked into the DPP wiper control register via the DI pin. Data enters on the clock’s rising edge. The DPP output changes to its new setting on the clock cycle following D7, the last data bit. Programming is accomplished by bringing PROG high sometime after the start bit and at least 150 ns prior to the falling edge of the clock cycle immediately Figure 1. Writing to Memory to 1 2 3 4 5 6 7 8 9 10 11 12 N N+1 N+2 CS NEW DPP DATA DI 1 A0 A1 D0 D1 D2 D3 D4 D5 D6 D7 CURRENT DPP DATA DO D0 D1 D2 D3 D4 D5 D6 D7 PROG RDY/BSY DPP OUTPUT CURRENT DPP VALUE NON-VOL ATILE NEW DPP VALUE VOLATILE NEW DPP VALUE NON-VOL ATILE © Catalyst Semiconductor, Inc. Characteristics subject to change without notice 7 Doc. No. MD-2001 Rev. H CAT525 following the D7 bit. Two clock cycles after the D7 bit the DPP control register will be ready to receive the next set of address and data bits. The clock must be kept running throughout the programming cycle. Internal control circuitry takes care of generating and ramping up the programming voltage for data transfer to the non-volatile memory cells. The CAT525’s nonvolatile memory cells will endure over 100,000 write cycles and will retain data for a minimum of 20 years without being refreshed. READING DATA Each time data is transferred into a DPP wiper control register currently held data is shifted out via the D0 pin, thus in every data transaction a read cycle occurs. Note, however, that the reading process is destructive. Data must be removed from the register in order to be read. Figure 2 depicts a Read Only cycle in which no change occurs in the DPP’s output. This feature allows µPs to poll DPPs for their current setting without disturbing the output voltage but it assumes that the setting being read is also stored in non-volatile memory so that it can be restored at the end of the read cycle. In Figure 2 CS returns low th before the 13 clock cycle completes. In doing so the non-volatile memory setting is reloaded into the DPP wiper control register. Since this value is the same as that which had been there previously no change in the DPP’s output is noticed. Had the value held in the control register been different from that stored in nonvolatile memory then a change would occur at the read cycle’s conclusion. TEMPORARILY CHANGE OUTPUT The CAT525 allows temporary changes in DPP’s output to be made without disturbing the settings retained in non-volatile memory. This feature is particularly useful when testing for a new output setting and allows for user adjustment of preset or default values without losing the original factory settings. Figure 3 shows the control and data signals needed to effect a temporary output change. DPP settings may be changed as many times as required and can be made to any of the four DPPs in any order or sequence. The temporary setting(s) remain in effect long as CS remains high. When CS returns low all four DPPs will return to the output values stored in non-volatile memory. When it is desired to save a new setting acquired using this feature, the new value must be reloaded into the DPP control register prior to programming. This is because the CAT525’s internal control circuitry discards from the programming register the new data two clock cycles after receiving it if no PROG signal is received. Figure 2. Reading from Memory to 1 2 3 4 5 6 7 8 9 10 11 12 Figure 3. Temporary Change in Output to 1 2 3 4 5 6 7 8 9 10 11 12 N N+1 N+2 CS CS NEW DPP DATA 1 A0 A1 D0 D1 D2 D3 D4 D5 D6 D7 DI 1 A0 A1 CURRENT DPP DATA DI CURRENT DPP DATA D6 D7 DO D0 D1 D2 D3 D4 D5 DO D0 D1 D2 D3 D4 D5 D6 D7 PROG PROG RDY/BSY RDY/BSY DPP OUTPUT CURRENT DPP VALUE NON-VOL ATILE DPP OUTPUT CURRENT DPP VALUE NON-VOL ATILE NEW DPP VALUE VOLATILE CURRENT DPP VALUE NON-VOL ATILE Doc. No. MD-2001 Rev. H 8 © Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT525 APPLICATION CIRCUITS +5V VI RI +15V VDD CONTROL & DATA VREFH VDPP RF DPP INPUT DPP OUTPUT VDPP = MSB LSB CODE x (VFS - VZERO + VZERO ) 255 ANALOG OUTPUT VFS = 0.99VREF VREF = 5V RI = RF + – -15V VOUT = OP 07 VOUT 1111 1000 0111 0000 0000 1111 0000 1111 0001 0000 VZERO = 0.01VREF 255 × 0.98VREF + 0.01VREF = 0.990 VREF 255 128 × 0.98VREF + 0.01VREF = 0.502VREF 255 127 × 0.98VREF + 0.01VREF = 0.498 VREF 255 1 × 0.98VREF + 0.01VREF = 0.014 VREF 255 0 × 0.98VREF + 0.01VREF = 0.010 VREF 255 CAT525 GND VREFL VOUT = +4.90V VOUT = +0.02V VOUT = -0 .02V VDPP ( RI + RF ) - VI R F RI VOUT = -4.86V VOUT = -4.90V For R I = RF VOUT = 2VDPP - VI Bipolar DPP Output +5V RI +15V RF GND VREFL R VOUT = (1 + F ) VDPP RI Amplified DPP Output +5V VDD VREF VREFH 127RC +5V VDD FINE ADJUST DPP FINE ADJUST DPP COARSE ADJUST DPP GND RC VOFFSET +V + – COARSE ADJUST DPP GND VREFL RC = VREF 256 x 1µA Fine adjust gives ±1 LSB change in VOFFSET when VOFFSET = VREF/2 Coarse-Fine Offset Control by Averaging DPP Outputs for Single Power Supply Systems Coarse-Fine Offset Control by Averaging DPP Outputs for Dual Power Supply Systems © Catalyst Semiconductor, Inc. Characteristics subject to change without notice 9 + -15V CONTROL & DATA CAT525 VDPP – OP 07 +VREF VREFH VREFL VDD VREFH VOUT 127RC RC = RC R0 = (+VREF) - (VOFFSET+) 1µA (-VREF) + (VOFFSET+) 1µA R0 +V + -VREF VOFFSET – -V Doc. No. MD-2001 Rev. H CAT525 V+ I > 2mA VREF = 5.000V VDD CONTROL & DATA VREFH LT 1029 CAT525 GND VREFL Digitally Trimmed Voltage Reference 28 ÷ 32V 15kΩ 10µF 1N5231B VDD CONTROL & DATA VREFH 5.1V 10kΩ CAT525 GND VREFL + – LM 324 MPT3055EL OUTPUT 1.00kΩ 4.02kΩ 10µF 35V 0 ÷ 25V @ 1A Digitally Controlled Voltage Reference Doc. No. MD-2001 Rev. H 10 © Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT525 +5V 1.0µF VREF VIN + VDD VREFH LM339 10kΩ +5V WINDOW 1 – + – CAT525 VPP CS DI DPP1 + – +5V 10kΩ WINDOW 2 1.0µF +5V VREF VIN + VDD VREFH LM339 10kΩ +5V WINDOW 1 + DO DPP2 PROG – + – – + – +5V 10kΩ WINDOW 3 CS DI VPP CAT525 DPP1 CLK + – DPP3 DPP2 + – 10kΩ +5V WINDOW 2 + – +5V 10kΩ WINDOW 4 PROG DO + DPP3 – + – DPP4 CLK DPP4 + – VREFL 10kΩ +5V WINDOW 3 + – 10kΩ +5V WINDOW 5 GND GND VREFL + – + – VREF WINDOW 1 VOUT1 WINDOW 2 VOUT2 WINDOW 3 VREFH WINDOW 1 VOUT1 VOUT2 VOUT3 WINDOW 4 WINDOW 2 VOUT4 VOUT3 WINDOW 5 VOUT4 WINDOW 3 GND GND WINDOW STRUCTURE WINDOW STRUCTURE Staircase Window Comparator Overlapping Window Comparator © Catalyst Semiconductor, Inc. Characteristics subject to change without notice 11 Doc. No. MD-2001 Rev. H CAT525 +5V 2.2kΩ VDD VREFH 4.7µF LM385-2.5 +15V ISINK = 2 ÷ 255mA DPP1 + +5V – 10kΩ 10kΩ 2N7000 1mA steps CONTROL & DATA CAT525 39Ω 1W 39Ω 1W DPP2 + – 2N7000 5µA steps GND VREFL 5MΩ 5MΩ 3.9kΩ 10kΩ 10kΩ Current Sink with 4 Decades of Resolution +15V 51kΩ + TIP29 – 10kΩ +5V 10kΩ VDD VREFH 5MΩ DPP1 5MΩ 39Ω 1W 39Ω 1W 5MΩ DPP2 GND VREFL LM385-2.5 -15V ISOURCE = 2 ÷ 255mA Current Source with 4 Decades of Resolution Doc. No. MD-2001 Rev. H + CONTROL & DATA CAT525 BS170P 5MΩ 3.9kΩ BS170P 12 + -15V – TIP30 + – 1mA steps – 5µA steps © Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT525 PACKAGE OUTLINE DRAWING PDIP 20-Lead (L) (1)(2) E1 D TOP VIEW E A2 A c L A1 e b1 b eB SIDE VIEW END VIEW SYMBOL MIN NOM MAX A A1 A2 b b1 c D E E1 e eB L 3.56 0.38 2.92 0.36 1.15 0.21 24.89 7.62 6.10 7.88 2.99 3.30 3.30 0.45 1.52 0.26 26.16 7.87 6.35 2.54 TYP 5.33 4.95 0.55 1.77 0.35 26.92 8.25 7.11 10.92 3.81 For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf. Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-001. © Catalyst Semiconductor, Inc. Characteristics subject to change without notice 13 Doc. No. MD-2001 Rev. H CAT525 SOIC 20-Lead 300mils (W) (1)(2) SYMBOL MIN NOM MAX A A1 A2 b E1 E 2.36 0.10 2.05 0.31 0.20 12.60 10.01 7.40 0.25 0.40 0° 5° 2.49 2.64 0.30 2.55 0.41 0.27 12.80 10.30 7.50 1.27 BSC 0.51 0.33 13.00 10.64 7.60 0.75 c D E E1 e h L 0.81 1.27 8° 15° b PIN#1 IDENTIFICATION e θ θ1 TOP VIEW D h h θ1 A A2 θ θ1 A1 SIDE VIEW L END VIEW c For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf. Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-013. Doc. No. MD-2001 Rev. H 14 © Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT525 EXAMPLE OF ORDERING INFORMATION (1) Prefix CAT Optional Company ID Device # Suffix 525 W Package L: PDIP W: SOIC Product Number 525 I Temperature Range I = Industrial (-40ºC to 85ºC) – T1 Tape & Reel T: Tape & Reel 1: 1000/Reel ORDERING PART NUMBER CAT525LI CAT525WI Notes: (1) All packages are RoHS-compliant (Lead-free, Halogen-free). (2) The standard lead finish is Matte-Tin. (3) This device used in the above example is a CAT525WI-T1 (SOIC, Industrial Temperature, Tape & Reel, 1000). © Catalyst Semiconductor, Inc. Characteristics subject to change without notice 15 Doc. No. MD-2001 Rev. H REVISION HISTORY Date 03/16/2004 07/12/2004 07/27/2007 10/31/2007 Rev. D E F G Reason Updated Potentiometer Characteristics Updated Functional Diagram Updated Potentiometer Characteristics Added Package Outline Drawings Updated Example of Ordering Information Added MD- to document number Updated Package Outline Drawings Updated Example of Ordering Information Update document title Update Logic Output table Update A.C. Timing Diagram Update Writing to Memory 12/06/07 H Copyrights, Trademarks and Patents © Catalyst Semiconductor, Inc. Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: Adaptive Analog™, Beyond Memory™, DPP™, EZDim™, LDD™, MiniPot™, Quad-Mode™ and Quantum Charge Programmable™ Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES. Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur. Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete. Catalyst Semiconductor, Inc. Corporate Headquarters 2975 Stender Way Santa Clara, CA 95054 Phone: 408.542.1000 Fax: 408.542.1200 www.catsemi.com Document No: MD-2001 Revision: H Issue date: 11/06/07