CAT5261YI-50TE13

CAT5261 Dual Digitally Programmable Potentiometer (DPP™) with 256 Taps and SPI Interface FEATURES s Two linear-taper digitally programmable H GEN FR ALO EE LE A D F R E ETM s Automatic recall of saved wiper settings at potentiometers s 256 resistor taps per potentiometer s End to end resistance 50kΩ or 100kΩ s Potentiometer control and memory access via power up s 2.5 to 6.0 volt operation s Standby current less than 1µA s 1,000,000 nonvolatile WRITE cycles s 100 year nonvolatile memory data retention s 24-lead SOIC and 24-lead TSSOP s Industrial temperature range SPI interface s Low wiper resistance, typically 100Ω s Nonvolatile memory storage for up to four wiper settings for each potentiometer DESCRIPTION The CAT5261 is two Digitally Programmable Potentiometers (DPPs™) integrated with control logic and 8 bytes of NVRAM memory. Each DPP consists of a series of resistive elements connected between two externally accessible end points. The tap points between each resistive element are connected to the wiper outputs with CMOS switches. A separate 8-bit control register (WCR) independently controls the wiper tap switches for each DPP. Associated with each wiper control register are four 8-bit non-volatile memory data registers (DR) used for storing up to four wiper settings. Writing to the wiper control register or any of the non-volatile data registers is via a SPI serial bus. On power-up, the contents of the first data register (DR0) for each of the potentiometers is automatically loaded into its respective wiper control register. The CAT5261 can be used as a potentiometer or as a two terminal, variable resistor. It is intended for circuit level or system level adjustments in a wide variety of applications. It is available in the -40°C to 85°C industrial operating temperature range and offered in a 24-lead SOIC and TSSOP package. PIN CONFIGURATION SOIC/TSSOP Package (J, W/U, Y) SO A0 NC NC NC NC VCC RL0 RH0 RW0 CS WP 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 CAT 19 5261 18 17 16 15 14 13 HOLD SCK NC NC NC NC GND RW1 RH1 RL1 A1 SI FUNCTIONAL DIAGRAM RH0 RH1 CS SCK SI SO SPI BUS INTERFACE WIPER CONTROL REGISTERS R W0 R W1 WP A0 A1 HOLD CONTROL LOGIC NONVOLATILE DATA REGISTERS RL0 RL1 © 2004 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 1 Document No. 2122, Rev. B CAT5261 PIN DESCRIPTION Pin (SOIC/TSSOP) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 PIN DESCRIPTIONS Function Serial Data Output Device Address, LSB No Connect No Connect No Connect No Connect Supply Voltage Low Reference Terminal for Potentiometer 0 High Reference Terminal for Potentiometer 0 Wiper Terminal for Potentiometer 0 Chip Select Write Protection Serial Input Device Address Low Reference Terminal for Potentiometer 1 High Reference Terminal for Potentiometer 1 Wiper Terminal for Potentiometer 1 Ground No Connect No Connect No Connect No Connect Bus Serial Clock Hold Name SO A0 NC NC NC NC VCC RL0 RH0 RW0 CS WP SI A1 RL1 RH1 RW1 GND NC NC NC NC SCK HOLD SI: Serial Input SI is the serial data input pin. This pin is used to input all opcodes, byte addresses and data to be written to the CAT5261. Input data is latched on the rising edge of the serial clock. SO: Serial Output SO is the serial data output pin. This pin is used to transfer data out of the CAT5261. During a read cycle, data is shifted out on the falling edge of the serial clock. SCK: Serial Clock SCK is the serial clock pin. This pin is used to synchronize the communication between the microcontroller and the CAT5261. Opcodes, byte addresses or data present on the SI pin are latched on the rising edge of the SCK. Data on the SO pin is updated on the falling edge of the SCK. A0, A1: Device Address Inputs These inputs set the device address when addressing multiple devices. A total of four devices can be addressed on a single bus. A match in the slave address must be made with the address input in order to initiate communication with the CAT5261. RH, RL: Resistor End Points The RH and RL pins are equivalent to the terminal connections on a mechanical potentiometer. RW: Wiper The RW pins are equivalent to the wiper terminal of a mechanical potentiometer. CS: Chip Select CS is the Chip select pin. CS low enables the CAT5261 and CS high disables the CAT5261. CS high takes the SO output pin to high impedance and forces the devices into a Standby mode (unless an internal write operation is underway). The CAT5261 draws ZERO current in the Standby mode. A high to low transition on CS is required prior to any sequence being initiated. A low to high transition on CS after a valid write sequence is what initiates an internal write cycle. Write Protect WP: WP is the Write Protect pin. The Write Protect pin will allow normal read/write operations when held high. When WP is tied low, all non-volatile write operations to the Data registers are inhibited (change of wiper control register is allowed). WP going low while CS is still low will interrupt a write to the registers. If the internal write cycle has already been initiated, WP going low will have no effect on any write operation. HOLD: Hold The HOLD pin is used to pause transmission to the CAT5261 while in the middle of a serial sequence without having to retransmit entire sequence at a later time. To pause, HOLD must be brought low while SCK is low. The SO pin is in a high impedance state during the time the part is paused, and transitions on the SI pins will be ignored. To resume communication, HOLD is brought high, while SCK is low. (HOLD should be held high any time this function is not being used.) HOLD may be tied high directly to VCC or tied to VCC through a resistor. Document No. 2122, Rev. B 2 CAT5261 SERIAL BUS PROTOCOL The CAT5261 supports the SPI bus data transmission protocol. The synchronous Serial Peripheral Interface (SPI) helps the CAT5261 to interface directly with many of today's popular microcontrollers. The CAT5261 contains an 8-bit instruction register .The instruction set and the operation codes are detailed in the instruction set table 3 on page 9. After the device is selected with CS going low the first byte will be received. The part is accessed via the SI pin, with data being clocked in on the rising edge of SCK. The first byte contains one of the six op-codes that define the operation to be performed. DEVICE OPERATION The CAT5261 is two resistor arrays integrated with an SPI serial interface logic, two 8-bit wiper control registers and eight 8-bit, non-volatile memory data registers. Each resistor array contains 255 separate resistive elements connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL). RH and RL are symmetrical and may be interchanged. The tap positions between and at the ends of the series resistors are connected to the output wiper terminals (RW) by a CMOS transistor switch. Only one tap point for each potentiometer is connected to its wiper terminal at a time and is determined by the value of the wiper control register. Data can be read or written to the wiper control registers or the non-volatile memory data registers via the SPI bus. Additional instructions allows data to be transferred between the wiper control registers and each respective potentiometer's non-volatile data registers. Also, the device can be instructed to operate in an "increment/decrement" mode. 3 Document No. 2122, Rev. B CAT5261 ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias .................. -55°C to +125°C Storage Temperature ........................ -65°C to +150°C Voltage on any Pin with Respect to VSS(1)(2) ................ -2.0V to +VCC +2.0V VCC with Respect to Ground ................ -2.0V to +7.0V Package Power Dissipation Capability (TA = 25°C) ................................... 1.0W Lead Soldering Temperature (10 secs) ............ 300°C Wiper Current .................................................... +6mA *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Recommended Operating Conditions: VCC = +2.5V to +6.0V Temperature Industrial Min -40°C Max 85°C Notes: (1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns. (2) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V. POTENTIOMETER CHARACTERISTICS Over recommended operating conditions unless otherwise stated. Symbol RPOT RPOT Parameter Potentiometer Resistance (-00) Potentiometer Resistance (-50) Potentiometer Resistance Tolerance RPOT Matching Power Rating IW RW RW VTERM VN Wiper Current Wiper Resistance Wiper Resistance Voltage on any RH or RL Pin Noise Resolution Absolute Linearity (2) Test Conditions Min Typ 100 50 Max Units kΩ kΩ +20 % 1 25°C, each pot 50 +3 IW = +3mA @ VCC =3V IW = +3mA @ VCC = 5V VSS = 0V (1) 0.4 Rw(n)(actual)-R(n)(expected)(5) Rw(n+1)-[Rw(n)+LSB](5) (1) (1) (1) RPOT = 50kΩ(1) 10/10/25 0.4 +300 20 +1 +0.2 GND 200 100 300 150 VCC % mW mA Ω Ω V nV/ Hz % LSB (4) LSB (4) ppm/°C ppm/°C pF MHz Relative Linearity (3) TCRPOT TCRATIO CH/CL/CW fc Temperature Coefficient of RPOT Ratiometric Temp. Coefficient Potentiometer Capacitances Frequency Response Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) Absolute linearity is utilitzed to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. (3) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. (4) LSB = RTOT / 255 or (RH - RL) / 255, single pot (5) n = 0, 1, 2, ..., 255 Document No. 2122, Rev. B 4 CAT5261 D.C. OPERATING CHARACTERISTICS Over recommended operating conditions unless otherwise stated. Symbol ICC1 ICC2 ISB ILI ILO VIL VIH VOL1 VOH1 Parameter Power Supply Current Power Supply Current Non-Volatile WRITE Standby Current (VCC = 5.0V) Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage (VCC = 3.0V) Output High Voltage Test Conditions fSCK = 2.5MHz, SO Open VCC = 6 V Inputs = GND fsck = 2.5MHz, SO Open VCC = 6 V, Inputs = GND VIN = GND or VCC; SO Open VIN = GND to VCC VOUT = GND to VCC Min Typ Max 1 5 1 10 10 Units mA mA µA µA µA V V V V -1 VCC x 0.7 IOL = 3 mA IOH = -1.6mA VCC-0.8 VCC x 0.3 VCC + 1.0 0.4 PIN CAPACITANCE (1) Applicable over recommended operating range from TA = 25˚C, f = 1.0 MHz, VCC = 5.0V (unless otherwise noted). Symbol COUT CIN Test Conditions Output Capacitance (SO) Input Capacitance (CS, SCK, SI, WP, HOLD, A0, A1) Min Typ Max 8 6 Units pF pF Conditions VOUT=0V VIN=0V Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. 5 Document No. 2122, Rev. B CAT5261 A.C. CHARACTERISTICS Over recommended operating conditions unless otherwise stated. Test SYMBOL tSU tH tWH tWL fSCK tLZ tRI(1) tFI(1) tHD tCD tV tHO tDIS tHZ tCS tCSS tCSH PARAMETER Data Setup Time Data Hold Time SCK High Time SCK Low Time Clock Frequency HOLD to Output Low Z Input Rise Time Input Fall Time HOLD Setup Time HOLD Hold Time Output Valid from Clock Low Output Hold Time Output Disable Time HOLD to Output High Z CS High Time CS Setup Time CS Hold Time 2 250 250 0 250 100 100 100 200 Min 50 50 125 125 DC 3 50 2 2 Typ Max UNITS ns ns ns ns MHz ns µs µs ns ns ns ns ns ns ns ns ns CL = 50pF Conditions NOTE: (1) This parameter is tested initially and after a design or process change that affects the parameter. POWER UP TIMING (1)(2) Over recommended operating conditions unless otherwise stated. Symbol tPUR tPUW Parameter Power-up to Read Operation Power-up to Write Operation Min Typ Max 1 1 Units ms ms Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. XDCP TIMING Symbol Parameter tWRPO tWRL Wiper Response Time After Power Supply Stable Wiper Response Time After Instruction Issued Min 5 5 Max 10 10 Units µs µs Document No. 2122, Rev. B 6 CAT5261 WRITE CYCLE LIMITS Over recommended operating conditions unless otherwise stated. Symbol tWR Parameter Write Cycle Time Min Typ Max 5 Units ms RELIABILITY CHARACTERISTICS Over recommended operating conditions unless otherwise stated. Symbol NEND(1) TDR (1) Parameter Endurance Data Retention ESD Susceptibility Latch-Up Reference Test Method MIL-STD-883, Test Method 1033 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 3015 JEDEC Standard 17 Min 1,000,000 100 2000 100 Typ Max Units Cycles/Byte Years Volts mA VZAP(1) ILTH(1) Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. Figure 1. Sychronous Data Timing VIH tCS CS VIL VIH tCSS tCSH SCK VIL tSU VIH tWH tH tWL SI VIL VALID IN tRI tFI tV VOH tHO tDIS HI-Z SO VOL HI-Z Note: Dashed Line= mode (1, 1) Figure 2. HOLD Timing HOLD CS tCD SCK tHD HOLD tHZ SO HIGH IMPEDANCE tCD tHD tLZ 7 Document No. 2122, Rev. B CAT5261 INSTRUCTION AND REGISTER DESCRIPTION DEVICE TYPE / ADDRESS BYTE The first byte sent to the CAT5261 from the master/ processor is called the Device Address Byte. The most significant four bits of the Device Type address are a device type identifier. These bits for the CAT5261 are fixed at 0101[B] (refer to Table 1). The two least significant bits in the slave address byte, A1 - A0, are the internal slave address and must match the physical device address which is defined by the state of the A1 - A0 input pins for the CAT5261 to successfully continue the command sequence. Only the device which slave address matches the incoming device address sent by the master executes the instruction. The A1 - A0 inputs can be actively driven by CMOS input signals or tied to VCC or VSS. The remaining two bits in the device address byte must be set to 0. Table 1. Identification Byte Format Device Type Identifier INSTRUCTION BYTE The next byte sent to the CAT5261 contains the instruction and register pointer information. The four most significant bits used provide the instruction opcode I3 - I0. The R1 and R0 bits point to one of the four data registers of each associated potentiometer. The least two significant bits point to one of two Wiper Control Registers. The format is shown in Table 2. Data Register Selection Data Register Selected DR0 DR1 R1 0 0 R0 0 1 Slave Address ID3 0 (MSB) ID2 1 ID1 0 ID0 1 0 0 A1 A0 (LSB) Table 2. Instruction Byte Format Instruction Opcode Data Register Selection WCR/Pot Selection I3 (MSB) I2 I1 I0 R1 R0 P1 P0 (LSB) Document No. 2122, Rev. B 8 CAT5261 WIPER CONTROL AND DATA REGISTERS Wiper Control Register (WCR) The CAT5261 contains two 8-bit Wiper Control Registers, one for each potentiometer. The Wiper Control Register output is decoded to select one of 256 switches along its resistor array. The contents of the WCR can be altered in four ways: it may be written by the host via Write Wiper Control Register instruction; it may be written by transferring the contents of one of four associated Data Registers via the XFR Data Register instruction; it can be modified one step at a time by the Increment/decrement instruction (see Instruction section for more details). Finally, it is loaded with the content of its data register zero (DR0) upon power-up. The Wiper Control Register is a volatile register that loses its contents when the CAT5261 is powered-down. Although the register is automatically loaded with the value in DR0 upon power-up, this may be different from the value present at power-down. Data Registers (DR) Each potentiometer has four 8-bit non-volatile Data Registers. These can be read or written directly by the host. Data can also be transferred between any of the Table 3. Instruction Set Instruction Set Instruction Read Wiper Control Register Write Wiper Control Register Read Data Register Write Data Register XFR Data Register to Wiper Control Register XFR Wiper Control Register to Data Register Global XFR Data Registers to Wiper Control Registers Global XFR Wiper Control Registers to Data Register Increment/Decrement Wiper Control Register Read Status (WIP bit) Note: 1/0 = data is one or zero I3 I2 I1 I0 R1 R0 four Data Registers and the associated Wiper Control Register. Any data changes in one of the Data Registers is a non-volatile operation and will take a maximum of 5ms. If the application does not require storage of multiple settings for the potentiometer, the Data Registers can be used as standard memory locations for system parameters or user preference data. Write in Process The contents of the Data Registers are saved to nonvolatile memory when the CS input goes HIGH after a write sequence is received. The status of the internal write cycle can be monitored by issuing a Read Status command to read the Write in Process (WIP) bit. INSTRUCTIONS Five of the ten instructions are three bytes in length. These instructions are: — Read Wiper Control Register - read the current wiper position of the selected potentiometer in the WCR — Write Wiper Control Register - change current wiper position in the WCR of the selected potentiometer — Read Data Register - read the contents of the selected Data Register WCR1/ P1 WCR0/ P0 Operation Read the contents of the Wiper Control Register pointed to by P1-P0 Write new value to the Wiper Control Register pointed to by P1-P0 Read the contents of the Data Register pointed to by P1-P0 and R1-R0 Write new value to the Data Register pointed to by P1-P0 and R1-R0 Transfer the contents of the Data Register pointed to by P1-P0 and R1-R0 to its associated Wiper Control Register Transfer the contents of the Wiper Control Register pointed to by P1-P0 to the Data Register pointed to by R1-R0 Transfer the contents of the Data Registers pointed to by R1-R0 of all four pots to their respective Wiper Control Registers Transfer the contents of both Wiper Control Registers to their respective data Registers pointed to by R1-R0 of all four pots Enable Increment/decrement of the Control Latch pointed to by P1-P0 Read WIP bit to check internal write cycle status 1 1 1 1 1 0 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0 1/0 1/0 1/0 0 0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1 1 1 0 1/0 1/0 1/0 1/0 0 0 0 1 1/0 1/0 0 0 1 0 0 0 1/0 1/0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 1/0 0 1/0 1 9 Document No. 2122, Rev. B CAT5261 — Write Data Register - write a new value to the selected Data Register — Read Status - Read the status of the WIP bit which when set to "1" signifies a write cycle is in progress. The basic sequence of the three byte instructions is illustrated in Figure 8. These three-byte instructions exchange data between the WCR and one of the Data Registers. The WCR controls the position of the wiper. The response of the wiper to this action will be delayed by tWRL. A transfer from the WCR (current wiper position), to a Data Register is a write to non-volatile memory and takes a minimum of tWR to complete. The transfer can occur between one of the potentiometers and one of its associated registers; or the transfer can occur between both potentiometers and one associated register. Four instructions require a two-byte sequence to complete, as illustrated in Figure 7. These instructions transfer data between the host/processor and the CAT5261; either between the host and one of the data registers or directly between the host and the Wiper Control Register. These instructions are: — XFR Data Register to Wiper Control Register This transfers the contents of one specified Data Register to the associated Wiper Control Register. — XFR Wiper Control Register to Data Register This transfers the contents of the specified Wiper Figure 7. Two-Byte Instruction Sequence SI 0 1 0 1 0 0 Control Register to the specified associated Data Register. — Global XFR Data Register to Wiper Control Register This transfers the contents of all specified Data Registers to the associated Wiper Control Registers. — Global XFR Wiper Counter Register to Data Register This transfers the contents of all Wiper Control Registers to the specified associated Data Registers. INCREMENT/DECREMENT COMMAND The final command is Increment/Decrement (Figure 9 and 10). The Increment/Decrement command is different from the other commands. Once the command is issued the master can clock the selected wiper up and/ or down in one segment steps; thereby providing a fine tuning capability to the host. For each SCK clock pulse (tHIGH) while SI is HIGH, the selected wiper will move one resistor segment towards the RH terminal. Similarly, for each SCK clock pulse while SI is LOW, the selected wiper will move one resistor segment towards the RL terminal. See Instructions format for more detail. ID3 ID2 ID1 ID0 A3 A2 A1 A0 I3 Device ID Internal Address I2 I1 I0 R1 R0 P1 P0 Register Address Pot/WCR Address Instruction Opcode Figure 8. Three-Byte Instruction Sequence SI 0 1 0 1 0 A2 0 A1 A0 I3 I2 I1 I0 R1 R0 P1 P0 Data Pot/WCR Register Address Address D7 D6 D5 D4 D3 D2 D1 D0 WCR[7:0] or Data Register D[7:0] ID3 ID2 ID1 ID0 A3 Device ID Internal Address Instruction Opcode Figure 9. Increment/Decrement Instruction Sequence SI 0 1 0 1 0 A3 0 A2 A1 A0 Internal Address I3 I2 I1 I0 I N Pot/WCR C Data Register Address 1 Address R1 R0 P1 P0 I N C 2 I N C n D E C 1 D E C n ID3 ID2 ID1 ID0 Device ID Instruction Opcode Document No. 2122, Rev. B 10 CAT5261 Figure 10. Increment/Decrement Timing Limits INC/DEC Command Issued SCK tWRL SI RW Voltage Out INSTRUCTION FORMAT Read Wiper Control Register (WCR) DEVICE ADDRESSES CS 0 1010 10 INSTRUCTION 10 DATA 43 2 10 CS 0 AA 1 0 010 0P P7 6 5 Write Wiper Control Register (WCR) DEVICE ADDRESSES CS 0 1010 10 Read Data Register (DR) DEVICE ADDRESSES CS 0 1010 10 Write Data Register (DR) DEVICE ADDRESSES CS 0 1010 10 Read (WIP) Status DEVICE ADDRESSES CS 0 1010 10 INSTRUCTION DATA 43 0 2 0 0000 1W CS 0I P 11 Document No. 2122, Rev. B INSTRUCTION 10 DATA 43 2 10 CS 0 AA 1 0 100 0P P7 6 5 INSTRUCTION 101 0 DATA 43 2 10 CS High Voltage Write Cycle 0 A A 1 0 11RRP P7 6 5 INSTRUCTION 101 0 DATA 43 2 10 CS 0 A A 1 1 00RRP P7 6 5 0 AA 0 1 010 00 17 6 5 CAT5261 INSTRUCTION FORMAT (continued) Global Transfer Data Register (DR) to Wiper Control Register (WCR) DEVICE ADDRESSES CS 0 1010 INSTRUCTION 0 A A 0 0 01RR0 0 CS 10 10 Global Transfer Wiper Control Register (WCR) to Data Register (DR) DEVICE ADDRESSES CS 0 1010 INSTRUCTION High Voltage 0 A A 1 0 00RR0 0 CS 10 10 Write Cycle Transfer Wiper Control Register (WCR) to Data Register (DR) DEVICE ADDRESSES CS 0 1010 INSTRUCTION High Voltage 0 A A 1 1 1 0RRP P CS 10 101 0 Write Cycle Transfer Data Register (DR) to Wiper Control Register (WCR) DEVICE ADDRESSES CS 0 1010 INSTRUCTION 0 A A 1 1 01RRP P CS 10 101 0 Increment (I)/Decrement (D) Wiper Control Register (WCR) DEVICE ADDRESSES CS 0 1010 0 10 INSTRUCTION 10 DATA I/D I/D ••• CS A A 0 0 1 0 0 0 P P I/D I/D Notes: (1) Any write or transfer to the Non-volatile Data Registers is followed by a high voltage cycle after a STOP has been issued. Document No. 2122, Rev. B 12 CAT5261 ORDERING INFORMATION Prefix CAT Device # 5261 Suffix J I -50 -TE13 Optional Company ID Product Number Package J: SOIC U: TSSOP W: SOIC (Lead free, Halogen free) Y: TSSOP (Lead free, Halogen free) Tape & Reel TE13: 2000/Reel Resistance -50: 50kohm -00: 100kohm Notes: (1) The device used in the above example is a CAT5261JI-50-TE13 (SOIC, Industrial Temperature, 50kohm, Tape & Reel) PACKAGING INFORMATION 24-LEAD 300 MIL WIDE SOIC (J) 0.2914 (7.40) 0.2992 (7.60) 0.394 (10.00) 0.419 (10.65) 0.5985 (15.20) 0.6141 (15.60) 0.0926 (2.35) 0.1043 (2.65) 0.050 (1.27) BSC 0.013 (0.33) 0.020 (0.51) 0.0040 (0.10) 0.0118 (0.30) 0.010 (0.25) X 45 0.029 (0.75) 0.0091 (0.23) 0.0125 (0.32) 0 —8 0.016 (0.40) 0.050 (1.27) All Dimensions in inches (mm). 13 Document No. 2122, Rev. B CAT5261 PACKAGING INFORMATION CON'T 24 Lead TSSOP (U) 7.8 + 0.1 -A- 7.72 TYP 6.4 4.4 + 0.1 -B(1.78 TYP) 4.16 TYP 3.2 0.42 TYP 0.65 TYP PIN #1 INDENT. 0.2 C B A ALL LEAD TIPS LAND PATTERN RECOMMENDATION 1.1 MAX TYP 0.1 C ALL LEAD TIPS (0.9) -C0.10 + 0.05 TYP 0.65 TYP 0.19 - 0.30 TYP 0.3 M A B S C S SEE DETAIL A GAGE PLANE 0.09 - 0.20 TYP 0.25 0-8 o o 0.6+0.1 SEATING PLANE DETAIL A All Dimensions in mm. Document No. 2122, Rev. B 14 REVISION HISTORY Date 11/18/2003 5/6/2004 Rev. A B Reason Initial Issue Updated wiper resistance from 50Ω to 100Ω Updated Functional Diagram Updated WP Pin Description Updated notes in Absolute Max Ratings Eliminated Commercial temp range in all areas Updated Potentiometer Characteristics table Updated DC Characteristics table Updated Pin Capacitance table Updated AC Characteristics table Added XDCP Timing Table on page 6 Corrected Sychronous Data Timing (Figure 1) drawing Copyrights, Trademarks and Patents Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: DPP ™ AE2 ™ Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000. CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES. Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur. Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete. Catalyst Semiconductor, Inc. Corporate Headquarters 1250 Borregas Avenue Sunnyvale, CA 94089 Phone: 408.542.1000 Fax: 408.542.1200 www.catalyst-semiconductor.com Publication #: Revison: Issue date: 2122 B 5/6/04