CAT5401WI-50

CAT5401 Quad Digitally Programmable Potentiometers (DPP™) with 64 Taps and SPI Interface FEATURES Four linear taper digitally programmable potentiometers 64 resistor taps per potentiometer End to end resistance 2.5kΩ, 10kΩ, 50kΩ or 100kΩ Potentiometer control and memory access via SPI interface: Mode (0, 0) and (1, 1) Low wiper resistance, typically 80Ω Nonvolatile memory storage for up to four wiper settings for each potentiometer Automatic recall of saved wiper settings at power up 2.5 to 6.0 volt operation Standby current less than 1µA 1,000,000 nonvolatile WRITE cycles 100 year nonvolatile memory data retention 24-lead SOIC and 24-lead TSSOP Industrial temperature range For Ordering Information details, see page 14. DESCRIPTION The CAT5401 is four Digitally Programmable Potentiometers (DPPs™) integrated with control logic and 16 bytes of NVRAM memory. Each DPP consists of a series of 63 resistive elements connected between two externally accessible end points. The tap points between each resistive element are connected to the wiper outputs with CMOS switches. A separate 6-bit control register (WCR) independently controls the wiper tap switches for each DPP. Associated with each wiper control register are four 6-bit non-volatile memory data registers (DR) used for storing up to four wiper settings. Writing to the wiper control register or any of the non-volatile data registers is via a SPI serial bus. On power-up, the contents of the first data register (DR0) for each of the four potentiometers is automatically loaded into its respective wiper control register. The CAT5401 can be used as a potentiometer or as a two terminal, variable resistor. It is intended for circuit level or system level adjustments in a wide variety of applications. PIN CONFIGURATION SOIC Package (W) VCC RL0 RH0 RW0 CS WP SI A1 RL1 RH1 RW1 GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 CAT 19 5401 18 17 16 15 14 13 NC RL3 RH3 RW3 A0 SO HOLD SCK RL2 RH2 SI A1 RL1 RH1 RW1 GND NC RW2 RH2 RL2 TSSOP Package (Y) 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 CAT 19 5401 18 17 16 15 14 13 WP CS RW0 RH0 RL0 VCC NC RL3 RH3 RW3 A0 SO FUNCTIONAL DIAGRAM RH0 CS SCK SI SO RH1 RH2 RH3 SPI BUS INTERFACE WIPER CONTROL REGISTERS RW0 RW1 WP A0 A1 CONTROL LOGIC NONVOLATILE DATA REGISTERS RW2 RW3 RW2 SCK NC HOLD RL0 RL1 RL2 RL3 © Catalyst Semiconductor, Inc. Characteristics subject to change without notice 1 Doc. No. MD-2012 Rev. G CAT5401 PIN DESCRIPTIONS Pin# (SOIC) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Pin# (TSSOP) 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Name VCC RL0 RH0 RW0 ¯¯¯ CS ¯¯¯ WP SI A1 RL1 RH1 RW1 GND NC RW2 RH2 RL2 SCK ¯¯¯¯¯ HOLD SO A0 RW3 RH3 RL3 NC Function Supply Voltage Low Reference Terminal for Potentiometer 0 High Reference Terminal for Potentiometer 0 Wiper Terminal for Potentiometer 0 Chip Select Write Protection Serial Input Device Address Low Reference Terminal for Potentiometer 1 High Reference Terminal for Potentiometer 1 Wiper Terminal for Potentiometer 1 Ground No Connect Wiper Terminal for Potentiometer 2 High Reference Terminal for Potentiometer 2 Low Reference Terminal for Potentiometer 2 Bus Serial Clock Hold Serial Data Output Device Address, LSB Wiper Terminal for Potentiometer 3 High Reference Terminal for Potentiometer 3 Low Reference Terminal for Potentiometer 3 No Connect SI: Serial Input SI is the serial data input pin. This pin is used to input all opcodes, byte addresses and data to be written to the CAT5401. Input data is latched on the rising edge of the serial clock. SO: Serial Output SO is the serial data output pin. This pin is used to transfer data out of the CAT5401. During a read cycle, data is shifted out on the falling edge of the serial clock. SCK: Serial Clock SCK is the serial clock pin. This pin is used to synchronize the communication between the microcontroller and the CAT5401. Opcodes, byte addresses or data present on the SI pin are latched on the rising edge of the SCK. Data on the SO pin is updated on the falling edge of the SCK. A0, A1: Device Address Inputs These inputs set the device address when addressing multiple devices. A total of four devices can be addressed on a single bus. A match in the slave address must be made with the address input in order to initiate communication with the CAT5401. RH, RL: Resistor End Points The four sets of RH and RL pins are equivalent to the terminal connections on a mechanical potentiometer. RW: Wiper The four RW pins are equivalent to the wiper terminal of a mechanical potentiometer. ¯¯¯: Chip Select CS ¯¯¯ is the Chip select pin. ¯¯¯ low enables the CS CS CAT5401 and ¯¯¯ high disables the CAT5401. ¯¯¯ CS CS high takes the SO output pin to high impedance and forces the devices into a Standby mode (unless an internal write operation is underway). The CAT5401 draws ZERO current in the Standby mode. A high to low transition on ¯¯¯ is required prior to any sequence CS being initiated. A low to high transition on ¯¯¯ after a CS valid write sequence is what initiates an internal write cycle. ¯¯¯: Write Protect WP ¯¯¯ is the Write Protect pin. The Write Protect pin will allow normal read/write operations when held high. When WP ¯¯¯ is tied low, all non-volatile write operations to the Data registers are inhibited (change of wiper control register WP is allowed). ¯¯¯ going low while ¯¯¯ is still low will interrupt a write to the registers. If the internal write cycle has WP CS already been initiated, ¯¯¯ going low will have no effect on any write operation. WP ¯¯¯¯¯ HOLD: Hold The ¯¯¯¯¯ pin is used to pause transmission to the CAT5401 while in the middle of a serial sequence without HOLD ¯¯¯¯¯ having to retransmit entire sequence at a later time. To pause, HOLD must be brought low while SCK is low. The SO pin is in a high impedance state during the time the part is paused, and transitions on the SI pins will be ¯¯¯¯¯ ¯¯¯¯¯ ignored. To resume communication, HOLD is brought high, while SCK is low. (HOLD should be held high any ¯¯¯¯¯ time this function is not being used.) HOLD may be tied high directly to VCC or tied to VCC through a resistor. 2 Doc. No. MD-2012 Rev. G © Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT5401 SERIAL BUS PROTOCOL The CAT5041 supports the SPI bus data transmission protocol. The synchronous Serial Peripheral Interface (SPI) helps the CAT5401 to interface directly with many of today's popular microcontrollers. The CAT5041 contains an 8-bit instruction register. The instruction set and the operation codes are detailed in the instruction set table 3. After the device is selected with ¯¯¯ going low the first CS byte will be received. The part is accessed via the SI pin, with data being clocked in on the rising edge of SCK. The first byte contains one of the six op-codes that define the operation to be performed. DEVICE OPERATION The CAT5401 is four resistor arrays integrated with SPI serial interface logic, four 6-bit wiper control registers and sixteen 6-bit, non-volatile memory data registers. Each resistor array contains 63 separate resistive elements connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL). RH and RL are symmetrical and may be interchanged. The tap positions between and at the ends of the series resistors are connected to the output wiper terminals (RW) by a CMOS transistor switch. Only one tap point for each potentiometer is connected to its wiper terminal at a time and is determined by the value of the wiper control register. Data can be read or written to the wiper control registers or the nonvolatile memory data registers via the SPI bus. Additional instructions allows data to be transferred between the wiper control registers and each respective potentiometer's non-volatile data registers. Also, the device can be instructed to operate in an "increment/decrement" mode. © Catalyst Semiconductor, Inc. Characteristics subject to change without notice 3 Doc. No. MD-2012 Rev. G CAT5401 Absolute Maximum Ratings(1) Parameters Temperature Under Bias Storage Temperature Voltage on Any Pin with Respect to VSS(1) (2) VCC with Respect to Ground Package Power Dissipation Capability (TA = 25ºC) Lead Soldering Temperature (10s) Wiper Current Recommended Operating Conditions Parameters VCC Industrial Temperature Potentiometer Characteristics Over recommended operating conditions unless otherwise stated. Symbol RPOT RPOT RPOT RPOT Parameter Potentiometer Resistance (-00) Potentiometer Resistance (-50) Potentiometer Resistance (-10) Potentiometer Resistance (-2.5) Potentiometer Resistance Tolerance RPOT Matching Power Rating Wiper Current Wiper Resistance Wiper Resistance Voltage on any RH or RL Pin Noise Resolution Absolute Linearity (5) Relative Linearity (6) Temperature Coefficient of RPOT Ratiometric Temp. Coefficient Potentiometer Capacitances Frequency Response Test Conditions Min Typ 100 50 10 2.5 ±20 25°C, each pot IW = ±3mA @ VCC = 3V IW = ±3mA @ VCC = 5V VSS = 0V (4) RW(n)(actual) - R(n)(expected)(8) RW(n+1) - [RW(n) + LSB](8) (4) (4) (4) RPOT = 50kΩ (4) 200 100 GND 0.4 +1 +0.2 +300 20 10/10/25 0.4 1 50 +3 300 150 VCC Max Units kΩ kΩ kΩ kΩ % % mW mA Ω Ω V nV√Hz % LSB (7) LSB (7) ppm/ºC ppm/ºC pF MHz Ratings +2.5 to +6 -40 to +85 Units V °C Ratings -55 to +125 -65 to +150 -2.0 to +VCC + 2.0 -0.2 to +7.0 1.0 300 ±12 Units ºC °C V V W ºC mA IW RW RW VTERM VN TCRPOT TCRATIO CH/CL/CW fc Notes: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. (2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20ns. (3) Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC +1V. (4) This parameter is tested initially and after a design or process change that affects the parameter. (5) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. (6) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. (7) LSB = RTOT / 255 or (RH - RL) / 255, single pot (8) n = 0, 1, 2, ..., 255 Doc. No. MD-2012 Rev. G 4 © Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT5401 D.C. OPERATING CHARACTERISTICS Over recommended operating conditions unless otherwise stated. Symbol ICC ISB ILI ILO VIL VIH VOL1 Parameter Power Supply Current Standby Current (VCC = 5.0V) Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage (VCC = 3.0V) IOL = 3 mA Test Conditions fSCL = 2MHz, SO = Open Inputs = GND VIN = GND or VCC, SO = Open VIN = GND to VCC VOUT = GND to VCC -1 VCC x 0.7 Min Max 1 5 10 10 VCC x 0.3 VCC + 1.0 0.4 Units mA µA µA µA V V V PIN Capacitance (1) Available over recommended operating range from TA = 25ºC, f = 1.0MHz, VCC = 5V (unless otherwise noted). Symbol COUT CIN Test Input/Output Capacitance (SDA) Input Capacitance (A0, A1, A2, A3, SCL, ¯¯¯) WP Conditions VOUT = 0V VIN = 0V Max. 8 6 Units pF pF A.C. CHARACTERISTICS Over recommended operating conditions unless otherwise stated. Symbol tSU tH tWH tWL fSCK tLZ tRI( 1) Parameter Data Setup Time Data Hold Time SCK High Time SCK Low Time Clock Frequency ¯¯¯¯¯ HOLD to Output Low Z Input Rise Time Input Fall Time ¯¯¯¯¯ HOLD Setup Time ¯¯¯¯¯ HOLD Hold Time Write Cycle Time Output Valid from Clock Low Output Hold Time Output Disable Time ¯¯¯¯¯ HOLD to Output High Z ¯¯¯ High Time CS ¯¯¯ Setup Time CS ¯¯¯ Hold Time CS Test Conditions Min 50 50 125 125 DC Typ Max Units ns ns ns ns 3 50 2 2 MHz ns µs µs ns ns tFI(1) tHD tCD tWC tV tHO tDIS tHZ tCS tCSS tCSH Note: (1) CL = 50pF 100 100 10 250 0 250 100 250 250 250 ms ns ns ns ns ns ns ns This parameter is tested initially and after a design or process change that affects the parameter. © Catalyst Semiconductor, Inc. Characteristics subject to change without notice 5 Doc. No. MD-2012 Rev. G CAT5401 Power Up Timing (1)(2) Symbol tPUR tPUW Parameter Power-up to Read Operation Power-up to Write Operation Max 1 1 Units ms ms Write Cycle Limits Symbol tWR Parameter Write Cycle Time Max 5 Units ms Reliability Characteristics Symbol NEND (3) Parameter Endurance Data Retention ESD Susceptibility Latch-Up Reference Test Method MIL-STD-883, Test Method 1033 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 3015 JEDEC Standard 17 Min 1,000,000 100 2000 100 Max Units Cycles/Byte Years V mA TDR(3) VZAP(3) ILTH(3) Figure 1. Synchronous Data Timing VIH tCS CS VIL tCSS VIH VIL VIH tSU VALID IN tRI tFI tCSH tWL SCK tWH tH SI VIL tV tHO tDIS HI-Z SO VOH VOL HI-Z ¯¯¯¯¯ Figure 2. HOLD Timing CS tCD SCK tHD HOLD tHZ SO tHD tCD HIGH IMPEDANCE Notes: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) tPUR and tPUW are delays required from the time VCC is stable until the specified operation can be initiated. (3) This parameter is tested initially and after a design or process change that affects the parameter. (4) Dashed Line = mode (1, 1) - - - - - - - tLZ Doc. No. MD-2012 Rev. G 6 © Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT5401 INSTRUCTION AND REGISTER DESCRIPTION DEVICE TYPE / ADDRESS BYTE The first byte sent to the CAT5401 from the master/ processor is called the Device Address Byte. The most significant four bits of the Device Type address are a device type identifier. These bits for the CAT5401 are fixed at 0101[B] (refer to Table 1). The two least significant bits in the slave address byte, A1 - A0, are the internal slave address and must match the physical device address which is defined by the state of the A1 - A0 input pins for the CAT5401 to successfully continue the command sequence. Only the device which slave address matches the incoming device address sent by the master executes the instruction. The A1 - A0 inputs can be actively driven by CMOS input signals or tied to VCC or VSS. The remaining two bits in the device address byte must be set to 0. INSTRUCTION BYTE The next byte sent to the CAT5401 contains the instruction and register pointer information. The four most significant bits used provide the instruction opcode I [3:0]. The R1 and R0 bits point to one of the four data registers of each associated potentiometer. The least two significant bits point to one of four Wiper Control Registers. The format is shown in Table 2. Data Register Selection Data Register Selected DR0 DR1 DR2 DR3 R1 0 0 1 1 R0 0 1 0 1 Table 1. Identification Byte Format Device Type Identifier Slave Address ID3 0 (MSB) ID2 1 ID1 0 ID0 1 0 0 A1 A0 (LSB) Table 2. Instruction Byte Format Instruction Opcode Data Register Selection WCR/Pot Selection I3 (MSB) I2 I1 I0 R1 R0 P1 P0 (LSB) © Catalyst Semiconductor, Inc. Characteristics subject to change without notice 7 Doc. No. MD-2012 Rev. G CAT5401 Wiper Control and Data Registers Wiper Control Register (WCR) The CAT5401 contains four 6-bit Wiper Control Registers, one for each potentiometer. The Wiper Control Register output is decoded to select one of 64 switches along its resistor array. The contents of the WCR can be altered in four ways: it may be written by the host via Write Wiper Control Register instruction; it may be written by transferring the contents of one of four associated Data Registers via the XFR Data Register instruction, it can be modified one step at a time by the Increment/decrement instruction (see Instruction section for more details). Finally, it is loaded with the content of its data register zero (DR0) upon power-up. The Wiper Control Register is a volatile register that loses its contents when the CAT5401 is powereddown. Although the register is automatically loaded with the value in DR0 upon power-up, this may be different from the value present at power-down. Data Registers (DR) Each potentiometer has four 6-bit non-volatile Data Registers. These can be read or written directly by the host. Data can also be transferred between any of the four Data Registers and the associated Wiper Control Register. Any data changes in one of the Data Table 3. Instruction Set Instruction Set Instruction Read Wiper Control Register Write Wiper Control Register Read Data Register Write Data Register XFR Data Register to Wiper Control Register XFR Wiper Control Register to Data Register Global XFR Data Registers to Wiper Control Registers Global XFR Wiper Control Registers to Data Register Increment/Decrement Wiper Control Register Read Status (WIP bit) I3 I2 I1 I0 R1 R0 WCR1/ P1 WCR0/ P0 Operation Read the contents of the Wiper Control Register pointed to by P1-P0 Write new value to the Wiper Control Register pointed to by P1-P0 Read the contents of the Data Register pointed to by P1-P0 and R1-R0 Write new value to the Data Register pointed to by P1-P0 and R1-R0 Transfer the contents of the Data Register pointed to by P1-P0 and R1-R0 to its associated Wiper Control Register Transfer the contents of the Wiper Control Register pointed to by P1-P0 to the Data Register pointed to by R1-R0 Transfer the contents of the Data Registers pointed to by R1-R0 of all four pots to their respective Wiper Control Registers Transfer the contents of both Wiper Control Registers to their respective data Registers pointed to by R1-R0 of all four pots Enable Increment/decrement of the Control Latch pointed to by P1-P0 Read WIP bit to check internal write cycle status Registers is a non-volatile operation and will take a maximum of 5ms. Write in Process The contents of the Data Registers are saved to nonvolatile memory when the ¯¯¯ input goes HIGH CS after a write sequence is received. The status of the internal write cycle can be monitored by issuing a Read Status command to read the Write in Process (WIP) bit. Instructions Four of the nine instructions are three bytes in length. These instructions are: — Read Wiper Control Register – read the current wiper position of the selected potentiometer in the WCR — Write Wiper Control Register – change current wiper position in the WCR of the selected potentiometer — Read Data Register – read the contents of the selected Data Register — Write Data Register – write a new value to the selected Data Register — Read Status – Read the status of the WIP bit which when set to "1" signifies a write cycle is in progress. Note: 1/0 = data is one or zero 1 1 1 1 1 1 0 1 0 0 0 0 0 1 1 1 0 0 0 1 0 1 1 0 0 1 0 0 1 0 1 0 1 0 1 0 1 0 0 1 0 0 1/0 1/0 1/0 1/0 1/0 1/0 0 0 0 0 1/0 1/0 1/0 1/0 1/0 1/0 0 0 1/0 1/0 1/0 1/0 1/0 1/0 0 0 1/0 0 1/0 1/0 1/0 1/0 1/0 1/0 0 0 1/0 1 Doc. No. MD-2012 Rev. G 8 © Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT5401 The basic sequence of the three byte instructions is illustrated in Figure 4. These three-byte instructions exchange data between the WCR and one of the Data Registers. The WCR controls the position of the wiper. The response of the wiper to this action will be delayed by tWRL. A transfer from the WCR (current wiper position), to a Data Register is a write to nonvolatile memory and takes a minimum of tWR to complete. The transfer can occur between one of the four potentiometers and one of its associated registers; or the transfer can occur between all potentiometers and one associated register. Four instructions require a two-byte sequence to complete, as illustrated in Figure 3. These instructions transfer data between the host/processor and the CAT5401; either between the host and one of the data registers or directly between the host and the Wiper Control Register. These instructions are: — XFR Data Register to Wiper Control Register This transfers the contents of one specified Data Register to the associated Wiper Control Register. — XFR Wiper Control Register to Data Register This transfers the contents of the specified Wiper Control Register to the specified associated Data Register. Figure 3. Two-Byte Instruction Sequence SI 0 1 0 1 0 0 A2 A1 A0 I3 Internal Address I2 I1 I0 R1 R0 P1 P0 Register Address Pot/WCR Address — Gang XFR Data Register to Wiper Control Register This transfers the contents of all specified Data Registers to the associated Wiper Control Registers. — Gang XFR Wiper Counter Register to Data Register This transfers the contents of all Wiper Control Registers to the specified associated Data Registers. Increment/Decrement Command The final command is Increment/Decrement (Figure 5). The Increment/Decrement command is different from the other commands. Once the command is issued the master can clock the selected wiper up and/or down in one segment steps; thereby providing a fine tuning capability to the host. For each SCK clock pulse (tHIGH) while SI is HIGH, the selected wiper will move one resistor segment towards the RH terminal. Similarly, for each SCK clock pulse while SI is LOW, the selected wiper will move one resistor segment towards the RL terminal. See Instructions format for more detail. ID3 ID2 ID1 ID0 A3 Device ID Instruction Opcode Figure 4. Three-Byte Instruction Sequence SI 0 1 0 1 0 0 A2 A1 A0 I3 I2 I1 I0 R1 R0 P1 P0 Data Pot/WCR Register Address Address D7 D6 D5 D4 D3 D2 D1 D0 WCR[7:0] or Data Register D[7:0] ID3 ID2 ID1 ID0 A3 Device ID Internal Address Instruction Opcode Figure 5. Increment/Decrement Instruction Sequence SI 0 1 0 1 0 A3 0 A2 A1 A0 Internal Address I3 I2 I1 I0 I N Pot/WCR C Data Register Address 1 Address R1 R0 P1 P0 I N C 2 I N C n D E C 1 D E C n ID3 ID2 ID1 ID0 Device ID Instruction Opcode © Catalyst Semiconductor, Inc. Characteristics subject to change without notice 9 Doc. No. MD-2012 Rev. G CAT5401 Figure 6. Increment/Decrement Timing Limits INC/DEC Command Issued SCK tWRID SI RW Voltage Out INSTRUCTION FORMAT Read Wiper Control Register (WCR) DEVICE ADDRESSES ¯¯¯ CS 0 1 0 1 0 0 A1 A0 1 0 INSTRUCTION 0 1 0 0 P1 P0 7 0 6 0 5 DATA 4 3 2 1 0 ¯¯¯ CS Write Wiper Control Register (WCR) DEVICE ADDRESSES ¯¯¯ CS 0 1 0 1 0 0 A1 A0 1 0 INSTRUCTION 1 0 0 0 P1 P0 7 0 6 0 5 DATA 4 3 2 1 0 ¯¯¯ CS Read Data Register (DR) DEVICE ADDRESSES ¯¯¯ CS 0 1 0 1 0 0 A1 A0 1 0 1 INSTRUCTION 1 R1 R0 P1 P0 7 6 5 DATA 4 3 2 1 0 ¯¯¯ CS Write Data Register (DR) DEVICE ADDRESSES ¯¯¯ CS 0 1 0 1 0 0 A1 A0 1 1 0 INSTRUCTION 0 R1 R0 P1 P0 7 6 5 DATA 4 3 2 1 0 ¯¯¯ CS High Voltage Write Cycle Read (WIP) Status DEVICE ADDRESSES ¯¯¯ CS 0 1 0 1 0 0 A1 A0 0 1 INSTRUCTION 0 1 0 0 0 1 7 0 6 0 5 0 DATA 4 0 3 0 2 0 1 0 W I P ¯¯¯ CS Doc. No. MD-2012 Rev. G 10 © Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT5401 INSTRUCTION FORMAT (continued) Global Transfer Data Register (DR) to Wiper Control Register (WCR) DEVICE ADDRESSES ¯¯¯ CS 0 1 0 1 0 0 A1 A0 0 0 0 INSTRUCTION 1 R1 R0 0 0 ¯¯¯ CS Global Transfer Wiper Control Register (WCR) to Data Register (DR) DEVICE ADDRESSES ¯¯¯ CS 0 1 0 1 0 0 A1 A0 1 0 0 INSTRUCTION 0 R1 R0 0 0 ¯¯¯ CS High Voltage Write Cycle Transfer Wiper Control Register (WCR) to Data Register (DR) DEVICE ADDRESSES ¯¯¯ CS 0 1 0 1 0 0 A1 A0 1 1 1 INSTRUCTION 0 R1 R0 P1 P0 ¯¯¯ CS High Voltage Write Cycle Transfer Data Register (DR) to Wiper Control Register (WCR) DEVICE ADDRESSES ¯¯¯ CS 0 1 0 1 0 0 A1 A0 1 1 0 INSTRUCTION 1 R1 R0 P1 P0 ¯¯¯ CS Increment (I)/Decrement (D) Wiper Control Register (WCR) DEVICE ADDRESSES ¯¯¯ CS 0 1 0 1 0 0 A1 A0 0 0 1 INSTRUCTION 0 0 0 P1 P0 I/D I/D DATA ... I/D I/D ¯¯¯ CS Note: (1) Any write or transfer to the Non-volatile Data Registers is followed by a high voltage cycle after ¯¯¯ goes high. CS © Catalyst Semiconductor, Inc. Characteristics subject to change without notice 11 Doc. No. MD-2012 Rev. G CAT5401 PACKAGE OUTLINES SOIC 24-Lead 300mils (W) (1)(2) SYMBOL MIN NOM MAX A A1 A2 b E1 E 2.35 0.10 2.05 0.31 0.20 15.20 10.11 7.34 1.27 BSC 0.25 0.40 0° 5° 2.65 0.30 2.55 0.51 0.33 15.40 10.51 7.60 0.75 1.27 8° 15° c D E E1 e h b PIN#1 IDENTIFICATION e L θ θ1 TOP VIEW D h h θ1 A A2 θ θ1 A1 SIDE VIEW L END VIEW c 2HFor current Tape and Reel information, download the PDF file from: Notes: (1) All dimensions are in millimeters, angles in degrees. (2) Complies with JEDEC standard MO-013. Doc. No. MD-2012 Rev. G 12 © Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT5401 TSSOP 24-Lead 4.4mm (Y) (1)(2) b SYMBOL MIN NOM MAX A A1 A2 b E1 E 1.20 0.05 0.80 0.19 0.09 7.70 6.25 4.30 7.80 6.40 4.40 0.65 BSC 1.00 REF 0.50 0° 0.60 0.70 8° 0.15 1.05 0.30 0.20 7.90 6.55 4.50 c D E E1 e L L1 θ1 e TOP VIEW D c A2 A θ1 L1 L SIDE VIEW END VIEW A1 3HFor current Tape and Reel information, download the PDF file from: Notes: (1) All dimensions are in millimeters, angles in degrees. (2) Complies with JEDEC standard MO-153. © Catalyst Semiconductor, Inc. Characteristics subject to change without notice 13 Doc. No. MD-2012 Rev. G CAT5401 EXAMPLE OF ORDERING INFORMATION Prefix CAT Device # Suffix 5401 W Package W: SOIC Y: TSSOP I Temperature Range I = Industrial (-40ºC to 85ºC) -00 Resistance 25: 2.5kΩ 10: 10kΩ 50: 50kΩ 00: 100kΩ - T1 Tape & Reel T: Tape & Reel 1: 1000/Reel - SOIC 2: 2000/Reel - TSSOP Company ID Product Number 5401 Notes: (1) (2) (3) All packages are RoHS-compliant (Lead-free, Halogen-free). The device used in the above example is a CAT5401WI-00-T1 (SOIC, Industrial Temperature, 100kΩ, Tape & Reel). The lead finish is Matte-Tin. Ordering Part Number CAT5401WI-25 CAT5401WI-10 CAT5401WI-50 CAT5401WI-00 CAT5401YI-25 CAT5401YI-10 CAT5401YI-50 CAT5401YI-00 Doc. No. MD-2012 Rev. G 14 © Catalyst Semiconductor, Inc. Characteristics subject to change without notice REVISION HISTORY Date 03/31/2004 Rev. F Reason Changed Preliminary designation to Final Eliminated Commercial temp range in all areas Updated Potentiometer characteristics notes Updated Pin Descriptions (A0, A1 and ¯¯¯) WP Updated notes for Absolute Max Ratings 80 and Potentiometer Characteristics Added Example of Ordering Information Deleted BGA package Added MD- to document number 10/16/2007 G Copyrights, Trademarks and Patents © Catalyst Semiconductor, Inc. Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: Adaptive Analog™, Beyond Memory™, DPP™, EZDim™, LDD™, MiniPot™, Quad-Mode™ and Quantum Charge Programmable™ Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES. Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur. Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete. Catalyst Semiconductor, Inc. Corporate Headquarters 2975 Stender Way Santa Clara, CA 95054 Phone: 408.542.1000 Fax: 408.542.1200 1Hwww.catsemi.com Document No: MD-2012 Revision: G Issue date: 10/16/07