CAT5409JI-50-TE13

CAT5409 Quad Digitally Programmable Potentiometers (DPP™) with 64 Taps and 2-wire Interface FEATURES s Four linear-taper digital potentiometers s 64 resistor taps per potentiometer s End-to-end resistance 2.5kΩ, 10kΩ, 50kΩ or 100kΩ s 2-wire interface (I C like) s Low wiper resistance, typically 80Ω s Four non-volatile wiper settings for each 2 H GEN FR ALO EE LE A D F R E ETM s Recall of saved wiper settings at power-up s 2.5 to 6.0 volt operation s Standby current less than 1µA s 1,000,000 nonvolatile WRITE cycles s 100 year nonvolatile memory data retention s 24-lead SOIC, 24-lead TSSOP and BGA s Write protection for data register potentiometer DESCRIPTION The CAT5409 is four Digitally Programmable Potentiometers (DPP™) integrated with control logic and 16 bytes of NVRAM memory. A separate 6-bit control register (WCR) independently controls the wiper tap position for each DPP. Associated with each wiper control register are four 6bit non-volatile memory data registers (DR) used for storing up to four wiper settings. Writing to the wiper control register or any of the non-volatile data registers is via a 2-wire serial bus (I2C-like). On power-up, the contents of the first data register (DR0) for each of the four potentiometers is automatically loaded into its respective wiper control register (WCR). The Write Protection ( WP ) pin protects against inadvertent programming of the data register. The CAT5409 can be used as a potentiometer or as a two terminal, variable resistor. It is intended for circuit level or system level adjustments in a wide variety of applications. PIN CONFIGURATION SOIC Package (J, W) VCC RL0 RH0 RW0 A2 WP SDA A1 RL1 RH1 RW1 GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 CAT 19 5409 18 17 16 15 14 13 1 A B RW0 RL0 VCC NC RL3 RW3 NC RL3 RH3 RW3 A0 NC A3 SCL RL2 RH2 RW2 NC 2 A2 WP RH0 RH3 NC A0 SDA A1 RL1 RH1 RW1 GND NC RW2 RH2 RL2 SCL A3 3 A1 SDA RH1 RH2 A3 SCL TSSOP Package (U, Y) 1 2 3 4 5 6 7 8 9 10 11 12 4 RL1 RW1 VSS NC RW2 RL2 24 23 22 21 20 CAT 19 5409 18 17 16 15 14 13 WP A2 RW0 RH0 RL0 VCC NC RL3 RH3 RW3 A0 NC FUNCTIONAL DIAGRAM RH0 RH1 RH2 R H3 SCL SDA 2-WIRE BUS INTERFACE WIPER CONTROL REGISTERS R W0 R W1 WP R W2 A0 A1 A2 A3 CONTROL LOGIC NONVOLATILE DATA REGISTERS R W3 RL0 RL1 RL2 R L3 BGA C D E F Top View - Bump Side Down Document No. 2010, Rev. I © 2004 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 1 CAT5409 PIN DESCRIPTION Pin (TSSOP) 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 PIN DESCRIPTIONS Function Supply Voltage Low Reference Terminal for Potentiometer 0 High Reference Terminal for Potentiometer 0 Wiper Terminal for Potentiometer 0 Device Address Write Protection Serial Data Input/Output Device Address Low Reference Terminal for Potentiometer 1 High Reference Terminal for Potentiometer 1 Wiper Terminal for Potentiometer 1 Ground No Connect Wiper Terminal for Potentiometer 2 High Reference Terminal for Potentiometer 2 Low Reference Terminal for Potentiometer 2 Bus Serial Clock Device Address No Connect Device Address, LSB Wiper Terminal for Potentiometer 3 High Reference Terminal for Potentiometer 3 Low Reference Terminal for Potentiometer 3 No Connect Pin (SOIC) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Pin (BGA) Name C1 B1 C2 A1 A2 B2 B3 A3 A4 C3 B4 C4 D4 E4 D3 F4 F3 E3 D1 F2 F1 D2 E1 E2 VCC RL0 RH0 RW0 A2 WP SDA A1 RL1 RH1 RW1 GND NC RW2 RH2 RL2 SCL A3 NC A0 RW3 RH3 RL3 NC SCL: Serial Clock The CAT5409 serial clock input pin is used to clock all data transfers into or out of the device. SDA: Serial Data The CAT5409 bidirectional serial data pin is used to transfer data into and out of the device. The SDA pin is an open drain output and can be wireOred with the other open drain or open collector outputs. A0, A1, A2, A3: Device Address Inputs These inputs set the device address when addressing multiple devices. A total of sixteen devices can be addressed on a single bus. A match in the slave address must be made with the address input in order to initiate communication with the CAT5409. RH, RL: Resistor End Points The four sets of RH and RL pins are equivalent to the terminal connections on a mechanical potentiometer. RW: Wiper The four RW pins are equivalent to the wiper terminal of a mechanical potentiometer. WP: Write Protect Input The WP pin when tied low prevents non-volatile writes to the data registers (change of wiper control register is allowed) and when tied high or left floating normal read/write operations are allowed. See Write Protection on page 7 for more details. DEVICE OPERATION The CAT5409 is four resistor arrays integrated with 2wire serial interface logic, four 6-bit wiper control registers and sixteen 6-bit, non-volatile memory data registers. Each resistor array contains 63 separate resistive elements connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL). RH and RL are symmetrical and may be interchanged. The tap positions between and at the ends of the series resistors are connected to the output wiper terminals (RW) by a CMOS transistor switch. Only one tap point for each potentiometer is connected to its wiper terminal at a time and is determined by the value of the wiper control register. Data can be read or written to the wiper control registers or the non-volatile memory data registers via the 2-wire bus. Additional instructions allows data to be transferred between the wiper control registers and each respective potentiometer's non-volatile data registers. Also, the device can be instructed to operate in an "increment/decrement" mode. Document No. 2010, Rev. I 2 CAT5409 ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias .................. -55°C to +125°C Storage Temperature ........................ -65°C to +150°C Voltage on any Pin with Respect to VSS(1)(2) ................ -2.0V to +VCC +2.0V VCC with Respect to Ground ................ -2.0V to +7.0V Package Power Dissipation Capability (TA = 25°C) ................................... 1.0W Lead Soldering Temperature (10 secs) ............ 300°C Wiper Current .................................................. +12mA *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Recommended Operating Conditions: VCC = +2.5V to +6.0V Temperature Industrial Min -40°C Max 85°C Notes: (1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns. (2) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V. POTENTIOMETER CHARACTERISTICS Over recommended operating conditions unless otherwise stated. Symbol RPOT RPOT RPOT RPOT Parameter Potentiometer Resistance (-00) Potentiometer Resistance (-50) Potentiometer Resistance (-10) Potentiometer Resistance (-2.5) Potentiometer Resistance Tolerance RPOT Matching Power Rating IW RW RW VTERM VN Wiper Current Wiper Resistance Wiper Resistance Voltage on any RH or RL Pin Noise Resolution Absolute Linearity (2) Relative Linearity (3) TCRPOT TCRATIO CH/CL/CW fc Temperature Coefficient of RPOT Ratiometric Temp. Coefficient Potentiometer Capacitances Frequency Response Rw(n)(actual)-R(n)(expected)(5) Rw(n+1)-[Rw(n)+LSB](5) (1) (1) (1) RPOT = 50kΩ(1) 10/10/25 0.4 +300 20 IW = +3mA @ VCC =3V IW = +3mA @ VCC = 5V VSS = 0V (1) GND TBD 1.6 +1 +0.2 80 25°C, each pot Test Conditions Min Typ 100 50 10 2.5 +20 1 50 +6 300 150 VCC Max Units kΩ kΩ kΩ kΩ % % mW mA Ω Ω V nV/ Hz % LSB (4) LSB (4) ppm/°C ppm/°C pF MHz Notes: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) Absolute linearity is utilitzed to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. (3) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. (4) LSB = RTOT / 63 or (RH - RL) / 63, single pot (5) n = 0, 1, 2, ..., 63 3 Document No. 2010, Rev. I CAT5409 D.C. OPERATING CHARACTERISTICS Over recommended operating conditions unless otherwise stated. Symbol ICC ISB ILI ILO VIL VIH VOL1 Parameter Power Supply Current Standby Current (VCC = 5.0V) Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage (VCC = 3.0V) Test Conditions fSCL = 400kHz VIN = GND or VCC; SDA Open VIN = GND to VCC VOUT = GND to VCC Min Typ Max 1 1 10 10 Units mA µA µA µA V V V -1 VCC x 0.7 IOL = 3 mA VCC x 0.3 VCC + 1.0 0.4 CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V Symbol CI/O CIN (1) (1) Test Input/Output Capacitance (SDA) Input Capacitance (A0, A1, A2, A3, SCL, WP) Conditions VI/O = 0V VIN = 0V Min Typ Max 8 6 Units pF pF A.C. CHARACTERISTICS Over recommended operating conditions unless otherwise stated. Symbol fSCL TI(1) tAA tBUF(1) tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR (1) Parameter Clock Frequency Noise Suppression Time Constant at SCL, SDA Inputs SLC Low to SDA Data Out and ACK Out Time the bus must be free before a new transmission can start Start Condition Hold Time Clock Low Period Clock High Period Start Condition SetupTime (for a Repeated Start Condition) Data in Hold Time Data in Setup Time SDA and SCL Rise Time SDA and SCL Fall Time Stop Condition Setup Time Data Out Hold Time Min Typ Max 400 50 0.9 Units kHz ns µs µs µs µs µs µs ns ns µs ns µs ns 1.2 0.6 1.2 0.6 0.6 0 100 0.3 300 0.6 50 tF(1) tSU:STO tDH POWER UP TIMING (1) Over recommended operating conditions unless otherwise stated. Symbol tPUR tPUW Parameter Power-up to Read Operation Power-up to Write Operation Min Typ Max 1 1 Units ms ms Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. Document No. 2010, Rev. I 4 CAT5409 WRITE CYCLE LIMITS Over recommended operating conditions unless otherwise stated. Symbol tWR Parameter Write Cycle Time Min Typ Max 5 Units ms The write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address. RELIABILITY CHARACTERISTICS Over recommended operating conditions unless otherwise stated. Symbol NEND (1) Parameter Endurance Data Retention ESD Susceptibility Latch-Up Reference Test Method MIL-STD-883, Test Method 1033 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 3015 JEDEC Standard 17 Min 1,000,000 100 2000 100 Typ Max Units Cycles/Byte Years Volts mA TDR(1) VZAP(1) ILTH(1)(2) Figure 1. Bus Timing tF tLOW SCL tSU:STA tHD:STA tHD:DAT tSU:DAT tSU:STO tHIGH tLOW tR SDA IN tAA SDA OUT tDH tBUF Figure 2. Write Cycle Timing SCL SDA 8TH BIT BYTE n ACK tWR STOP CONDITION START CONDITION ADDRESS Figure 3. Start/Stop Timing SDA SCL START BIT STOP BIT Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. 5 Document No. 2010, Rev. I CAT5409 SERIAL BUS PROTOCOL The following defines the features of the 2-wire bus protocol: (1) Data transfer may be initiated only when the bus is not busy. (2) During a data transfer, the data line must remain stable whenever the clock line is high. Any changes in the data line while the clock is high will be interpreted as a START or STOP condition. The device controlling the transfer is a master, typically a processor or controller, and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the CAT5409 will be considered a slave device in all applications. START Condition The START Condition precedes all commands to the device, and is defined as a HIGH to LOW transition of SDA when SCL is HIGH. The CAT5409 monitors the SDA and SCL lines and will not respond until this condition is met. STOP Condition A LOW to HIGH transition of SDA when SCL is HIGH determines the STOP condition. All operations must end with a STOP condition. the particular slave device it is requesting. The four most significant bits of the 8-bit slave address are fixed as 0101 for the CAT5409 (see Figure 5). The next four significant bits (A3, A2, A1, A0) are the device address bits and define which device the Master is accessing. Up to sixteen devices may be individually addressed by the system. Typically, +5V and ground are hard-wired to these pins to establish the device's address. After the Master sends a START condition and the slave address byte, the CAT5409 monitors the bus and responds with an acknowledge (on the SDA line) when its address matches the transmitted slave address. Acknowledge After a successful data transfer, each receiving device is required to generate an acknowledge. The Acknowledging device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data. The CAT5409 responds with an acknowledge after receiving a START condition and its slave address. If the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8-bit byte. When the CAT5409 is in a READ mode it transmits 8 bits of data, releases the SDA line, and monitors the line for an acknowledge. Once it receives this acknowledge, the CAT5409 will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a STOP condition. DEVICE ADDRESSING The bus Master begins a transmission by sending a START condition. The Master then sends the address of Figure 4. Acknowledge Timing SCL FROM MASTER 1 8 9 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER START ACKNOWLEDGE 5020 FHD F06 Document No. 2010, Rev. I 6 CAT5409 WRITE OPERATIONS In the Write mode, the Master device sends the START condition and the slave address information to the Slave device. After the Slave generates an acknowledge, the Master sends the instruction byte that defines the requested operation of CAT5409. The instruction byte consist of a four-bit opcode followed by two register selection bits and two pot selection bits. After receiving another acknowledge from the Slave, the Master device transmits the data to be written into the selected register. The CAT5409 acknowledges once more and the Master generates the STOP condition, at which time if a nonvolatile data register is being selected, the device begins an internal programming cycle to non-volatile memory. While this internal cycle is in progress, the device will not respond to any request from the Master device. Acknowledge Polling The disabling of the inputs can be used to take advantage of the typical write cycle time. Once the stop condition is issued to indicate the end of the host's write operation, Figure 5. Slave Address Bits the CAT5409 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address. If the CAT5409 is still busy with the write operation, no ACK will be returned. If the CAT5409 has completed the write operation, an ACK will be returned and the host can then proceed with the next instruction operation. WRITE PROTECTION The Write Protection feature allows the user to protect against inadvertent programming of the non-volatile data registers. If the WP pin is tied to LOW, the data registers are protected and become read only. Similarly, the WP pin going low after start but after start will interrupt non-volatile write to data registers, while the WP pin going low after internal write cycle has started, will have no effect on any write operation. The CAT5409 will accept both slave addresses and instructions, but the data registers are protected from programming by the device’s failure to send an acknowledge after data is received. CAT5409 0 1 0 1 A3 A2 A1 A0 * ** A0, A1, A2 and A3 correspond to pin A0, A1, A2 and A3 of the device. A0, A1, A2 and A3 must compare to its corresponding hard wired input pins. Figure 6. Write Timing BUS ACTIVITY: MASTER SDA LINE S T A R T S SLAVE/DPP ADDRESS Fixed Variable INSTRUCTION BYTE op code Data Register Pot/WCR Address Address DR1 WCR DATA S T O P P A C K A C K A C K 7 Document No. 2010, Rev. I CAT5409 INSTRUCTION AND REGISTER DESCRIPTION SLAVE ADDRESS BYTE The first byte sent to the CAT5409 from the master/ processor is called the Slave/DPP Address Byte. The most significant four bits of the slave address are a device type identifier. These bits for the CAT5409 are fixed at 0101[B] (refer to Table 1). The next four bits, A3 - A0, are the internal slave address and must match the physical device address which is defined by the state of the A3 - A0 input pins for the CAT5409 to successfully continue the command sequence. Only the device which slave address matches the incoming device address sent by the master executes the instruction. The A3 - A0 inputs can be actively driven by CMOS input signals or tied to VCC or VSS. Table 1. Identification Byte Format Device Type Identifier INSTRUCTION BYTE The next byte sent to the CAT5409 contains the instruction and register pointer information. The four most significant bits used provide the instruction opcode I [3:0]. The R1 and R0 bits point to one of the four data registers of each associated potentiometer. The least two significant bits point to one of four Wiper Control Registers. The format is shown in Table 2. Data Register Selection Data Register Selected DR0 DR1 DR2 DR3 R1 0 0 1 1 R0 0 1 0 1 Slave Address ID3 0 (MSB) ID2 1 ID1 0 ID0 1 A3 A2 A1 A0 (LSB) Table 2. Instruction Byte Format Instruction Opcode Data Register Selection WCR/Pot Selection I3 (MSB) I2 I1 I0 R1 R0 P1 P0 (LSB) Document No. 2010, Rev. I 8 CAT5409 WIPER CONTROL AND DATA REGISTERS Wiper Control Register (WCR) The CAT5409 contains four 6-bit Wiper Control Registers, one for each potentiometer. The Wiper Control Register output is decoded to select one of 64 switches along its resistor array. The contents of the WCR can be altered in four ways: it may be written by the host via Write Wiper Control Register instruction; it may be written by transferring the contents of one of four associated Data Registers via the XFR Data Register instruction, it can be modified one step at a time by the Increment/decrement instruction (see Instruction section for more details). Finally, it is loaded with the content of its data register zero (DR0) upon power-up. The Wiper Control Register is a volatile register that loses its contents when the CAT5409 is powered-down. Although the register is automatically loaded with the value in DR0 upon power-up, this may be different from the value present at power-down. Data Registers (DR) Each potentiometer has four 6-bit non-volatile Data Registers. These can be read or written directly by the host. Data can also be transferred between any of the Table 3. Instruction Set Instruction Set Instruction Read Wiper Control Register Write Wiper Control Register Read Data Register Write Data Register XFR Data Register to Wiper Control Register XFR Wiper Control Register to Data Register Global XFR Data Registers to Wiper Control Registers Global XFR Wiper Control Registers to Data Register Increment/Decrement Wiper Control Register Note: 1/0 = data is one or zero I3 I2 I1 I0 R1 R0 four Data Registers and the associated Wiper Control Register. Any data changes in one of the Data Registers is a non-volatile operation and will take a maximum of 5ms. If the application does not require storage of multiple settings for the potentiometer, the Data Registers can be used as standard memory locations for system parameters or user preference data. INSTRUCTIONS Four of the nine instructions are three bytes in length. These instructions are: — Read Wiper Control Register - read the current wiper position of the selected potentiometer in the WCR — Write Wiper Control Register - change current wiper position in the WCR of the selected potentiometer — Read Data Register - read the contents of the selected Data Register — Write Data Register - write a new value to the selected Data Register The basic sequence of the three byte instructions is illustrated in Figure 8. These three-byte instructions WCR1/ P1 WCR0/ P0 Operation Read the contents of the Wiper Control Register pointed to by P1-P0 Write new value to the Wiper Control Register pointed to by P1-P0 Read the contents of the Data Register pointed to by P1-P0 and R1-R0 Write new value to the Data Register pointed to by P1-P0 and R1-R0 Transfer the contents of the Data Register pointed to by P1-P0 and R1-R0 to its associated Wiper Control Register Transfer the contents of the Wiper Control Register pointed to by P1-P0 to the Data Register pointed to by R1-R0 Transfer the contents of the Data Registers pointed to by R1-R0 of all four pots to their respective Wiper Control Register s Transfer the contents of both Wiper Control Registers to their respective data Registers pointed to by R1-R0 of all four pots Enable Increment/decrement of the Control Latch pointed to by P1-P0 1 1 1 1 1 0 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0 0 0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1 1 1 0 1/0 1/0 1/0 1/0 0 0 0 1 1/0 1/0 0 0 1 0 0 0 1/0 1/0 0 0 0 0 1 0 0 0 1/0 1/0 9 Document No. 2010, Rev. I CAT5409 exchange data between the WCR and one of the Data Registers. The WCR controls the position of the wiper. The response of the wiper to this action will be delayed by tWRL. A transfer from the WCR (current wiper position), to a Data Register is a write to non-volatile memory and takes a minimum of tWR to complete. The transfer can occur between one of the four potentiometers and one of its associated registers; or the transfer can occur between all potentiometers and one associated register. Four instructions require a two-byte sequence to complete, as illustrated in Figure 7. These instructions transfer data between the host/processor and the CAT5409; either between the host and one of the data registers or directly between the host and the Wiper Control Register. These instructions are: — XFR Data Register to Wiper Control Register This transfers the contents of one specified Data Register to the associated Wiper Control Register. — XFR Wiper Control Register to Data Register This transfers the contents of the specified Wiper Control Register to the specified associated Data Register. — Global XFR Data Register to Wiper Control Register This transfers the contents of all specified Data Registers to the associated Wiper Control Registers. — Global XFR Wiper Counter Register to Data Register This transfers the contents of all Wiper Control Registers to the specified associated Data Registers. INCREMENT/DECREMENT COMMAND The final command is Increment/Decrement (Figure 5 and 9). The Increment/Decrement command is different from the other commands. Once the command is issued and the CAT5409 has responded with an acknowledge, the master can clock the selected wiper up and/or down in one segment steps; thereby providing a fine tuning capability to the host. For each SCL clock pulse (tHIGH) while SDA is HIGH, the selected wiper will move one resistor segment towards the RH terminal. Similarly, for each SCL clock pulse while SDA is LOW, the selected wiper will move one resistor segment towards the RL terminal. See Instructions format for more detail. Figure 7. Two-Byte Instruction Sequence SDA 0 1 0 1 A I3 C K I2 I1 I0 R1 R0 P1 P0 Register Address A C K Pot/WCR Address S T O P S ID3 ID2 ID1 ID0 A3 A2 A1 A0 T A Internal R Device ID Address T Instruction Opcode Figure 8. Three-Byte Instruction Sequence SDA 0 1 0 1 A2 A0 A I3 C K Internal Address A1 I2 I1 I0 R1 R0 P1 P0 A C K Data Pot/WCR Register Address Address D7 D6 D5 D4 D3 D2 D1 D0 WCR[7:0] or Data Register D[7:0] A C K S T O P S ID3 ID2 ID1 ID0 A3 T A Device ID R T Instruction Opcode Figure 9. Increment/Decrement Instruction Sequence SDA S T A R T 0 1 0 1 A3 A2 A1 A0 Internal Address A C K I3 I2 I1 I0 A C Pot/WCR K Data Address Register Address R1 R0 P1 P0 I N C 1 I N C 2 I N C n D E C 1 D E C n S T O P ID3 ID2 ID1 ID0 Device ID Instruction Opcode Document No. 2010, Rev. I 10 CAT5409 Figure 10. Increment/Decrement Timing Limits INC/DEC Command Issued SCL tWRID SDA RW Voltage Out INSTRUCTION FORMAT Read Wiper Control Register (WCR) S T A R T DEVICE ADDRESSES 0 1 0 1 A3 A2 A1 A0 A C K A C 1 0 0 1 0 0 P1 P0 K INSTRUCTION DATA 76 00 5 43 210 A C K S T O P Write Wiper Control Register (WCR) S T A R T DEVICE ADDRESSES 0 1 0 1 A3 A2 A1 A0 A C K A C 1 0 1 0 0 0 P1 P0 K INSTRUCTION DATA 76 00 5 43 210 A C K S T O P Read Data Register (DR) S T A R T A C 0 1 0 1 A3 A2A1 A0 K DEVICE ADDRESS A A DATA C C 1 0 1 1 R1 R0 P1 P0 7 6 5 4 3 210 K K 00 INSTRUCTION S T O P Write Data Register (DR) S T A R T A C 0 1 0 1 A3 A2A1 A0 K DEVICE ADDRESS A A DATA C C 1 1 0 0 R1 R0 P1 P0 7 6 5 4 3 210 K K 00 INSTRUCTION S T O P 11 Document No. 2010, Rev. I CAT5409 INSTRUCTION FORMAT (continued) Global Transfer Data Register (DR) to Wiper Control Register (WCR) S T A R T A C 0 1 0 1 A3 A2 A1 A0 K DEVICE ADDRESS INSTRUCTION 0 0 0 1 R1 R0 0 0 A C K S T O P Global Transfer Wiper Control Register (WCR) to Data Register (DR) S T A R T A C 0 1 0 1 A3 A2 A1 A0 K DEVICE ADDRESS INSTRUCTION 1 0 0 0 R1 R0 0 0 A C K S T O P Transfer Wiper Control Register (WCR) to Data Register (DR) S T A R T A C 0 1 0 1 A3 A2 A1 A0 K DEVICE ADDRESS A C 1 1 1 0 R1 R0 P1 P0 K INSTRUCTION S T O P Transfer Data Register (DR) to Wiper Control Register (WCR) S T A R T A C 0 1 0 1 A3 A2 A1 A0 K DEVICE ADDRESS A C 1 1 0 1 R1 R0 P1 P0 K INSTRUCTION S T O P Increment (I)/Decrement (D) Wiper Control Register (WCR) S T A R T A A INSTRUCTION C C 0 1 0 1 A3 A2 A1 A0 0 0 1 0 0 0 P1 P0 K K DEVICE ADDRESS DATA I/D I/D ••• A C I/D I/D K S T O P Notes: (1) Any write or transfer to the Non-volatile Data Registers is followed by a high voltage cycle after a STOP has been issued. Document No. 2010, Rev. I 12 CAT5409 ORDERING INFORMATION Prefix CAT Device # 5409 Suffix J I -00 -TE13 Optional Company ID Product Number Package J: SOIC B: BGA U: TSSOP W: SOIC (Lead free, Halogen free) Y: TSSOP (Lead free, Halogen free) Tape & Reel TE13: 2000/Reel Resistance -25: 2.5kohm -10: 10kohm -50: 50kohm -00: 100kohm Temperature Range I = Industrial (-40 C to 85 C) Notes: (1) The device used in the above example is a CAT5409JI-00-TE13 (SOIC, Industrial Temperature, 10kohm, Tape & Reel) 13 Document No. 2010, Rev. I CAT5409 PACKAGING INFORMATION 24-LEAD 300 MIL WIDE SOIC (J, W) 0.2914 (7.40) 0.2992 (7.60) 0.394 (10.00) 0.419 (10.65) 0.5985 (15.20) 0.6141 (15.60) 0.0926 (2.35) 0.1043 (2.65) 0.050 (1.27) BSC 0.013 (0.33) 0.020 (0.51) 0.0040 (0.10) 0.0118 (0.30) 0.010 (0.25) X 45 0.029 (0.75) 0.0091 (0.23) 0.0125 (0.32) 0 —8 0.016 (0.40) 0.050 (1.27) Document No. 2010, Rev. I 14 CAT5409 PACKAGING INFORMATION CON'T 24 Lead TSSOP (U, Y) 7.8 + 0.1 -A- 7.72 TYP 6.4 4.4 + 0.1 -B(1.78 TYP) 4.16 TYP 3.2 0.42 TYP 0.65 TYP PIN #1 INDENT. 0.2 C B A ALL LEAD TIPS LAND PATTERN RECOMMENDATION 1.1 MAX TYP 0.1 C ALL LEAD TIPS (0.9) -C0.10 + 0.05 TYP 0.65 TYP 0.19 - 0.30 TYP 0.3 M A B S C S SEE DETAIL A GAGE PLANE 0.09 - 0.20 TYP 0.25 0-8 o o 0.6+0.1 SEATING PLANE DETAIL A 15 Document No. 2010, Rev. I CAT5409 PACKAGING INFORMATION CON'T 24 Ball BGA a 1 A B b C D E F Top View (Bump Side Down) f k a j m 2 3 4 4 3 2 1 A B C D E F b Bottom View (Bump Side Up) Note: Drawing not to scale = Die orientation mark d c e Side View (Bump Side Down) Millimeters Symbol Package Body Dimension X Package Body Dimension Y Package Height Package Body Thickness Ball Height Ball Diameter Total Ball Count Ball Count X Axis Ball Count Y Axis Pins Pitch X Axis Pins Pitch Y Axis Edge to Ball Center (Corner) Distance Along X Edge to Ball Center (Corner) Distance Along Y a b c d e f g h i j k l m Min TBD TBD 0.635 0.433 0.202 0.284 24 4 6 0.5 0.5 TBD TBD TBD TBD TBD TBD TBD TBD Nom TBD TBD 0.505 0.395 0.110 0.180 Max TBD TBD 0.765 0.471 0.294 0.388 Nom TBD TBD 0.02500 0.01705 0.00795 0.01118 Inches Min TBD TBD 0.01988 0.01555 0.00433 0.00709 Max TBD TBD 0.03012 0.01854 0.01157 0.01528 TBD TBD TBD TBD Document No. 2010, Rev. I 16 REVISION HISTORY Date 10/8/2003 3/30/2004 Rev. H I Reason Updated Features Updated Description Changed Preliminary designation to Final Eliminated Commercial temp range in all areas Updated WP Pin Description Updaed notes in Absolute Max Ratings and Potentiometer Characteristics Copyrights, Trademarks and Patents Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: DPP ™ AE2 ™ Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000. 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Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete. Catalyst Semiconductor, Inc. Corporate Headquarters 1250 Borregas Avenue Sunnyvale, CA 94089 Phone: 408.542.1000 Fax: 408.542.1200 www.catalyst-semiconductor.com Publication #: Revison: Issue date: Type: 2010 I 3/30/04 Final