CAT64LC40LTE13

CAT64LC10/20/40 1K/2K/4K-Bit SPI Serial EEPROM FEATURES s SPI bus compatible s Low power CMOS technology s 2.5V to 6.0V operation s Self-timed write cycle with auto-clear s Hardware reset pin s Hardware and software write protection H GEN FR ALO EE LE A D F R E ETM s Commercial, industrial and automotive temperature ranges s Power-up inadvertant write protection s RDY/BSY pin for end-of-write indication s 1,000,000 program/erase cycles s 100 year data retention DESCRIPTION The CAT64LC10/20/40 is a 1K/2K/4K-bit Serial EEPROM which is configured as 64/128/256 registers by 16 bits. Each register can be written (or read) serially by using the DI (or DO) pin. The CAT64LC10/20/40 is manufactured using Catalyst’s advanced CMOS PIN CONFIGURATION DIP Package (P, L) CS SK DI DO 1 2 3 4 8 7 6 5 VCC RDY/BUSY RESET GND PIN FUNCTIONS Pin Name CS SK DI i D DO VCC GND RESET RDY/BUSY c s Reset i t n o RDY/BUSY VCC CS SK 1 2 3 4 8 7 6 5 CS SK DI DO 1 2 3 4 8 7 6 5 SOIC Package (J, W) u n RESET GND DO DI VCC RDY/BUSY RESET GND EEPROM floating gate technology. It is designed to endure 1,000,000 program/erase cycles and has a data retention of 100 years. The device is available in 8-pin DIP, SOIC and TSSOP packages. d e CS SK DI DO 1 2 3 4 RDY/BUSY VCC CS SK 1 2 3 4 VCC a P 8 7 6 5 8 7 6 5 RESET GND DO DI ts r TSSOP Package (U, Y) VCC RDY/BUSY RESET GND SOIC Package (S, V) TSSOP Package (UR, YR) BLOCK DIAGRAM GND Function Chip Select Clock Input Serial Data Input Serial Data Output +2.5V to +6.0V Power Supply Ground DI RESET CS MODE DECODE LOGIC DATA REGISTER OUTPUT BUFFER MEMORY ARRAY 64/128/256 x 16 ADDRESS DECODER SK CLOCK GENERATOR DO RDY/BUSY Ready/BUSY Status 64LC10/20/40 F02 © 2004 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 1 Doc. No. 1021, Rev. C CAT64LC10/20/40 ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias ................. –55°C to +125°C Storage Temperature ....................... –65°C to +150°C Voltage on any Pin with Respect to Ground(1) ............ –2.0V to +VCC +2.0V VCC with Respect to Ground ............... –2.0V to +7.0V Package Power Dissipation Capability (Ta = 25°C) ................................... 1.0W Lead Soldering Temperature (10 secs) ............ 300°C Output Short Circuit Current(2) ........................ 100 mA RELIABILITY CHARACTERISTICS Symbol NEND (3) *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Parameter Endurance Data Retention ESD Susceptibility Latch-Up Min. 1,000,000 100 2000 100 Max. Units Cycles/Byte Years Volts mA Reference Test Method MIL-STD-883, Test Method 1033 MIL-STD-883, Test Method 1008 TDR(3) VZAP(3) ILTH(3)(4) CAPACITANCE (TA = 25°C, f= 1.0 MHz, VCC =6.0V) Symbol CI/O(3) CIN (3) Test Input/Output Capacitance (DO, RDY/BSY) Input Capacitance (CS, SK, DI, RESET) Note: (1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns. (2) Output shorted for no more than one second. No more than one output shorted at a time. (3) This parameter is tested initially and after a design or process change that affects the parameter. (4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V. i D Doc. No. 1021, Rev. C c s i t n o u n d e Max. 8 6 MIL-STD-883, Test Method 3015 JEDEC Standard 17 a P Units pF pF ts r Conditions VI/O = 0V VIN = 0V 2 CAT64LC10/20/40 D.C. OPERATING CHARACTERISTICS VCC = +2.5V to +6.0V, unless otherwise specified. Limits Sym. ICC Parameter Operating Current 2.5V Min. Typ. Max. 0.4 1 2 3 3 2 10 –0.1 VCC x 0.7 –0.1 VCC x 0.8 2.5V 6.0V Units mA mA mA mA µA µA µA V V V V V V V 0.4 0.4 V V IOH = –10µA IOH = –10µA IOH = –400µA IOL = 10µA IOL = 2.1mA Test Conditions fSK = 250 kHz fSK = 1 MHz EWEN, EWDS, READ 6.0V ICCP Program Current 2.5V 6.0V ISB(1) ILI ILO VIL VIH VIL VIH Standby Current Input Leakage Current Output Leakage Current Low Level Input Voltage, DI High Level Input Voltage, DI Low Level Input Voltage, CS, SK, RESET High Level Input Voltage, CS, SK, RESET VOH(1) High Level Output Voltage VOL(1) Low Level Output Voltage Note: (1) VOH and VOL spec applies to READY/BUSY pin also i D c s i t n o 2.5V 6.0V VCC – 0.3 VCC – 0.3 2.4 u n d e VCC + 0.5 VCC x 0.2 VCC + 0.5 VCC x 0.3 a P VIN = GND or VCC CS = VCC VIN = GND to VCC VOUT = GND to VCC ts r 3 Doc. No. 1021, Rev. C CAT64LC10/20/40 A.C. OPERATING CHARACTERISTICS VCC = +2.5V to +6.0V, unless otherwise specified. Limits Symbol tCSS tCSH tDIS tDIH tPD1 tPD0 tHZ(2) tCSMIN tSKHI Parameter CS Setup Time CS Hold Time DI Setup Time DI Hold Time Output Delay to 1 Output Delay to 0 Output Delay to High Impendance Minimum CS High Time Minimum SK High Time 2.5V 4.5V–6.0V tSKLOW Minimum SK Low Time 2.5V 250 Min. 100 100 200 200 Typ. Max. Units ns tSV fSK Output Delay to Status Valid Maximum Clock Frequency tRESS tRESMIN tRESH tRC Reset to CS Setup Time Minimum RESET High Time RESET to READY Hold Time Write Recovery POWER-UP TIMING(1)(3) Symbol tPUR tPUW WRITE CYCLE LIMIITS Symbol tWR Parameter Program Cycle Time 2.5V 4.5V–6.0V Min. Max. 10 5 Units ms i D c s Power-Up to Read Operation Power-Up to Program Operation i t n o Parameter u n 2.5V 4.5V–6.0V 4.5V–6.0V d e 400 1000 400 250 1000 0 250 0 100 Min. 1000 a P 300 500 500 300 ts r ns ns ns ns ns ns ns ns ns ns kHz ns ns ns ns Max. 10 1 Units µs ms Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) This parameter is sampled but not 100% tested. (3) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. Doc. No. 1021, Rev. C 4 CAT64LC10/20/40 INSTRUCTION SET Instruction Read 64LC10 64LC20 64LC40 Write 64LC10 64LC20 64LC40 Write Enable Write Disable [Write All Locations](1) Opcode 10101000 10101000 10101000 10100100 10100100 10100100 10100011 10100000 10100001 Address A5 A4 A3 A2 A1 A0 0 A6 A5 A4 A3 A2 A1 A0 0 0 Data D15 - D0 D15 - D0 D15 - D0 D15 - D0 A7 A6 A5 A4 A3 A2 A1 A0 A5 A4 A3 A2 A1 A0 0 A6 A5 A4 A3 A2 A1 A0 0 0 D15 - D0 D15 - D0 A7 A6 A5 A4 A3 A2 A1 A0 XXXXXXXX XXXXXXXX XXXXXXXX Figure 1. A.C. Testing Input/Output Waveform (2)(3(4) (CL = 100 pF) VCC x 0.8 INPUT PULSE LEVELS VCC x 0.2 VCC x 0.7 Note: (1) (Write All Locations) is a test mode operation and is therefore not included in the A.C./D.C. Operations specifications. (2) Input Rise and Fall Times (10% to 90%) < 10 ns. (3) Input Pulse Levels = VCC x 0.2 and VCC x 0.8. (4) Input and Output Timing Reference = VCC x 0.3 and VCC x 0.7. i D c s i t n o u n VCC x 0.3 d e REFERENCE POINTS a P D15–D0 ts r 5 Doc. No. 1021, Rev. C CAT64LC10/20/40 DEVICE OPERATION The CAT64LC10/20/40 is a 1K/2K/4K-bit nonvolatile memory intended for use with all standard controllers. The CAT64LC10/20/40 is organized in a 64/128/256 x 16 format. All instructions are based on an 8-bit format. There are four 16-bit instructions: READ, WRITE, EWEN, and EWDS. The CAT64LC10/20/40 operates on a single power supply ranging from 2.5V to 6.0V and it has an onchip voltage generator to provide the high voltage needed during a programming operation. Instructions, addresses Figure 2. Sychronous Data Timing and data to be written are clocked into the DI pin on the rising edge of the SK clock. The DO pin is normally in a high impedance state except when outputting data in a READ operation or outputting RDY/BSY status when polled during a WRITE operation. The format for all instructions sent to this device includes a 4-bit start sequence, 1010, a 4-bit op code and an 8bit address field or dummy bits. For a WRITE operation, RESET tRESS SK tDIS DI tCSS CS tCSH tDIH tSKLOW tSKHI DO tRC RDY/BUSY Figure 3. Read Instruction Timing RESET i D SK CS DI DO RDY/BUSY Doc. No. 1021, Rev. C c s 1 0 1 0 i t n o tRESH u n tPD0,tPD1 tHZ d e tCSMIN a P tSV tSV ts r 1 0 0 0 ADDRESS* D15 D14 HIGH D1 D0 * Please check the instruction set table for address 6 CAT64LC10/20/40 a 16-bit data field is also required following the 8-bit address field. The CAT64LC10/20/40 requires an active LOW CS in order to be selected. Each instruction must be preceded by a HIGH-to-LOW transition of CS before the input of the 4-bit start sequence. Prior to the 4-bit start sequence (1010), the device will ignore inputs of all other logical sequence. Read Upon receiving a READ command and address (clocked into the DI pin), the DO pin will output data one tPD after the falling edge of the 16th clock (the last bit of the address field). The READ operation is not affected by the RESET input. Write After receiving a WRITE op code, address and data, the device goes into the AUTO-Clear cycle and then the Figure 4. Write Instruction Timing RESET SK CS DI 1 0 1 0 0 1 0 0 DO RDY/BUSY * Please check instruction set table for address Figure 5. Ready/BUSY Status Instruction Timing RESET i D SK CS DI DO RDY/BUSY c s LOW HIGH i t n o u n ADDRESS* d e D15 D0 a P ts r WRITE INSTRUCTION NEXT INSTRUCTION 7 Doc. No. 1021, Rev. C CAT64LC10/20/40 WRITE cycle. The RDY/BSY pin will output the BUSY status (LOW) one tSV after the rising edge of the 32nd clock (the last data bit) and will stay LOW until the write cycle is complete. Then it will output a logical “1” until the next WRITE cycle. The RDY/BSY output is not affected by the input of CS. An alternative to get RDY/BSY status is from the DO pin. During a write cycle, asserting a LOW input to the CS pin will cause the DO pin to output the RDY/BSY status. Bringing CS HIGH will bring the DO pin back to a high impedance state again. After the device has completed a WRITE cycle, the DO pin will output a logical “1” when the device is deselected. The rising edge of the first “1” input on the DI pin will reset DO back to the high impedance state again. The WRITE operation can be halted anywhere in the operation by the RESET input. If a RESET pulse occurs during a WRITE operation, the device will abort the operation and output a READY status. NOTE: Data may be corrupted if a RESET occurs while the device is BUSY. If the reset occurs before the BUSY period, no writing will be initiated. However, if RESET occurs after the BUSY period, new data will have been written over the old data. Figure 6. RESET During BUSY Instruction Timing BUSY RESET SK CS DI 1 0 1 DO RDY/BUSY * Please check instruction set table for address Figure 7. EWEN Instruction Timing i D RESET SK CS DI DO RDY/BUSY Doc. No. 1021, Rev. C c s 1 0 1 0 i t n o 0 0 1 1 HIGH-Z HIGH 0 0 1 0 0 u n ADDRESS* D15 d e D0 a P ts r tWR 5064 FHD F09 8 CAT64LC10/20/40 RESET The RESET pin, when set to HIGH, will reset or abort a WRITE operation. When RESET is set to HIGH while the WRITE instruction is being entered, the device will not execute the WRITE instruction and will keep DO in HighZ condition. When RESET is set to HIGH, while the device is in a clear/write cycle, the device will abort the operation and will display READY status on the RDY/BSY pin and on the DO pin if CS is low. The RESET input affects only the WRITE and WRITE ALL operations. It does not reset any other operations such as READ, EWEN and EWDS. Figure 8. EWDS Instruction Timing RESET ERASE/WRITE ENABLE and DISABLE The CAT64LC10/20/40 powers up in the erase/write disabled state. After power-up or while the device is in an erase/write disabled state, any write operation must be preceded by an execution of the EWEN instruction. Once enabled, the device will stay enabled until an EWDS has been executed or a power-down has occured. The EWDS is used to prevent any inadvertent overwriting of the data. The EWEN and EWDS instructions have no affect on the READ operation and are not affected by the RESET input. SK CS DI 1 0 DO RDY/BUSY i D c s i t n o 1 0 0 0 0 0 HIGH-Z HIGH u n d e a P ts r 9 Doc. No. 1021, Rev. C CAT64LC10/20/40 ORDERING INFORMATION P: PDIP S: SOIC (JEDEC) J: SOIC (JEDEC) U: TSSOP UR: TSSOP (Rotated) L: PDIP (Lead free, Halogen free) V: SOIC (JEDEC) (Lead free, Halogen free) W: SOIC (JEDEC) (Lead free, Halogen free) Y: TSSOP (Lead free, Halogen free) YR: TSSOP (Rotated) (Lead free, Halogen free) Notes: (1) The device used in the above example is a 64LC10SI-TE13 (SOIC, Industrial Temperature, Tape & Reel) i D Doc. No. 1021, Rev. C c s i t n o u n d e a P ts r 10 CAT64LC10/20/40 PACKAGING INFORMATION 8-LEAD TSSOP (U) 3.0 + 0.1 -A8 5 7.72 TYP 6.4 4.4 + 0.1 -B(1.78 TYP) 3.2 4.16 TYP 0.42 TYP 0.2 C B A 1 PIN #1 IDENT. 4 ALL LEAD TIPS 1.1 MAX TYP 0.1 C ALL LEAD TIPS -C- 0.65 TYP i D c s i t n o (0.9) 0.19 - 0.30 TYP 0.3 M A B S C S 0.10 + 0.05 TYP u n 0 o- 8 o d e 0.6+0.1 0.65 TYP LAND PATTERN RECOMMENDATION a P SEE DETAIL A ts r 0.09 - 0.20 TYP GAGE PLANE 0.25 SEATING PLANE DETAIL A 11 Doc. No. 1021, Rev. C CAT64LC10/20/40 REVISION HISTORY Date 9/3/2004 11/17/2004 Rev. B C Reason Added Green packages in all areas Updated DC Operating Characteristics table & notes Changed ISB from 1µA, Max to 3µA, Max in DC Operating Characteristics table Copyrights, Trademarks and Patents Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: DPP ™ AE2 ™ Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000. CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES. Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur. Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete. Catalyst Semiconductor, Inc. Corporate Headquarters 1250 Borregas Avenue Sunnyvale, CA 94089 Phone: 408.542.1000 Fax: 408.542.1200 www.catalyst-semiconductor.com i D c s i t n o u n d e a P ts r Publication #: Revison: Issue date: 1021 C 11/3/04 Doc. No. 1021, Rev. C 12