CAT93C46RVI-G2

CAT93C46R 1-Kb Microwire Serial EEPROM FEATURES I High speed operation: 4MHz @ 5V, 2MHz @ 1.8V I 1.8V to 5.5V supply voltage range I Selectable x8 or x16 memory organization I Sequential read I Software write protection I Power-up inadvertent write protection I Low power CMOS technology I 1,000,000 program/erase cycles I 100 year data retention I Industrial temperature range I RoHS-compliant 8-pin PDIP, SOIC, TSSOP and DESCRIPTION The CAT93C46R is a 1-Kb CMOS Serial EEPROM device which is organized as either 64 registers of 16 bits or 128 registers of 8 bits, as determined by the state of the ORG pin. The CAT93C46R features sequential read and self-timed internal write with autoclear. On-chip Power-On Reset circuitry protects the internal logic against powering up in the wrong state. In contrast to the CAT93C46, the CAT93C46R features an internal instruction clock counter which provides improved noise immunity for Write/Erase commands. 8-pad TDFN packages PIN CONFIGURATION PDIP (L) SOIC (V, X) TSSOP (Y) TDFN (VP2) CS SK DI DO 1 2 3 4 8 7 6 5 VCC NC ORG GND NC VCC CS SK FUNCTIONAL SYMBOL VCC SOIC (W) 1 2 3 4 8 7 6 5 ORG GND DO DI ORG CS SK DI CAT93C46R DO GND PIN FUNCTIONS Pin Name CS SK DI DO VCC GND ORG NC Function Chip Select Clock Input Serial Data Input Serial Data Output Power Supply Ground Memory Organization No Connection For Ordering Information details, see page 12. Note: When the ORG pin is connected to VCC, the x16 organization is selected. When it is connected to ground, the x8 pin is selected. If the ORG pin is left unconnected, then an internal pull-up device will select the x16 organization. * The Green & Gold seal identifies RoHS-compliant packaging, using NiPdAu pre-plated lead frames. © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 1 Doc. No. 1107, Rev. F CAT93C46R ABSOLUTE MAXIMUM RATINGS (1) Storage Temperature Voltage on Any Pin with Respect to Ground (2) -65°C to +150°C -0.5 V to +6.5 V RELIABILITY CHARACTERISTICS (3) Symbol NEND(4) TDR Parameter Endurance Data Retention Min 1,000,000 100 Units Program/ Erase Cycles Years D.C. OPERATING CHARACTERISTICS VCC = +1.8V to +5.5V, unless otherwise specified. Symbol ICC1 ICC2 ISB1 ISB2 ILI ILO VIL1 VIH1 VIL2 VIH2 VOL1 VOH1 VOL2 VOH2 Note: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. (2) The DC input voltage on any pin should not be lower than -0.5V or higher than VCC +0.5V. During transitions, the voltage on any pin may undershoot to no less than -1.5V or overshoot to no more than VCC +1.5V, for periods of less than 20 ns. (3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100 and JEDEC test methods. (4) Block Mode, VCC = 5V, TA = 25°C. Parameter Power Supply Current (Write) Power Supply Current (Read) Power Supply Current (Standby) (x8 Mode) Power Supply Current (Standby) (x16Mode) Input Leakage Current Output Leakage Current (Including ORG pin) Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage Test Conditions fSK = 1MHz VCC = 5.0V fSK = 1MHz VCC = 5.0V CS = 0V ORG = GND CS = 0V ORG = Float or VCC VIN = 0V to VCC VOUT = 0V to VCC, CS = 0V 4.5V ≤ VCC < 5.5V 4.5V ≤ VCC < 5.5V 1.8V ≤ VCC < 4.5V 1.8V ≤ VCC < 4.5V 4.5V ≤ VCC < 5.5V IOL = 2.1mA 4.5V ≤ VCC < 5.5V IOH = -400µA 1.8V ≤ VCC < 4.5V IOL = 1mA 1.8V ≤ VCC < 4.5V IOH = -100µA Min Max 1 500 10 10 2 2 Units mA µA µA µA µA µA V V V V V V -0.1 2 0 VCC x 0.7 0.8 VCC + 1 VCC x 0.2 VCC+1 0.4 2.4 0.2 VCC - 0.2 V V Doc. No. 1107, Rev. F 2 © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT93C46R PIN CAPACITANCE Symbol COUT (1) Test Output Capacitance (DO) Input Capacitance (CS, SK, DI, ORG) Conditions VOUT = 0V VIN = 0V Max 5 5 Units pF pF CIN(1) A.C. CHARACTERISTICS(2) VCC = 1.8V- 5.5V Symbol tCSS tCSH tDIS tDIH tPD1 tPD0 tHZ(1) tEW tCSMIN tSKHI tSKLOW tSV SKMAX Parameter CS Setup Time CS Hold Time DI Setup Time DI Hold Time Output Delay to 1 Output Delay to 0 Output Delay to High-Z Program/Erase Pulse Width Minimum CS Low Time Minimum SK High Time Minimum SK Low Time Output Delay to Status Valid Maximum Clock Frequency DC 0.25 0.25 0.25 0.25 2 DC Min 50 0 100 100 0.25 0.25 100 5 0.1 0.1 0.1 0.1 4 Max VCC = 4.5V- 5.5V Min 50 0 50 50 0.1 0.1 100 5 Max Units ns ns ns ns µs µs ns ms µs µs µs µs MHz POWER-UP TIMING (1)(3) Symbol tPUR tPUW Parameter Power-up to Read Operation Power-up to Write Operation Max 1 1 Units ms ms A.C. TEST CONDITIONS Input Rise and Fall Times Input Pulse Voltages Timing Reference Voltages Input Pulse Voltages Timing Reference Voltages Output Load ≤ 50ns 0.4V to 2.4V 4.5V ≤ VCC ≤ 5.5V 0.8V, 2.0V 4.5V ≤ VCC ≤ 5.5V 0.2VCC to 0.7VCC 1.8V ≤ VCC ≤ 4.5V 0.5VCC 1.8V ≤ VCC ≤ 4.5V Current Source IOLmax/IOHmax; CL = 100pF NOTE: (1) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100 and JEDEC test methods. (2) Test conditions according to “A.C. Test Conditions” table. (3) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 3 Doc No. 1107, Rev. F CAT93C46R INSTRUCTION SET Address Instruction READ ERASE WRITE EWEN E WDS ERAL WRAL Start Bit 1 1 1 1 1 1 1 Opcode 10 11 01 00 00 00 00 x8 A6-A0 A6-A0 A6-A0 11XXXXX 00XXXXX 10XXXXX 01XXXXX Data x8 x16 Comments Read Address AN– A0 Clear Address AN– A0 D7-D0 D15-D0 Write Address AN– A0 Write Enable Write Disable Clear All Addresses D7-D0 D15-D0 Write All Addresses x16 A5-A0 A5-A0 A5-A0 11XXXX 00XXXX 10XXXX 01XXXX DEVICE OPERATION The CAT93C46R is a 1024-bit nonvolatile memory intended for use with industry standard microprocessors. The CAT93C46R can be organized as either registers of 16 bits or 8 bits. When organized as X16, seven 9-bit instructions control the reading, writing and erase operations of the device. When organized as X8, seven 10-bit instructions control the reading, writing and erase operations of the device. The CAT93C46R operates on a single power supply and will generate on chip the high voltage required during any write operation. Instructions, addresses, and write data are clocked into the DI pin on the rising edge of the clock (SK). The DO pin is normally in a high impedance state except when reading data from the device, or when checking the ready/busy status after a write operation. The ready/busy status can be determined after the start of a write operation by selecting the device (CS high) and polling the DO pin; DO low indicates that the write operation is not completed, while DO high indicates that the device is ready for the next instruction. If necessary, the DO pin may be placed back into a high impedance state during chip select by shifting a dummy “1” into the DI pin. The DO pin will enter the high impedance state on the rising edge of the clock (SK). Placing the DO pin into the high impedance state is recommended in applications where the DI pin and the DO pin are to be tied together to form a common DI/O pin. The Ready/Busy flag can be disabled only in Ready state; no change is allowed in Busy state. The format for all instructions sent to the device is a logical "1" start bit, a 2-bit (or 4-bit) opcode, 6-bit address (an additional bit when organized X8) and for write operations a 16-bit data field (8-bit for X8 organization). Read Upon receiving a READ command and an address (clocked into the DI pin), the DO pin of the CAT93C46R will come out of the high impedance state and, after sending an initial dummy zero bit, will begin shifting out the data addressed (MSB first). The output data bits will toggle on the rising edge of the SK clock and are stable after the specified time delay (tPD0 or tPD1). Sequential Read After the 1st data word has been shifted out and CS remains asserted with the SK clock continuing to toggle, the CAT93C46R will automatically increment to the next address and shift out the next data word. As long as CS is continuously asserted and SK continues to toggle, the device will keep incrementing to the next address automatically until it reaches the end of the address space, then loops back to address 0. In the sequential Read mode, only the initial data word is preceeded by a dummy zero bit; all subsequent data words will follow without a dummy zero bit. Erase/Write Enable and Disable The CAT93C46R powers up in the write disable state. Any writing after power-up or after an EWDS (write disable) instruction must first be preceded by the EWEN (write enable) instruction. Once the write instruction is enabled, it will remain enabled until power to the device is removed, or the EWDS instruction is sent. The EWDS instruction can be used to disable all CAT93C46R write and erase instructions, and will prevent any accidental writing or clearing of the device. Data can be read normally from the device regardless of the write enable/ disable status. Doc. No. 1107, Rev. F 4 © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT93C46R Figure 1. Sychronous Data Timing tSKHI SK tDIS DI tCSS CS tDIS DO tPD0,tPD1 DATA VALID tCSMIN VALID VALID tDIH tSKLOW tCSH Figure 2. Read Instruction Timing SK tCSMIN CS STANDBY AN DI 1 1 0 tHZ 0 DN D N— 1 D1 D0 HIGH-Z AN—1 A0 DO HIGH-Z tPD0 Figure 2b. Sequential Read Instruction Timing SK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CS Don't Care AN DI 1 1 0 AN–1 A0 DO HIGH-Z Dummy 0 D15 . . . D0 or D7 . . . D0 Address + 1 D15 . . . D0 or D7 . . . D0 Address + 2 D15 . . . D0 or D7 . . . D0 Address + n D15 . . . or D7 . . . Figure 3. EWEN/EWDS Instruction Timing SK CS STANDBY DI 1 0 0 * * ENABLE=11 DISABLE=00 © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 5 Doc No. 1107, Rev. F CAT93C46R Write After receiving a WRITE command, address and the data, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN (see Design Note for details). The falling edge of CS will start the self clocking clear and data store cycle of the memory location specified in the instruction. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C46R can be determined by selecting the device and polling the DO pin. Since this device features Auto-Clear before write, it is NOT necessary to erase a memory location before it is written into. Erase Upon receiving an ERASE command and address, the CS (Chip Select) pin must be deasserted for a minimum of tCSMIN after the proper number of clock pulses (see Design Note). The falling edge of CS will start the self clocking clear cycle of the selected memory location. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/ busy status of the CAT93C46R can be determined by selecting the device and polling the DO pin. Once cleared, the content of a cleared location returns to a logical “1” state. Erase All Upon receiving an ERAL command, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self clocking clear cycle of all memory locations in the device. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C46R can be determined by selecting the device and polling the DO pin. Once cleared, the contents of all memory bits return to a logical “1” state. Write All Upon receiving a WRAL command and data, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self clocking data write to all memory locations in the device. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. (Note 1.) The ready/ busy status of the CAT93C46R can be determined by selecting the device and polling the DO pin. It is not necessary for all memory locations to be cleared before the WRAL command is executed. Design Note With CAT93C46R, after the last data bit has been sampled, Chip Select (CS) must be brought Low before the next rising edge of the clock(SK) in order to start the slef-timed high voltage cycle. This is important because if the CS is brought low before or after this specific frame window, the addressed location will not be programmed or erased. Figure 4. Write Instruction Timing SK tCS MIN CS AN DI 1 0 1 tSV DO HIGH-Z tEW BUSY READY HIGH-Z tHZ AN-1 A0 DN D0 STATUS VERIFY STANDBY Doc. No. 1107, Rev. F 6 © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT93C46R Figure 5. Erase Instruction Timing SK CS AN DI 1 1 1 tSV HIGH-Z DO AN-1 A0 STATUS VERIFY tCS MIN STANDBY tHZ BUSY tEW READY HIGH-Z Figure 6. ERAL Instruction Timing SK CS STATUS VERIFY tCS MIN STANDBY DI 1 0 0 1 0 tSV tHZ BUSY tEW READY HIGH-Z DO HIGH-Z Figure 7. WRAL Instruction Timing SK CS STATUS VERIFY tCS MIN STANDBY DI 1 0 0 0 1 DN D0 tSV tHZ BUSY tEW READY HIGH-Z DO © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 7 Doc No. 1107, Rev. F CAT93C46R 8-LEAD 300 MIL WIDE PLASTIC DIP (L) E1 E D A2 A A1 L e b2 b eB SYMBOL A A1 A2 b b2 D E E1 e eB L MIN 0.38 3.05 0.36 1.14 9.02 7.62 6.09 7.87 0.115 NOM MAX 4.57 3.81 0.56 1.77 10.16 8.25 7.11 9.65 0.150 24C16_8-LEAD_DIP_(300P).eps 0.46 7.87 6.35 2.54 BSC 0.130 Notes: 1. All dimensions are in millimeters. 2. Complies with JEDEC Standard MS001. 3. Dimensioning and tolerancing per ANSI Y14.5M-1982 Doc. No. 1107, Rev. F 8 © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT93C46R 8-LEAD 150 MIL WIDE SOIC (V, W) E1 E D h x 45 C A θ1 e b A1 L SYMBOL A1 A b C D E E1 e h L θ1 MIN 0.10 1.35 0.33 0.19 4.80 5.80 3.80 NOM MAX 0.25 1.75 0.51 0.25 5.00 6.20 4.00 1.27 BSC 0.25 0.40 0° 0.50 1.27 8° 24C16_8-LEAD_SOIC.eps For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf. Notes: 1. All dimensions are in millimeters. 2. Complies with JEDEC specification MS-012. © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 9 Doc No. 1107, Rev. F CAT93C46R 8-LEAD TSSOP (Y) D 8 5 SEE DETAIL A c E E1 E/2 1 4 GAGE PLANE PIN #1 IDENT. θ1 A2 L 0.25 SEATING PLANE SEE DETAIL A A e b A1 SYMBOL A A1 A2 b c D E E1 e L θ1 MIN 0.05 0.80 0.19 0.09 2.90 6.30 4.30 0.50 0.00 NOM MAX 1.20 0.15 1.05 0.30 0.20 3.10 6.50 4.50 0.75 8.00 0.90 3.00 6.4 4.40 0.65 BSC 0.60 For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf. Notes: 1. All dimensions are in millimeters. 2. Complies with JEDEC Standard MO-153 Doc. No. 1107, Rev. F 10 © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT93C46R 8-PAD TDFN 2X3 PACKAGE (VP2) A E PIN 1 INDEX AREA D A1 A2 A3 D2 SYMBOL A A1 A2 A3 b D D2 E E2 e L MIN 0.70 0.00 0.45 0.20 1.90 1.30 2.90 1.20 0.20 NOM 0.75 0.02 0.55 0.20 REF 0.25 2.00 1.40 3.00 1.30 0.50 TYP 0.30 MAX 0.80 0.05 0.65 0.30 2.10 1.50 3.10 1.40 0.40 b e 3xe E2 PIN 1 ID L For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf. Notes: 1. All dimensions are in millimeters. 2. Complies with JEDEC specification MS-229. TDFN2X3 (03).eps © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 11 Doc No. 1107, Rev. F CAT93C46R ORDERING INFORMATION Prefix CAT Device # 93C46R V Suffix I –G T3 Optional Company ID Product Number 93C46R Temperature Range I = Industrial (-40°C - 85°C) Tape & Reel T: Tape & Reel 2: 2000/Reel(4) 3: 3000/Reel Lead Finish G: NiPdAu L V W X Y VP2 Package = PDIP = SOIC, JEDEC = SOIC, JEDEC = SOIC, EIAJ(4) = TSSOP = TDFN (2X3mm) Notes: (1) All packages are RoHS-compliant (Lead-free, Halogen-free). (2) The standard lead finish is NiPdAu. (3) The device used in the above example is a CAT93C46RVI-GT3 (SOIC, Industrial Temperature, NiPdAu, Tape & Reel). (4) For SOIC, EIAJ (X) package the standard lead finish is Matte-Tin. This package is available in 2000 pcs/reel, i.e. CAT93C46RXI-T2. (5) For additional package and temperature options, please contact your nearest Catalyst Semiconductor Sales office. Doc. No. 1107, Rev. F 12 © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice REVISION HISTORY Date 12/01/05 12/07/05 12/14/05 03/06/06 Revision Comments A Initial Issue B C D Update D.C. Operating Characteristics Update Pin Functions Update Ordering Information Update Features Update Pin Configuration Update A.C. Characteristics Update Device Operation Update Package Dimensions Update Package Marking Update Tape and Reel Update Pin Configuration Update D.C. Operating Characteristics Update A.C. Characteristics Update Device Operation Update Package Marking Update Tape and Reel Update Features Update Description Update Pin Functions Update Functional Symbol Update Absolute Maximum Ratings Update Reliability Characteristics Upadte D.C. Operating Characteristics Update Pin Capacitance Update A.C. Characteristics Update Timing Diagrams Update Package Dimensions Remove Package Marking Update Ordering Information 05/16/06 E 09/11/06 F Copyrights, Trademarks and Patents Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: DPP ™ AE2 ™ MiniPot ™ Quad-Mode ™ Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES. Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur. Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete. Catalyst Semiconductor, Inc. Corporate Headquarters 2975 Stender Way Santa Clara, CA 95054 Phone: 408.542.1000 Fax: 408.542.1200 www.catsemi.com Publication #: Revison: Issue date: 1107 F 09/11/06