CAT93C56LET3E

CAT93C56/57 (Die Rev. E) 2K-Bit Microwire Serial EEPROM FEATURES I High speed operation: 1MHz I Low power CMOS technology I 1.8 to 5.5 volt operation I Selectable x8 or x16 memory organization I Self-timed write cycle with auto-clear I Software write protection I Sequential read H GEN FR ALO EE LE A D F R E ETM I Power-up inadvertant write protection I 1,000,000 Program/erase cycles I 100 year data retention I Commercial, industrial and automotive temperature ranges I RoHS-compliant packages DESCRIPTION The CAT93C56/57 are 2K-bit Serial EEPROM memory devices which are configured as either registers of 16 bits (ORG pin at VCC) or 8 bits (ORG pin at GND). Each register can be written (or read) serially by using the DI (or DO) pin. The CAT93C56/57 are manufactured using Catalyst’s advanced CMOS EEPROM floating gate technology. The devices are designed to endure 1,000,000 program/erase cycles and has a data retention of 100 years. The devices are available in 8-pin DIP, SOIC, TSSOP and 8-pad TDFN packages. PIN CONFIGURATION DIP Package (L) CS SK DI DO 1 2 3 4 8 7 6 5 VCC NC ORG GND FUNCTIONAL SYMBOL SOIC Package (W) NC VCC CS SK 1 2 3 4 8 7 6 5 ORG GND DO DI VCC ORG CS SK DI DO SOIC Package (V) CS SK DI DO 1 2 3 4 8 7 6 5 VCC NC ORG GND CS SK DI DO SOIC Package (X) 1 2 3 4 8 7 6 5 VCC NC ORG GND GND PIN FUNCTIONS Pin Name Function Chip Select Clock Input Serial Data Input Serial Data Output Power Supply Ground Memory Organization No Connection CS SK DI DO VCC GND ORG TSSOP Package (Y) CS SK DI DO 1 2 3 4 8 7 6 5 VCC NC ORG GND TDFN Package (ZD4) VCC 8 NC 7 ORG 6 GND 5 1 CS 2 SK 3 DI 4 DO Bottom View For Ordering Information details, see page 8. NC Note: When the ORG pin is connected to VCC, the x16 organization is selected. When it is connected to ground, the x8 pin is selected. If the ORG pin is left unconnected, then an internal pullup device will select the x16 organization. © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice. Doc. No. 1088, Rev. O CAT93C56/57 ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias .................. -55°C to +125°C Storage Temperature ........................ -65°C to +150°C Voltage on any Pin with Respect to Ground(1) ............. -2.0V to +VCC +2.0V VCC with Respect to Ground ................ -2.0V to +7.0V Package Power Dissipation Capability (TA = 25°C) ................................... 1.0W Lead Soldering Temperature (10 secs) ............ 300°C Output Short Circuit Current(2) ........................ 100 mA RELIABILITY CHARACTERISTICS Symbol NEND(3) TDR(3) VZAP(3) ILTH(3)(4) Parameter Endurance Data Retention ESD Susceptibility Latch-Up Reference Test Method MIL-STD-883, Test Method 1033 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 3015 JEDEC Standard 17 Min 1,000,000 100 2000 100 Typ Max Units Cycles/Byte Years Volts mA *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. D.C. OPERATING CHARACTERISTICS VCC = +1.8V to +5.5V, unless otherwise specified. Symbol ICC1 ICC2 ISB1 ISB2 ILI ILO VIL1 VIH1 VIL2 VIH2 VOL1 VOH1 VOL2 VOH2 Parameter Power Supply Current (Write) Power Supply Current (Read) Power Supply Current (Standby) (x8 Mode) Power Supply Current (Standby) (x16Mode) Input Leakage Current Output Leakage Current (Including ORG pin) Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage Test Conditions fSK = 1MHz VCC = 5.0V fSK = 1MHz VCC = 5.0V CS = 0V ORG=GND CS=0V ORG=Float or VCC VIN = 0V to VCC VOUT = 0V to VCC, CS = 0V 4.5V ≤ VCC < 5.5V 4.5V ≤ VCC < 5.5V 1.8V ≤ VCC < 4.5V 1.8V ≤ VCC < 4.5V 4.5V ≤ VCC < 5.5V IOL = 2.1mA 4.5V ≤ VCC < 5.5V IOH = -400µA 1.8V ≤ VCC < 4.5V IOL = 1mA 1.8V ≤ VCC < 4.5V IOH = -100µA VCC - 0.2 2.4 0.2 -0.1 2 0 VCC x 0.7 0 Min Typ Max 3 500 10 10 1 1 0.8 VCC + 1 VCC x 0.2 VCC+1 0.4 Units mA µA µA µA µA µA V V V V V V V V Note: (1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns. (2) Output shorted for no more than one second. No more than one output shorted at a time. (3) This parameter is tested initially and after a design or process change that affects the parameter. (4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V. Doc. No. 1088, Rev. O 2 CAT93C56/57 PIN CAPACITANCE Symbol COUT CIN (2) (2) Test Output Capacitance (DO) Input Capacitance (CS, SK, DI, ORG) Conditions VOUT=0V VIN=0V Min Typ Max 5 5 Units pF pF INSTRUCTION SET Instruction READ ERASE WRITE EWEN EWDS ERAL WRAL Device Type 93C56(1) 93C57 93C56(1) 93C57 93C56(1) 93C57 93C56(1) 93C57 93C56(1) 93C57 93C56(1) 93C57 93C56(1) 93C57 Start Bit 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Address Opcode 10 10 11 11 01 01 00 00 00 00 00 00 00 00 x8 A8-A0 A7-A0 A8-A0 A7-A0 A8-A0 A7-A0 11XXXXXXX 11XXXXXX 00XXXXXXX 00XXXXXX 10XXXXXXX 10XXXXXX 01XXXXXXX 01XXXXXX Data x8 x16 Comments Read Address AN– A0 Clear Address AN– A0 D7-D0 D7-D0 D15-D0 Write Address AN– A0 D15-D0 Write Enable Write Disable Clear All Addresses D7-D0 D7-D0 D15-D0 Write All Addresses D15-D0 x16 A7-A0 A6-A0 A7-A0 A6-A0 A7-A0 A6-A0 11XXXXXX 11XXXXX 00XXXXXX 00XXXXX 10XXXXXX 10XXXXX 01XXXXXX 01XXXXX A.C. CHARACTERISTICS Limits VCC = 1.8V-5.5V Symbol tCSS tCSH tDIS tDIH tPD1 tPD0 tHZ(1) tEW tCSMIN tSKHI tSKLOW tSV SKMAX Parameter CS Setup Time CS Hold Time DI Setup Time DI Hold Time Output Delay to 1 Output Delay to 0 Output Delay to High-Z Program/Erase Pulse Width Minimum CS Low Time Minimum SK High Time Minimum SK Low Time Output Delay to Status Valid Maximum Clock Frequency DC 1 1 1 1 250 DC CL = 100pF (3) Test Conditions Min 200 0 400 400 1 1 400 10 0.5 0.5 0.5 0.5 500 DC Max VCC = 2.5V-5.5V Min 100 0 200 200 0.5 0.5 200 10 0.25 0.25 0.25 0.25 1000 Max VCC = 4.5V-5.5V Min 50 0 100 100 0.25 0.25 100 10 Max Units ns ns ns ns µs µs ns ms µs µs µs µs kHz Note: (1) Address bit A8 for 256x8 ORG and A7 for 128x16 ORG are "Don't Care" bits, but must be kept at either a "1" or "0" for READ, WRITE and ERASE commands. (2) This parameter is tested initially and after a design or process change that affects the parameter. 3 Doc. No. 1088, Rev. O CAT93C56/57 POWER-UP TIMING (1)(2) Symbol tPUR tPUW Parameter Power-up to Read Operation Power-up to Write Operation Max 1 1 Units ms ms A.C. TEST CONDITIONS Input Rise and Fall Times Input Pulse Voltages Timing Reference Voltages Input Pulse Voltages Timing Reference Voltages ≤ 50ns 0.4V to 2.4V 0.8V, 2.0V 0.2VCC to 0.7VCC 0.5VCC 4.5V ≤ VCC ≤ 5.5V 4.5V ≤ VCC ≤ 5.5V 1.8V ≤ VCC ≤ 4.5V 1.8V ≤ VCC ≤ 4.5V NOTE: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. (3) The input levels and timing reference points are shown in “AC Test Conditions” table. DEVICE OPERATION The CAT93C56/57 is a 2048-bit nonvolatile memory intended for use with industry standard microprocessors. The CAT93C56/57 can be organized as either registers of 16 bits or 8 bits. When organized as X16, seven 10-bit instructions for 93C57; seven 11-bit instructions for 93C56 control the reading, writing and erase operations of the device. When organized as X8, seven 11-bit instructions for 93C57; seven 12-bit instructions for 93C56 control the reading, writing and erase operations of the device. The CAT93C56/57 operates on a single power supply and will generate on chip, the high voltage required during any write operation. Instructions, addresses, and write data are clocked into the DI pin on the rising edge of the clock (SK). The DO pin is normally in a high impedance state except when reading data from the device, or when checking the ready/busy status after a write operation. The ready/busy status can be determined after the start of a write operation by selecting the device (CS high) and polling the DO pin; DO low indicates that the write operation is not completed, while DO high indicates that the device is ready for the next instruction. If necessary, the DO pin may be placed back into a high impedance state during chip select by shifting a dummy “1” into the DI pin. The DO pin will enter the high impedance state on the falling edge of the clock (SK). Placing the DO pin into the high impedance state is recommended in applications where the DI pin and the 4 DO pin are to be tied together to form a common DI/O pin. The format for all instructions sent to the device is a logical "1" start bit, a 2-bit (or 4-bit) opcode, 7-bit address (93C57)/ 8-bit address (93C56) (an additional bit when organized X8) and for write operations a 16-bit data field (8-bit for X8 organizations). Read Upon receiving a READ command and an address (clocked into the DI pin), the DO pin of the CAT93C56/ 57 will come out of the high impedance state and, after sending an initial dummy zero bit, will begin shifting out the data addressed (MSB first). The output data bits will toggle on the rising edge of the SK clock and are stable after the specified time delay (tPD0 or tPD1). Write After receiving a WRITE command, address and the data, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self clocking clear and data store cycle of the memory location specified in the instruction. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C56/57 can be determined by selecting the device and polling the DO pin. Since this device features AutoClear before write, it is NOT necessary to erase a memory location before it is written into. Doc. No. 1088, Rev. O CAT93C56/57 Figure 1. Sychronous Data Timing tSKHI SK tDIS DI tCSS CS tDIS DO tPD0,tPD1 DATA VALID tCSMIN VALID VALID tDIH tSKLOW tCSH Figure 2. Read Instruction Timing SK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CS Don't Care AN DI 1 1 0 AN–1 A0 DO HIGH-Z Dummy 0 D15 . . . D0 or D7 . . . D0 Address + 1 D15 . . . D0 or D 7 . . . D0 Address + 2 D15 . . . D0 or D 7 . . . D0 Address + n D15 . . . or D7 . . . Figure 3. Write Instruction Timing SK tCSMIN CS AN DI 1 0 1 tSV DO HIGH-Z tEW BUSY READY HIGH-Z tHZ AN-1 A0 DN D0 STATUS VERIFY STANDBY 5 Doc. No. 1088, Rev. O CAT93C56/57 Erase Upon receiving an ERASE command and address, the CS (Chip Select) pin must be deasserted for a minimum of tCSMIN. The falling edge of CS will start the self clocking clear cycle of the selected memory location. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C56/57 can be determined by selecting the device and polling the DO pin. Once cleared, the content of a cleared location returns to a logical “1” state. Erase/Write Enable and Disable The CAT93C56/57 powers up in the write disable state. Any writing after power-up or after an EWDS (write disable) instruction must first be preceded by the EWEN (write enable) instruction. Once the write instruction is enabled, it will remain enabled until power to the device is removed, or the EWDS instruction is sent. The EWDS instruction can be used to disable all CAT93C56/57 write and clear instructions, and will prevent any accidental writing or clearing of the device. Data can be read normally from the device regardless of the write enable/disable status. Erase All Upon receiving an ERAL command, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self clocking clear cycle of all memory locations in the device. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C56/57 can be determined by selecting the device and polling the DO pin. Once cleared, the contents of all memory bits return to a logical “1” state. Write All Upon receiving a WRAL command and data, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self clocking data write to all memory locations in the device. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C56/57 can be determined by selecting the device and polling the DO pin. It is not necessary for all memory locations to be cleared before the WRAL command is executed. Figure 4. Erase Instruction Timing SK CS AN DI 1 1 1 tSV HIGH-Z DO AN-1 A0 STATUS VERIFY tCS STANDBY tHZ BUSY tEW READY HIGH-Z Doc. No. 1088, Rev. O 6 CAT93C56/57 Figure 5. EWEN/EWDS Instruction Timing SK CS STANDBY DI 1 0 0 * * ENABLE=11 DISABLE=00 Figure 6. ERAL Instruction Timing SK CS STATUS VERIFY tCS STANDBY DI 1 0 0 1 0 tSV tHZ BUSY tEW READY HIGH-Z DO HIGH-Z Figure 7. WRAL Instruction Timing SK CS STATUS VERIFY tCSMIN STANDBY DI 1 0 0 0 1 DN D0 tSV tHZ BUSY tEW READY HIGH-Z DO 7 Doc. No. 1088, Rev. O CAT93C56/57 ORDERING INFORMATION Prefix CAT Device # 93C56 Product Number 93C56: 2K 93C57: 2K V Suffix I -1.8 –G T3 Rev E (4) Company ID Temperature Range I = Industrial (-40°C - 85°C) A = Automotive (-40°C - 105°C) E = Extended (-40°C to + 125°C) Package = PDIP = SOIC, JEDEC = SOIC, JEDEC = SOIC, EIAJ(5) = TSSOP = TDFN (3x3mm) Operating Voltage Blank (Vcc = 2.5V to 5.5V) 1.8 (Vcc = 1.8V to 5.5V) Die Revision 93C56: E 93C57: E Tape & Reel T: Tape & Reel 2: 2000/Reel(5) 3: 3000/Reel L V W X Y ZD4 Lead Finish Blank: Matte-Tin G: NiPdAu Notes: (1) All packages are RoHS-compliant (Lead-free, Halogen-free). (2) The standard finish is NiPdAu. (3) The device used in the above example is a CAT93C56VI-1.8-GT3 (SOIC, Industrial Temperature, 1.8V to 5.5V Operating Voltage, NiPdAu, Tape & Reel). (4) Product die revision letter is marked on top of the package as a suffix to the production date code (e.g., AYWWE.) For additional information, please contact your Catalyst sales office. (5) For SOIC, EIAJ (X) package the standard lead finish is Matte-Tin. This package is available in 2000 pcs/reel, i.e. CAT93C56XI-T2. (6) For additional package and temperature options, please contact your nearest Catalyst Semiconductor Sales office. Doc. No. 1088, Rev. O 8 REVISION HISTORY Date 05/14/04 Revision Comments L New Data Sheet Created From CAT93C46/56/57/66/86. Parts CAT93C56, CAT93C56, CAT93C57, CAT93C66, CAT93C76 and CAT93C86 have been separtated into single data sheets Updated Instruction Set Updated Description Update Features Update Pin Configuration Update Functional Symbol Update Pin Functions Update D.C. Operating Characteristics (VCC Range) Update A.C. Characteristics (VCC Range) Update Ordering Informations 10/7/04 03/18/05 10/13/06 M N O Copyrights, Trademarks and Patents Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: DPP ™ AE2 ™ Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000. CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES. Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur. Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete. Catalyst Semiconductor, Inc. Corporate Headquarters 1250 Borregas Avenue Sunnyvale, CA 94089 Phone: 408.542.1000 Fax: 408.542.1200 www.catalyst-semiconductor.com Publication #: Revison: Issue date: 1088 O 10/13/06