CAT93C76

CAT93C76 (Rev. A) 8K-Bit Microwire Serial EEPROM FEATURES High speed operation: 3MHz @ VCC ≥ 2.5V Low power CMOS technology 1.8 to 5.5 volt operation Selectable x8 or x16 memory organization Self-timed write cycle with auto-clear Software write protection Power-up inadvertant write protection 1,000,000 Program/erase cycles 100 year data retention Industrial and extended temperature ranges Sequential read “Green” package option available DESCRIPTION The CAT93C76 is an 8K-bit Serial EEPROM memory device which is configured as either registers of 16 bits (ORG pin at VCC or Not Connected) or 8 bits (ORG pin at GND). Each register can be written (or read) serially by using the DI (or DO) pin. The CAT93C76 is manufactured using Catalyst’s advanced CMOS EEPROM floating gate technology. The device is designed to endure 1,000,000 program/erase cycles and has a data retention of 100 years. The device is available in 8-pin PDIP, SOIC, TSSOP and 8-pad TDFN packages. PIN CONFIGURATION PDIP (L), SOIC (V) TSSOP (Y), TDFN (ZD4) CS SK DI DO 1 2 3 4 8 VCC 7 NC 6 ORG 5 GND FUNCTIONAL SYMBOL VCC ORG CS SK DI DO GND PIN FUNCTION Pin Name CS SK DI DO VCC GND ORG NC Function Chip Select Serial Clock Input Serial Data Input Serial Data Output Power Supply Ground Memory Organization No Connection For Ordering Information details, see page 12. Note: When the ORG pin is connected to VCC, x16 organization is selected. When it is connected to ground, x8 organization is selected. If the ORG pin is left unconnected, then an internal pull-up device will select x16 organization. © Catalyst Semiconductor, Inc. Characteristics subject to change without notice 1 Doc. No. MD-1090 Rev. B CAT93C76 (Rev. A) ABSOLUTE MAXIMUM RATINGS (1) Parameters Temperature Under Bias Storage Temperature Voltage on any Pin with Respect to Ground VCC with Respect to Ground Lead Soldering Temperature (10 seconds) Output Short Circuit Current (3) (2) Ratings –55 to +125 –65 to 150 -2.0 to +VCC +2.0 -2.0 to +7.0 300 100 Units ºC ºC V V ºC mA RELIABILITY CHARACTERISTICS(3) Symbol NEND(4) TDR(4) VZAP(4) ILTH(4)(5) Parameter Endurance Data Retention ESD Susceptibility Latch-Up Reference Test Method MIL-STD-883, Test Method 1033 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 3015 JEDEC Standard 17 Min 1,000,000 100 2000 100 Units Cycles/Byte Years V mA D.C. OPERATING CHARACTERISTICS VCC = +1.8V to +5.5V unless otherwise specified. Symbol ICC1 ICC2 ISB1 ISB2 ILI ILO ILORG VIL1 VIH1 VIL2 VIH2 VOL1 VOH1 VOL2 VOH2 Parameter Power Supply Current (Write) Power Supply Current (Read) Power Supply Current (Standby) (x8 Mode) Power Supply Current (Standby) (x16Mode) Input Leakage Current Output Leakage Current ORG Pin Leakage Current Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage Test Conditions fSK = 1MHz; VCC = 5.0V fSK = 1MHz; VCC = 5.0V CS = 0V ORG = GND CS = 0V ORG = Float or VCC VIN = 0V to VCC VOUT = 0V to VCC, CS = 0V ORG = GND or ORG = VCC 4.5V ≤ VCC ≤ 5.5V 4.5V ≤ VCC ≤ 5.5V 1.8V ≤ VCC < 4.5V 1.8V ≤ VCC < 4.5V 4.5V ≤ VCC ≤ 5.5V; IOL = 2.1mA 4.5V ≤ VCC ≤ 5.5V; IOH = -400µA 1.8V ≤ VCC < 4.5V; IOL = 100µA 1.8V ≤ VCC < 4.5V; IOH = -100µA Min Typ 1 300 2 0(6) 0(6) 0 (6) Max 3 500 10 10 10 10 10 0.8 VCC + 1 VCC x 0.2 VCC + 1 0.4 Units mA µA µA µA µA µA µA V V V V V V V V 1 -0.1 2 0 VCC x 0.7 2.4 0.1 VCC - 0.2 Notes: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. (2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20ns. (3) Output shorted for no more than one second. (4) These parameters are tested initially and after a design or process change that affects the parameter. (5) Latch-up protection is provided for stresses up to 100 mA on I/O pins from –1V to VCC +1V. (6) 0µA is defined as less than 900nA. Doc. No. MD-1090 Rev. B 2 © Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT93C76 (Rev. A) PIN CAPACITANCE (1) Symbol COUT CIN Test Output Capacitance (DO) Input Capacitance (CS, SK, DI, ORG) Conditions VOUT = 0V VIN = 0V Min Typ Max 5 5 Units pF pF INSTRUCTION SET (2) Instruction READ ERASE WRITE EWEN EWDS ERAL WRAL Start Bit 1 1 1 1 1 1 1 Address Opcode 10 11 01 00 00 00 00 x8 A10-A0 A10-A0 A10-A0 11XXXXXXXXX 00XXXXXXXXX 10XXXXXXXXX 01XXXXXXXXX x16 A9-A0 A9-A0 A9-A0 11XXXXXXXX 00XXXXXXXX 10XXXXXXXX 01XXXXXXXX D7-D0 D15-D0 D7-D0 D15-D0 x8 Data x16 Comments Read Address AN– A0 Clear Address AN– A0 Write Address AN– A0 Write Enable Write Disable Clear All Addresses Write All Addresses A.C. CHARACTERISTICS Limits Symbol tCSS tCSH tDIS tDIH tPD1 tPD0 tHZ(1) tEW tCSMIN tSKHI tSKLOW tSV SKMAX Parameter CS Setup Time CS Hold Time DI Setup Time DI Hold Time Output Delay to 1 Output Delay to 0 Output Delay to High-Z Program/Erase Pulse Width Minimum CS Low Time Minimum SK High Time Minimum SK Low Time Output Delay to Status Valid Maximum Clock Frequency (1)(4) Test Conditions VCC = 1.8V - 2.5V Min 100 0 100 100 250 Max VCC = 2.5V - 5.5V Min 50 0 50 50 150 150 100 5 150 150 150 Max Units ns ns ns ns ns ns ns ms ns ns ns 100 DC 3000 ns kHz CL = 100pF (3) 250 150 5 200 250 250 250 DC 1000 POWER-UP TIMING Symbol tPUR tPUW Parameter Power-up to Read Operation Power-up to Write Operation Max 1 1 Units ms ms Notes: (1) These parameters are tested initially and after a design or process change that affects the parameter. (2) Address bit A10 for the 1,024x8 org. and A9 for the 512x16 org. are “don’t care” bits, but must be kept at either a “1” or “0” for READ, WRITE and ERASE commands. (3) The input levels and timing reference points are shown in the “AC Test Conditions” table. (4) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. © Catalyst Semiconductor, Inc. Characteristics subject to change without notice 3 Doc. No. MD-1090 Rev. B CAT93C76 (Rev. A) A.C. TEST CONDITIONS Input Rise and Fall Times Input Pulse Voltages Timing Reference Voltages Input Pulse Voltages Timing Reference Voltages ≤ 50ns 0.4V to 2.4V 0.8V, 2.0V 0.2VCC to 0.7VCC 0.5VCC 4.5V ≤ VCC ≤ 5.5V 4.5V ≤ VCC ≤ 5.5V 1.8V ≤ VCC ≤ 4.5V 1.8V ≤ VCC ≤ 4.5V DEVICE OPERATION The CAT93C76 is a 8192-bit nonvolatile memory intended for use with industry standard microprocessors. The CAT93C76 can be organized as either registers of 16 bits or 8 bits. When organized as X16, seven 13-bit instructions control the read, write and erase operations of the device. When organized as X8, seven 14-bit instructions control the read, write and erase operations of the device. The CAT93C76 operates on a single power supply and will generate on chip, the high voltage required during any write operation. Instructions, addresses, and write data are clocked into the DI pin on the rising edge of the clock (SK). The DO pin is normally in a high impedance state except when reading data from the device, or when checking the ready/busy status after a write operation. The ready/busy status can be determined after the start of a write operation by selecting the device (CS high) and polling the DO pin; DO low indicates that the write operation is not completed, while DO high indicates that the device is ready for the next instruction. If necessary, the DO pin may be placed back into a high impedance state during chip select by shifting a dummy “1” into the DI pin. The DO pin will enter the high impedance state on the falling edge of the clock (SK). Placing the DO pin into the high impedance state is recommended in applications where the DI pin and the DO pin are to be tied together to form a common DI/O pin. The format for all instructions sent to the device is a logical "1" start bit, a 2-bit (or 4-bit) opcode, 10-bit address (an additional bit when organized X8) and for write operations a 16-bit data field (8-bit for X8 organizations). The most significant bit of the address is “don’t care” but it must be present. Read Upon receiving a READ command and an address (clocked into the DI pin), the DO pin of the CAT93C76 will come out of the high impedance state and, after sending an initial dummy zero bit, will begin shifting out the data addressed (MSB first). The output data bits will toggle on the rising edge of the SK clock and are stable after the specified time delay (tPD0 or tPD1). For the CAT93C76, after the initial data word has been shifted out and CS remains asserted with the SK clock continuing to toggle, the device will automatically increment to the next address and shift out the next data word in a sequential READ mode. As long as CS is continuously asserted and SK continues to toggle, the device will keep incrementing to the next address automatically until it reaches the end of the address space, then loops back to address 0. In the sequential READ mode, only the initial data word is preceeded by a dummy zero bit. All subsequent data words will follow without a dummy zero bit. Write After receiving a WRITE command, address and the data, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self clocking clear and data store cycle of the memory location specified in the instruction. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C76 can be determined by selecting the device and polling the DO pin. Since this device features Auto-Clear before write, it is NOT necessary to erase a memory location before it is written into. Doc. No. MD-1090 Rev. B 4 © Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT93C76 (Rev. A) Figure 1. Sychronous Data Timing tSKHI SK tDIS DI tCSS CS tDIS DO tPD0,tPD1 DATA VALID tCSMIN VALID VALID tDIH tSKLOW tCSH Figure 2. Read Instruction Timing SK CS Don't Care AN DI 1 1 0 AN-1 A0 DO HIGH-Z Dummy 0 D15 . . . D0 or D7 . . . D0 Address + 1 D15 . . . D0 or D7 . . . D0 Address + 2 D15 . . . D0 or D7 . . . D0 Address + n D15 . . . or D7 . . . Figure 3. Write Instruction Timing SK tCSMIN CS AN DI 1 0 1 tSV DO HIGH-Z tEW BUSY READY tHZ HIGH-Z AN-1 A0 DN D0 STATUS VERIFY STANDBY © Catalyst Semiconductor, Inc. Characteristics subject to change without notice 5 Doc. No. MD-1090 Rev. B CAT93C76 (Rev. A) Erase Upon receiving an ERASE command and address, the CS (Chip Select) pin must be deasserted for a minimum of tCSMIN. The falling edge of CS will start the self clocking clear cycle of the selected memory location. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C76 can be determined by selecting the device and polling the DO pin. Once cleared, the content of a cleared location returns to a logical “1” state. Erase/Write Enable and Disable The CAT93C76 powers up in the write disable state. Any writing after power-up or after an EWDS (write disable) instruction must first be preceded by the EWEN (write enable) instruction. Once the write instruction is enabled, it will remain enabled until power to the device is removed, or the EWDS instruction is sent. The EWDS instruction can be used to disable all CAT93C76 write and clear instructions, and will prevent any accidental writing or clearing of the device. Data can be read normally from the device regardless of the write enable/disable status. Erase All Upon receiving an ERAL command, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self clocking clear cycle of all memory locations in the device. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C76 can be Figure 4. Erase Instruction Timing SK determined by selecting the device and polling the DO pin. Once cleared, the contents of all memory bits return to a logical “1” state. Write All Upon receiving a WRAL command and data, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self clocking data write to all memory locations in the device. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C76 can be determined by selecting the device and polling the DO pin. It is not necessary for all memory locations to be cleared before the WRAL command is executed. Note 1: After the last data bit has been sampled, Chip Select (CS) must be brought Low before the next rising edge of the clock (SK) in order to start the selftimed high voltage cycle. This is important because if CS is brought low before or after this specific frame window, the addressed location will not be programmed or erased. Power-On Reset (POR) The CAT93C76 incorporates Power-On Reset (POR) circuitry which protects the device against malfunctioning while VCC is lower than the recommended operating voltage. The device will power up into a read-only state and will power-down into a reset state when VCC crosses the POR level of ~1.3 V. CS AN DI 1 1 1 tSV AN-1 A0 STATUS VERIFY tCS STANDBY DO HIGH-Z tHZ BUSY tEW READY HIGH-Z Doc. No. MD-1090 Rev. B 6 © Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT93C76 (Rev. A) Figure 5. EWEN/EWDS Instruction Timing SK CS STANDBY DI 1 0 0 * * ENABLE=11 DISABLE=00 Figure 6. ERAL Instruction Timing SK CS STATUS VERIFY tCS STANDBY DI 1 0 0 1 0 tSV tHZ BUSY tEW READY HIGH-Z DO HIGH-Z Figure 7. WRAL Instruction Timing SK CS STATUS VERIFY tCSMIN STANDBY DI 1 0 0 0 1 DN D0 tSV tHZ BUSY tEW READY HIGH-Z DO © Catalyst Semiconductor, Inc. Characteristics subject to change without notice 7 Doc. No. MD-1090 Rev. B CAT93C76 (Rev. A) PACKAGE OUTLINE DRAWING PDIP 8-Lead 300mils (L) (1)(2) SYMBOL MIN NOM MAX A A1 A2 b E1 5.33 0.38 2.92 0.36 1.14 0.20 9.02 7.62 6.10 7.87 2.92 3.30 3.30 0.46 1.52 0.25 9.27 7.87 2.54 BSC 6.35 7.11 10.92 3.80 4.95 0.56 1.78 0.36 10.16 8.25 b2 c D E e E1 eB PIN # 1 IDENTIFICATION D L TOP VIEW E A A2 A1 b2 L c e SIDE VIEW b eB END VIEW For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf. Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-001. Doc. No. MD-1090 Rev. B 8 © Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT93C76 (Rev. A) SOIC 8-Lead 150mils (V) (1)(2) SYMBOL MIN NOM MAX A A1 b c E1 E 1.35 0.10 0.33 0.19 4.80 5.80 3.80 1.27 BSC 0.25 0.40 0º 1.75 0.25 0.51 0.25 5.00 6.20 4.00 0.50 1.27 8º D E E1 e h L θ PIN # 1 IDENTIFICATION TOP VIEW D h A1 A θ c e b L END VIEW SIDE VIEW For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf. Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-012. © Catalyst Semiconductor, Inc. Characteristics subject to change without notice 9 Doc. No. MD-1090 Rev. B CAT93C76 (Rev. A) TSSOP 8-Lead (Y) (1)(2) b SYMBOL MIN NOM MAX A A1 A2 b c E1 E 1.20 0.05 0.80 0.19 0.09 2.90 6.30 4.30 3.00 6.40 4.40 0.65 BSC 1.00 REF 0.50 0° 0.60 0.75 8° 0.90 0.15 1.05 0.30 0.20 3.10 6.50 4.50 D E E1 e L L1 θ1 e TOP VIEW D c A2 A θ1 A1 SIDE VIEW L1 END VIEW L For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf. Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-153. Doc. No. MD-1090 Rev. B 10 © Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT93C76 (Rev. A) TDFN 8-Pad 3 x 3mm (ZD4) (1)(2) PIN#1 IDENTIFICATION SYMBOL A A1 A2 A3 b D D2 E E2 e L MIN 0.70 0.00 0.50 0.23 2.90 2.20 2.90 1.40 0.20 NOM 0.75 0.02 0.55 0.20 REF 0.30 3.00 2.30 3.00 1.50 0.65 TYP 0.30 MAX 0.80 0.05 0.60 0.37 3.10 2.40 3.10 1.60 0.40 For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf. Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-229. © Catalyst Semiconductor, Inc. Characteristics subject to change without notice 11 Doc. No. MD-1090 Rev. B CAT93C76 (Rev. A) EXAMPLE OF ORDERING INFORMATION (1) Prefix CAT Company ID Product Number L: V: Y: ZD4: Device # Suffix 93C76 V Package PDIP SOIC, JEDEC TSSOP TDFN (3 x 3mm) I Temperature Range I = Industrial (-40ºC to 85ºC) E = Extended (-40ºC to 125ºC) -G Lead Finish Blank: Matte-Tin G: NiPdAu T3 93C76 Tape & Reel T: Tape & Reel (5) 2: 2000 units/Reel 3: 3000 units/Reel Notes: (1) All packages are RoHS-compliant (Lead-free, Halogen-free). (2) (3) (4) (5) (6) The standard lead finish is NiPdAu. The device used in the above example is a 93C76VI-GT3 (SOIC, Industrial Temperature, NiPdAu, Tape & Reel) Product die revision letter is marked on top of the package as a suffix to the production date code (e.g., AYWWA.) For additional information, please contact your Catalyst sales office. For TDFN 3 x 3mm package Tape and Reel = 2000 pcs/reel, all others = 3000 pcs/reel. For additional package and temperature options, please contact your nearest Catalyst Semiconductor Sales office. 12 © Catalyst Semiconductor, Inc. Characteristics subject to change without notice Doc. No. MD-1090 Rev. B REVISION HISTORY Date 08/11/2004 09/21/2007 Rev. A B Comments Initial Issue Added Package Outline Drawings Updated the Example of Ordering Information Copyrights, Trademarks and Patents © Catalyst Semiconductor, Inc. Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: Beyond Memory™, DPP™, EZDim™, LDD™, MiniPot™ and Quad-Mode™ Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. 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Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete. Catalyst Semiconductor, Inc. Corporate Headquarters 2975 Stender Way Santa Clara, CA 95054 Phone: 408.542.1000 Fax: 408.542.1200 www.catsemi.com Document No: MD-1090 Revision: B Issue date: 09/21/07