CAT93C86WA-1.8-GT3

CAT93C86 (Die Rev. C) 16K-Bit Microwire Serial EEPROM FEATURES I High speed operation: 3MHz I Low power CMOS technology I 1.8 to 5.5 volt operation I Selectable x8 or x16 memory organization I Self-timed write cycle with auto-clear I Hardware and software write protection I Power-up inadvertant write protection I Sequential read I Program enable (PE) pin I 1,000,000 Program/erase cycles I 100 year data retention H GEN FR ALO EE LE A D F R E ETM I Commercial, industrial and automotive temperature ranges I RoHS-compliant packages DESCRIPTION The CAT93C86 is a 16K-bit Serial EEPROM memory device which is configured as either registers of 16 bits (ORG pin at VCC) or 8 bits (ORG pin at GND). Each register can be written (or read) serially by using the DI (or DO) pin. The CAT93C86 is manufactured using Catalyst’s advanced CMOS EEPROM floating gate technology. The device is designed to endure 1,000,000 program/erase cycles and has a data retention of 100 years. The device is available in 8-pin DIP, 8-pin SOIC and 8-pad TDFN packages. PIN CONFIGURATION DIP Package (L) CS SK DI DO 1 2 3 4 8 7 6 5 VCC PE ORG GND FUNCTIONAL SYMBOL SOIC Package (W) VCC PE VCC CS SK 1 2 3 4 8 7 6 5 ORG GND DO DI ORG CS SK PE DI DO SOIC Package (V) CS SK DI DO 1 2 3 4 8 7 6 5 VCC PE ORG GND CS SK DI DO SOIC Package (X) 1 2 3 4 8 7 6 5 VCC PE ORG GND GND PIN FUNCTIONS Pin Name CS Function Chip Select Clock Input Serial Data Input Serial Data Output Power Supply Ground Memory Organization Program Enable TDFN Package (ZD4) CS SK DI DO 1 2 3 4 8 7 6 5 SK DI VCC PE ORG GND DO VCC GND ORG Top View PE For Ordering Information details, see page 12. Note: When the ORG pin is connected to VCC, the x16 organization is selected. When it is connected to ground, the x8 pin is selected. If the ORG pin is left unconnected, then an internal pullup device will select the x16 organization. © Catalyst Semiconductor, Inc. Characteristics subject to change without notice. Doc. No. 1091, Rev. O CAT93C86 ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias .................. -55°C to +125°C Storage Temperature ........................ -65°C to +150°C Voltage on any Pin with Respect to Ground(1) ............. -2.0V to +VCC +2.0V VCC with Respect to Ground ................ -2.0V to +7.0V Package Power Dissipation Capability (TA = 25°C) ................................... 1.0W Lead Soldering Temperature (10 secs) ............ 300°C Output Short Circuit Current(2) ........................ 100 mA RELIABILITY CHARACTERISTICS Symbol NEND(3) TDR(3) VZAP(3) ILTH(3)(4) Parameter Endurance Data Retention ESD Susceptibility Latch-Up Reference Test Method MIL-STD-883, Test Method 1033 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 3015 JEDEC Standard 17 Min 1,000,000 100 2000 100 Typ Max Units Cycles/Byte Years Volts mA *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. D.C. OPERATING CHARACTERISTICS VCC = +1.8V to +5.5V, unless otherwise specified. Symbol ICC1 ICC2 ISB1 ISB2 ILI ILO VIL1 VIH1 VIL2 VIH2 VOL1 VOH1 VOL2 VOH2 Parameter Power Supply Current (Write) Power Supply Current (Read) Power Supply Current (Standby) (x8 Mode) Power Supply Current (Standby) (x16Mode) Input Leakage Current Output Leakage Current (Including ORG pin) Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage Test Conditions fSK = 1MHz VCC = 5.0V fSK = 1MHz VCC = 5.0V CS = 0V ORG=GND CS=0V ORG=Float or VCC VIN = 0V to VCC VOUT = 0V to VCC, CS = 0V 4.5V ≤ VCC < 5.5V 4.5V ≤ VCC < 5.5V 1.8V ≤ VCC < 4.5V 1.8V ≤ VCC < 4.5V 4.5V ≤ VCC < 5.5V IOL = 2.1mA 4.5V ≤ VCC < 5.5V IOH = -400µA 1.8V ≤ VCC < 4.5V IOL = 1mA 1.8V ≤ VCC < 4.5V IOH = -100µA VCC - 0.2 2.4 0.2 -0.1 2 0 VCC x 0.7 0 Min Typ Max 3 500 10 10 1 1 0.8 VCC + 1 VCC x 0.2 VCC+1 0.4 Units mA µA µA µA µA µA V V V V V V V V Note: (1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns. (2) Output shorted for no more than one second. No more than one output shorted at a time. (3) This parameter is tested initially and after a design or process change that affects the parameter. (4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V. Doc. No. 1091, Rev. O 2 CAT93C86 PIN CAPACITANCE Symbol COUT (1) Test Output Capacitance (DO) Input Capacitance (CS, SK, DI, ORG) Conditions VOUT=0V VIN=0V Min Typ Max 5 5 Units pF pF CIN(1) INSTRUCTION SET Start Bit 1 1 1 1 1 1 1 Address Opcode 10 11 01 00 00 00 00 x8 A10-A0 A10-A0 A10-A0 11XXXXXXXXX 00XXXXXXXXX 10XXXXXXXXX 01XXXXXXXXX Data x16 A9-A0 A9-A0 A9-A0 D7-D0 x8 x16 Comments Read Address AN– A0 Clear Address AN– A0 D15-D0 Write Address AN– A0 Write Enable Write Disable Clear All Addresses D7-D0 D15-D0 Write All Addresses Instruction READ ERASE WRITE EWEN EWDS ERAL WRAL 11XXXXXXXX 00XXXXXXXX 10XXXXXXXX 01XXXXXXXX A.C. CHARACTERISTICS Limits VCC = 1.8V-5.5V Symbol tCSS tCSH tDIS tDIH tPD1 tPD0 tHZ(1) tEW tCSMIN tSKHI tSKLOW tSV SKMAX Parameter CS Setup Time CS Hold Time DI Setup Time DI Hold Time Output Delay to 1 Output Delay to 0 Output Delay to High-Z Program/Erase Pulse Width Minimum CS Low Time Minimum SK High Time Minimum SK Low Time Output Delay to Status Valid Maximum Clock Frequency DC 1 1 1 1 500 DC CL = 100pF (3) Test Conditions Min 200 0 200 200 1 1 400 5 0.5 0.5 0.5 0.5 1000 DC Max VCC = 2.5V-5.5V Min 100 0 100 100 0.5 0.5 200 5 0.15 0.15 0.15 0.1 3000 Max VCC = 4.5V-5.5V Min 50 0 50 50 0.15 0.15 100 5 Max Units ns ns ns ns µs µs ns ms µs µs µs µs kHz 3 Doc. No. 1091, Rev. O CAT93C86 POWER-UP TIMING (1)(2) Symbol tPUR tPUW Parameter Power-up to Read Operation Power-up to Write Operation Max 1 1 Units ms ms A.C. TEST CONDITIONS Input Rise and Fall Times Input Pulse Voltages Timing Reference Voltages Input Pulse Voltages Timing Reference Voltages ≤ 50ns 0.4V to 2.4V 0.8V, 2.0V 0.2VCC to 0.7VCC 0.5VCC 4.5V ≤ VCC ≤ 5.5V 4.5V ≤ VCC ≤ 5.5V 1.8V ≤ VCC ≤ 4.5V 1.8V ≤ VCC ≤ 4.5V NOTE: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. (3) The input levels and timing reference points are shown in “AC Test Conditions” table. DEVICE OPERATION The CAT93C86 is a 16,384-bit nonvolatile memory intended for use with industry standard microprocessors. The CAT93C86 can be organized as either registers of 16 bits or 8 bits. When organized as X16, seven 13-bit instructions control the reading, writing and erase operations of the device. When organized as X8, seven 14-bit instructions control the reading, writing and erase operations of the device. The CAT93C86 operates on a single power supply and will generate on chip, the high voltage required during any write operation. Instructions, addresses, and write data are clocked into the DI pin on the rising edge of the clock (SK). The DO pin is normally in a high impedance state except when reading data from the device, or when checking the ready/busy status after a write operation. The ready/busy status can be determined after the start of a write operation by selecting the device (CS high) and polling the DO pin; DO low indicates that the write operation is not completed, while DO high indicates that the device is ready for the next instruction. If necessary, the DO pin may be placed back into a high impedance state during chip select by shifting a dummy “1” into the DI pin. The DO pin will enter the high impedance state on the falling edge of the clock (SK). Placing the DO pin into the high impedance state is recommended in applications where the DI pin and the DO pin are to be tied together to form a common DI/O pin. The format for all instructions sent to the device is a logical "1" start bit, a 2-bit (or 4-bit) opcode, 10-bit address (an additional bit when organized X8) and for write operations a 16-bit data field (8-bit for X8 organizations). Enabled mode. For Write Enable and Write Disable instruction PE=don’t care. Read Upon receiving a READ command and an address (clocked into the DI pin), the DO pin of the CAT93C86 will come out of the high impedance state and, after sending an initial dummy zero bit, will begin shifting out the data addressed (MSB first). The output data bits will toggle on the rising edge of the SK clock and are stable after the specified time delay (tPD0 or tPD1). After the initial data word has been shifted out and CS remains asserted with the SK clock continuing to toggle, the device will automatically increment to the next address and shift out the next data word in a sequential READ mode. As long as CS is continuously asserted and SK continues to toggle, the device will keep incrementing to the next address automatically until it reaches to the end of the address space, then loops back to address 0. In the sequential READ mode, only the initial data word is preceeded by a dummy zero bit. All subsequent data words will follow without a dummy zero bit. Write After receiving a WRITE command, address and the data, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self clocking clear and data store cycle of the memory location specified in the instruction. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C86 can be determined by selecting the device and polling the DO pin. Since this device features AutoClear before write, it is NOT necessary to erase a memory location before it is written into. Note: The Write, Erase, Write all and Erase all instructions require PE=1. If PE is left floating, 93C86 is in Program Doc. No. 1091, Rev. O 4 CAT93C86 Figure 1. Sychronous Data Timing tSKHI SK tDIS DI tCSS CS tDIS DO tPD0,tPD1 DATA VALID tCSMIN VALID VALID tDIH tSKLOW tCSH Figure 2. Read Instruction Timing SK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CS Don't Care AN DI 1 1 0 AN–1 A0 DO HIGH-Z Dummy 0 D15 . . . D0 or D7 . . . D0 Address + 1 D15 . . . D0 or D 7 . . . D0 Address + 2 D15 . . . D0 or D 7 . . . D0 Address + n D15 . . . or D7 . . . Figure 3. Write Instruction Timing SK tCSMIN CS AN DI 1 0 1 tSV DO HIGH-Z tEW BUSY READY HIGH-Z tHZ AN-1 A0 DN D0 STATUS VERIFY STANDBY 5 Doc. No. 1091, Rev. O CAT93C86 Erase Upon receiving an ERASE command and address, the CS (Chip Select) pin must be deasserted for a minimum of tCSMIN. The falling edge of CS will start the self clocking clear cycle of the selected memory location. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C86 can be determined by selecting the device and polling the DO pin. Once cleared, the content of a cleared location returns to a logical “1” state. Erase/Write Enable and Disable The CAT93C86 powers up in the write disable state. Any writing after power-up or after an EWDS (write disable) instruction must first be preceded by the EWEN (write enable) instruction. Once the write instruction is enabled, it will remain enabled until power to the device is removed, or the EWDS instruction is sent. The EWDS instruction can be used to disable all CAT93C86 write and clear instructions, and will prevent any accidental writing or clearing of the device. Data can be read normally from the device regardless of the write enable/disable status. Erase All Upon receiving an ERAL command, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self clocking clear cycle of all memory locations in the device. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C86 can be determined by selecting the device and polling the DO pin. Once cleared, the contents of all memory bits return to a logical “1” state. Write All Upon receiving a WRAL command and data, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self clocking data write to all memory locations in the device. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C86 can be determined by selecting the device and polling the DO pin. It is not necessary for all memory locations to be cleared before the WRAL command is executed. Figure 4. Erase Instruction Timing SK CS AN DI 1 1 1 tSV HIGH-Z DO AN-1 A0 STATUS VERIFY tCS STANDBY tHZ BUSY tEW READY HIGH-Z Doc. No. 1091, Rev. O 6 CAT93C86 Figure 5. EWEN/EWDS Instruction Timing SK CS STANDBY DI 1 0 0 * * ENABLE=11 DISABLE=00 Figure 6. ERAL Instruction Timing SK CS STATUS VERIFY tCS STANDBY DI 1 0 0 1 0 tSV tHZ BUSY tEW READY HIGH-Z DO HIGH-Z Figure 7. WRAL Instruction Timing SK CS STATUS VERIFY tCSMIN STANDBY DI 1 0 0 0 1 DN D0 tSV tHZ BUSY tEW READY HIGH-Z DO 7 Doc. No. 1091, Rev. O CAT93C86 8-LEAD 300 MIL WIDE PLASTIC DIP (L) E1 E D A2 A A1 L e b2 b eB SYMBOL A A1 A2 b b2 D E E1 e eB L MIN 0.38 3.05 0.36 1.14 9.02 7.62 6.17 7.87 2.79 NOM MAX 4.57 3.81 0.56 1.52 10.16 8.26 7.49 9.65 3.81 8-Lead_DIP_(300).eps 0.46 7.87 6.35 2.54 BSC For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf. Notes: 1. All dimensions are in millimeters. 2. Complies with JEDEC Standard MS001. 3. Dimensioning and tolerancing per ANSI Y14.5M-1982 Doc. No. 1091, Rev. O 8 CAT93C86 8-LEAD 150 MIL WIDE SOIC (V, W) E1 E D h x 45 C A θ1 e b A1 L SYMBOL A1 A b C D E E1 e h L θ1 MIN 0.10 1.35 0.33 0.19 4.80 5.80 3.80 NOM MAX 0.25 1.75 0.51 0.25 5.00 6.20 4.00 1.27 BSC 0.25 0.40 0° 0.50 1.27 8° 24C16_8-LEAD_SOIC.eps For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf. Notes: 1. All dimensions are in millimeters. 2. Complies with JEDEC specification MS-012. 9 Doc. No. 1091, Rev. O CAT93C86 8-LEAD 208 MIL SOIC (X) E b D A e A1 L c θ1 SYMBOL A1 A b c D E E1 e L θ1 MIN 0.05 0.36 0.19 5.13 7.75 5.13 NOM MAX 0.25 2.03 0.48 0.25 5.33 8.26 5.38 1.27 BSC 0.51 0° 0.76 8° For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf. Notes: 1. All dimensions are in millimeters. 2. Complies with EIAJ specification EDR-7320. Doc. No. 1091, Rev. O 10 CAT93C86 8-PAD TDFN 3X3 PACKAGE (ZD4) A E PIN 1 INDEX AREA D A1 A2 A3 D2 SYMBOL A A1 A2 A3 b D D2 E E2 e L MIN 0.70 0.00 0.45 0.25 2.90 2.20 2.90 1.40 0.20 NOM 0.75 0.02 0.55 0.20 REF 0.30 3.00 2.30 3.00 1.50 0.65 TYP 0.30 MAX 0.80 0.05 0.65 0.35 3.10 2.40 3.10 1.60 b e 3xe E2 PIN 1 ID L 0.40 For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf. Notes: 1. All dimensions are in millimeters. 2. Complies with JEDEC specification MO-229C. TDFN 8-Lead 3x3.eps 11 Doc. No. 1091, Rev. O CAT93C86 ORDERING INFORMATION Prefix CAT Device # 93C86 Product Number 93C86 V Suffix I -1.8 –G T3 Rev C (4) Company ID Temperature Range I = Industrial (-40°C - 85°C) A = Automotive (-40°C - 105°C) E = Extended (-40°C to + 125°C) Package = PDIP = SOIC, JEDEC = SOIC, JEDEC = SOIC, EIAJ(5) = TDFN (3x3mm) Operating Voltage Blank (V = 2.5V to 5.5V) cc 1.8 (V = 1.8V to 5.5V) cc Die Revision 93C86: C Tape & Reel T: Tape & Reel 2: 2000/Reel(5) 3: 3000/Reel L V W X ZD4 Lead Finish Blank: Matte-Tin G: NiPdAu Notes: (1) All packages are RoHS-compliant (Lead-free, Halogen-free). (2) The standard finish is NiPdAu. (3) The device used in the above example is a CAT93C86VI-1.8-GT3 (SOIC, Industrial Temperature, 1.8V to 5.5V Operating Voltage, NiPdAu, Tape & Reel). (4) Product die revision letter is marked on top of the package as a suffix to the production date code (e.g., AYWWE.) For additional information, please contact your Catalyst sales office. (5) For SOIC, EIAJ (X) package the standard lead finish is Matte-Tin. This package is available in 2000 pcs/reel, i.e. CAT93C86XI-T2. (6) For additional package and temperature options, please contact your nearest Catalyst Semiconductor Sales office. Doc. No. 1091, Rev. O 12 REVISION HISTORY Date 05/14/04 Revision Comments L New Data Sheet Created From CAT93C46/56/57/66/86. Parts CAT93C56, CAT93C56, CAT93C57, CAT93C66, CAT93C76 and CAT93C86 have been separtated into single data sheets Add Die Revision ID Letter Update Features Update Description Update Pin Condition Add Functional Diagram Update Pin Function Update D.C. Operating Characteristics Update Pin Capacitance Update Instruction Set Update Device Operation Update Ordering Information Added TDFN Package pin out minor changes Update Features Update Pin Configuration Update Pin Functions Update D.C. Operating Characteristics (VCC Range) Update A.C. Characteristics (VCC Range) Update Ordering Information 08/10/04 9/3/04 10/13/06 M N O Copyrights, Trademarks and Patents © Catalyst Semiconductor, Inc. Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: Beyond Memory ™, DPP ™, EZDim ™, LDD ™, MiniPot™ and Quad-Mode™ Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000. 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Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete. Catalyst Semiconductor, Inc. Corporate Headquarters 2975 Stender Way Santa Clara, CA 95054 Phone: 408.542.1000 Fax: 408.542.1200 www.catsemi.com Publication #: Revison: Issue date: 1091 O 10/13/06