THC63LVDM83E

THC63LVDM83E_Rev.1.40_E THC63LVDM83E 28bits LVTTL/CMOS to 4ch LVDS Serializer/Transmitter General Description Features The THC63LVDM83E is a general purpose data serializer based on LVDS technology with no overhead for protocol or encoding. The THC63LVDM83E converts 28bits of CMOS/TTL data into 4ch LVDS data stream. The transmitter can be programmed for rising edge or falling edge clocks through a dedicated pin. ･49pin 0.65mm pitch VFBGA Package ･Wide Input clock range: 8-160MHz ･Maximum total throughput 4.48Gbit/s@160MHz ･3.3/2.5/1.8/1.2V voltage logic input ･LVDS swing is reducible by RS-pin to reduce EMI and power consumption. ･PLL requires no external components. ･On chip jitter filtering. ･Spread Spectrum Clock input tolerant. ･Power down mode. ･Input clock triggering edge is selectable by R/F-pin. ･Operates from a Single 3.3V Supply and 110mW(typ.) at 75MHz. Block Diagram RS Normal/Small Swing Level Vref 7 7 28bit Parallel Data Input TB0-6 TC0-6 7 7 TD0-6 Clock Input (8 – 160MHz) CLKIN Multi-Level LVTTL/CMOS Input Buffer TA0-6 7:1 Serializer TA+ 7:1 Serializer TB+ 7:1 Serializer TC+ 7:1 Serializer TD+ PLL TA- TB- 4ch Serial Data Output (56 – 1120Mbps/ch) TC- TD- TCLK+ Clock Output TCLK- (8 - 160MHz) R/F /PDWN Copyright©2020 THine Electronics, Inc. 1 THine Electronics, Inc. THC63LVDM83E_Rev.1.40_E Ball Out TOP VIEW 1 2 3 4 5 6 7 A TA6 TA5 TA4 TA3 TA2 TA1 TA0 B TB4 TD3 TD2 TD1 TD0 TA- TA+ C TB5 TB0 GND VCC RS TB- TB+ D TB6 TB1 GND LVDS VCC LVDS VCC TC- TC+ E TC0 TB2 GND PLL VCC R/F F TC1 TB3 TD4 TD5 TD6 G TC2 TC3 TC4 TC5 TC6 TCLK- TCLK+ TD- TD+ CLKIN /PDWN Pin Description Pin Name TA+, TATB+, TBTC+, TCTD+, TDTCLK+, TCLKTA0 ~ TA6 TB0 ~ TB6 TC0 ~ TC6 TD0 ~ TD6 CLKIN Pin # B7, B6 C7, C6 D7, D6 F7, F6 E7, E6 A7,A6,A5,A4,A3,A2,A1 C2,D2,E2,F2,B1,C1,D1 E1,F1,G1,G2,G3,G4,G5 B5,B4,B3,B2,F3,F4,F5 G6 /PDWN G7 Type LVDS Output 3.3V LVTTL 2.5/1.8/1.2V CMOS Digital Input E5 RS C5 VCC C4 GND LVDS VCC PLL VCC C3,D3,E3 D4,D5 E4 Copyright©2020 THine Electronics, Inc. 4ch Serial Data Output Clock Output 3.3V LVTTL Digital Input R/F Description Analog Input Power 2 28bit Parallel Data Input Clock Input Power Down Control H: Normal operation L: Power Down (All output are Hi-Z.) Input Clock Triggering Edge Select H: Rising edge L: Falling edge Input/output Level Select and 2.5/1.8/1.2V Logic level Reference Voltage Input RS-pin Input Data/Clock Voltage Setting Input Voltage VCC 3.3V 1.25V 2.5V 0.9V 1.8V 0.6V 1.2V GND 3.3V Input Buffer LVDS Output Vref VOD VCC/2 1.25V 350mV 0.9V 0.6V VCC/2 200mV Power Supply Pin for LVTTL/CMOS input and digital circuit. Ground Pins for Common. Power Supply Pins for LVDS Outputs. Power Supply Pin for PLL circuit. THine Electronics, Inc. THC63LVDM83E_Rev.1.40_E Absolute Maximum Ratings Parameter Supply Voltage LVTTL/CMOS and Analog Input Voltage LVDS Transmitter Output Voltage Output Current Junction Temperature Storage Temperature Reflow Peak Temperature Reflow Peak Temperature Time Maximum Power Dissipation @+25C Min -0.3 -0.3 -0.3 -30 -55 - Max +4.0 VCC + 0.3 VCC + 0.3 30 +125 +125 +260 10 1.2 Units V V V mA C C C sec W Recommended Operating Conditions Symbol VCC Ta CLKIN Parameter Min 3.0 0 8 All Supply Voltage Operating Ambient Temperature Clock Frequency Power Consumption Symbol Max 3.6 +70 160 Units V C MHz VCC = 3.0~3.6V, Ta= 0~+70ºC Parameter LVDS Transmitter Operating Current Gray Scale Pattern 16(Fig.1) ITCCW LVDS Transmitter Operating Current Worst Case Pattern(Fig.2) ITCCS Typ 3.3 25 - Conditions RL=100, CL=5pF, f=85MHz RS=VCC, (RS=GND) RL=100, CL=5pF, f=160MHz RS=VCC, (RS=GND) RL=100, CL=5pF, f=85MHz RS=VCC, (RS=GND) RL=100, CL=5pF, f=160MHz RS=VCC, (RS=GND) Typ* 42 (34) 58 (50) 45 (36) 63 (55) Max Units - mA - mA - 10 LVDS Transmitter Power Down Current 67 (56) 92 (80) mA mA µA *Typ values are at VCC=3.3V, Ta = +25ºC CLKIN f TA0,TB1,TC2 f/16 TA1,TB2,TC3 f/8 TA2,TB3,TC4 f/4 TA3,TB4,TC5 f/2 TA4-TA6,TB0,TB5,TB6 TC0,TC1,TC6,TD0 – TD2 Steady State Low TD3 – TD6 Steady State High Figure 1. 16 Grayscale Pattern CLKIN f Tx0 – Tx6 f/2 X=A,B,C,D Figure 2. Worst Case Pattern Copyright©2020 THine Electronics, Inc. 3 THine Electronics, Inc. THC63LVDM83E_Rev.1.40_E LVTTL/CMOS DC Specifications Over recommended operating supply and temperature ranges unless otherwise specified. Symbol VIH VIL IINC Parameter Conditions 3.3V LVTTL Vref =VCC/2 2.5/1.8/1.2V CMOS Vref = RS Input Voltage 3.3V LVTTL Vref =VCC/2 2.5/1.8/1.2V CMOS Vref = RS Input Voltage GND  VIN  VCC High Level Input Voltage Low Level Input Voltage Input Current Min Typ Max 2.0 - VCC Vref +0.1 - VCC GND - 0.8 GND - - - Units V Vref -0.1 10 V A *Typ values are at VCC=3.3V, Ta = +25ºC. VCC VIH.max 2.4V VOH(*EIAJ) 2.0V VIH.min VCC/2 Vref 0.8V VIL.max 0.4V VOL(*EIAJ) GND VCC 2.3V VOH(*EIAJ) 1.7V 1.35V 1.25V VIH(*EIAJ) VIH.min Vref 1.15V VIL.max 0.7V 0.2V GND VIL.min VIH.max VCC VIL(*EIAJ) VCC 1.2V VOH(*EIAJ) 0.825V 1.07V 1.0V 0.9V VIH(*EIAJ) VIH.min Vref 0.715V 0.7V 0.6V 0.5V 0.455V 0.325V GND 0.8V 0.68V 0.45V GND VOL(*EIAJ) VIL.min VIH.max VIL.max VIL(*EIAJ) VOL(*EIAJ) VIL.min VIH.max VIH(*EIAJ) VIH(*EIAJ) VIH.min Vref VIL.max VIL(*EIAJ) VOL(*EIAJ) VIL.min 3.3V LVTTL RS=VCC or GND 2.5V CMOS RS=1.25V 1.8V CMOS RS=0.9V 1.2V CMOS RS=0.6V (*EIAJ ED-5001A Normal Range) (*EIAJ ED-5002A Normal Range) (*EIAJ ED-5003A Normal Range) (*EIAJ ED-5005A Normal Range) Figure 3. LVTTL/CMOS Digital Input Compatibility Copyright©2020 THine Electronics, Inc. 4 THine Electronics, Inc. THC63LVDM83E_Rev.1.40_E LVDS DC Specifications Over recommended operating supply and temperature ranges unless otherwise specified. Symbol VOD ∆VOD Parameter Differential Output Voltage IOS Change in VOD between complementary output states Common Mode Voltage Change in VOC between complementary output states Output Short Circuit Current IOZ Output TRI-STATE Current VOC ∆VOC Conditions RS=VCC, 0.6 ~ 1.4V RL=100Ω RS=GND RL=100Ω Min Typ Max Units 250 350 450 mV 120 200 300 mV RL=100Ω - - 35 mV RL=100Ω 1.125 1.25 1.375 V RL=100Ω - - 35 mV VOUT=GND, RL=100Ω /PDWN=GND, VOUT=GND to VCC - - -24 mA - - 10 A *Typ values are at VCC=3.3V, Ta = +25ºC. Tn- Single VOC VOD Tn+ VOD Differential Tn Vdiff=(Tn+)-(Tn-) 0V VOD n=0,1 n=A,B,C,D,CLK Figure 4. LVDS DC Specifications Copyright©2020 THine Electronics, Inc. 5 THine Electronics, Inc. THC63LVDM83E_Rev.1.40_E LVTTL/CMOS AC Specifications Over recommended operating supply and temperature ranges unless otherwise specified. Symbol tTCIT tTCP tTCH tTCL tTCD tTS tTH Parameter CLKIN Transition Time CLKIN Period CLKIN High Time CLKIN Low Time CLKIN to TCLK+/- Delay Tx0-6 Setup time to CLKIN Tx0-6 Hold time to CLKIN Min 6.25 0.35T 0.35T 2.0 0.0 Typ T 0.5T 0.5T 3T - Max 5.0 125 0.65T 0.65T - Units ns ns ns ns ns ns ns *Typ values are at VCC=3.3V, Ta = +25ºC 90% 90% 10% 10% tTCIT tTCIT Figure 5. CLKIN Transmission Time tTCP tTCH tTCL R/F = H CLKIN* Vref Vref Vref R/F = L tTS Tx0-6 X=A,B,C,D Vref tTH Vref Figure 6. LVTTL/CMOS Input Timings Copyright©2020 THine Electronics, Inc. 6 THine Electronics, Inc. THC63LVDM83E_Rev.1.40_E LVDS AC Specifications Over recommended operating supply and temperature ranges unless otherwise specified. Symbol tLVT tTOP1 tTop0 tTop6 tTop5 tTop4 tTop3 tTop2 Parameter LVDS Transition Time Output Data Position0 (T=6.25ns ~ 20ns) Output Data Position1 (T=6.25ns ~ 20ns) Output Data Position2 (T=6.25ns ~ 20ns) Output Data Position3 (T=6.25ns ~ 20ns) Output Data Position4 (T=6.25ns ~ 20ns) Output Data Position5 (T=6.25ns ~ 20ns) Output Data Position6 (T=6.25ns ~ 20ns) Min -0.15 T/7-0.15 2T/7-0.15 3T/7-0.15 4T/7-0.15 5T/7-0.15 6T/7-0.15 Typ 0.6 0.0 T/7 2T/7 3T/7 4T/7 5T/7 6T/7 Max 1.5 +0.15 T/7+0.15 2T/7+0.15 3T/7+0.15 4T/7+0.15 5T/7+0.15 6T/7+0.15 Units ns ns ns ns ns ns ns ns *Typ values are at VCC=3.3V, Ta = +25ºC Vdiff = (TA+) – (TA-) TA+ 5pF 80% 90% Vdiff 100Ω 20% TA- 10% tLVT tLVT Figure 7. LVDS Output Load and Transmission Time TCLK 0V 0V (Differential) tTOP2 max tTOP2 min tTOP3 max tTOP3 min tTOP4 max tTOP4 min tTOP5 max tTOP5 min tTOP6 max tTOP6 min tTOP0 max tTOP0 min tTOP1 max tTOP1 min Tx+/(Single) VOC Tx1 Tx0 Tx6 Tx5 Tx4 Tx3 Tx2 Tx1 Tx0 Tx6 X=A,B,C,D Previous Cycle Next Cycle Figure 8. LVDS Output Data Position Copyright©2020 THine Electronics, Inc. 7 THine Electronics, Inc. THC63LVDM83E_Rev.1.40_E Input to Output AC Specifications Over recommended operating supply and temperature ranges unless otherwise specified. Symbol tTCD tTPLL Parameter CLKIN to TCLK+/- Delay Phase Lock Loop Set Min - Typ 3T - Max 10.0 Units ns ms *Typ values are at VCC=3.3V, Ta = +25ºC R/F = H Vref CLKIN R/F = L tTCD TCLKVOC TCLK+ Figure 9. CLKIN to TCLK+/- Delay VCC 3V Min.0sec CLKIN 2V Min.0sec /PDWN 2V tTPLL TCLK Vdiff=0V Figure 10. PLL Set Time Copyright©2020 THine Electronics, Inc. 8 THine Electronics, Inc. THC63LVDM83E_Rev.1.40_E Board Layout Example TOP VIEW 1 2 3 4 5 6 7 A TA6 TA5 TA4 TA3 TA2 TA1 TA0 A B TB4 TD3 TD2 TD1 TD0 TA- TA+ B C TB5 TB0 GND VCC RS TB- TB+ C D TB6 TB1 GND LVDS VCC LVDS VCC TC- TC+ D E TC0 TB2 GND PLL VCC R/F TCLK- TCLK+ E F TC1 TB3 TD4 TD5 TD6 TD- TD+ F G TC2 TC3 TC4 TC5 TC6 CLKIN /PDWN G 1 2 3 4 5 6 7 R0 R1 R2 R3 R4 R5 R6 R7 B0 B1 G0 G1 G2 G3 G4 G5 G6 G7 TA6 TA5 TA4 TA3 TA2 TA1 TA0 TB4 TD3 TD2 TD1 TD0 TA- TA+ TB5 TB0 GND VCC RS TB- TB+ TB6 TB1 GND LVDS VCC LVDS VCC TC- TC+ TC0 TB2 GND PLL VCC R/F TCLK- TCLK+ TC1 TB3 TC2 TC3 TD4 TC4 TD5 TC5 TD6 TC6 TDCLKIN TD+ /PWDN B2 B3 B4 B5 B6 B7 Copyright©2020 THine Electronics, Inc. 9 THine Electronics, Inc. THC63LVDM83E_Rev.1.40_E Note 1) Cable Connection and Disconnection Don’t connect and disconnect the LVDS cable, when the power is supplied to the system. 2) GND Connection Connect the each GND of the PCB which THC63LVDM83E and LVDS-Rx on it. reduction to place GND cable as close to LVDS cable as possible. It is better for EMI 3) Multi Drop Connection Multi drop connection is not recommended. TCLK+ THC63LVDM83E LVDS-Rx TCLKLVDS-Rx 4) Asynchronous use Asynchronous using such as following systems are not recommended. CLKOUT DATA IC TCLK+ THC63LVDM83E CLKOUT DATA TCLK- CLKOUT LVDS-Rx IC TCLK+ THC63LVDM83E TCLK- CLKOUT DATA IC LVDS-Rx DATA TCLK+ THC63LVDM83E CLKOUT DATA DATA TCLKTCLK+ THC63LVDM83E IC TCLK- Package Copyright©2020 THine Electronics, Inc. 10 THine Electronics, Inc. THC63LVDM83E_Rev.1.40_E PIN A1 CORNER TOP VIEW 1 2 3 4 5 6 7 A B C D E F G 5.0 BOTTOM VIEW PIN A1 CORNER Φ0.3 7 6 5 4 3 2 1 A B C D E F G 3.90 SIDE VIEW Unit : mm 0.3 Copyright©2020 THine Electronics, Inc. 11 THine Electronics, Inc. THC63LVDM83E_Rev.1.40_E Notices and Requests 1. The product specifications described in this material are subject to change without prior notice. 2. The circuit diagrams described in this material are examples of the application which may not always apply to the customer's design. THine Electronics, Inc. (“THine”) is not responsible for possible errors and omissions in this material. Please note even if errors or omissions should be found in this material, THine may not be able to correct them immediately. 3. This material contains THine’s copyright, know-how or other proprietary. Copying or disclosing to third parties the contents of this material without THine’s prior permission is prohibited. 4. Note that even if infringement of any third party's industrial ownership should occur by using this product, THine will be exempted from the responsibility unless it directly relates to the production process or functions of the product. 5. Product Application 5.1 Application of this product is intended for and limited to the following applications: audio-video device, office automation device, communication device, consumer electronics, smartphone, feature phone, and amusement machine device. This product must not be used for applications that require extremely high-reliability/safety such as aerospace device, traffic device, transportation device, nuclear power control device, combustion chamber device, medical device related to critical care, or any kind of safety device. 5.2 This product is not intended to be used as an automotive part, unless the product is specified as a product conforming to the demands and specifications of IATF16949 ("the Specified Product") in this data sheet. THine accepts no liability whatsoever for any product other than the Specified Product for it not conforming to the aforementioned demands and specifications. 5.3 THine accepts liability for demands and specifications of the Specified Product only to the extent that the user and THine have been previously and explicitly agreed to each other. 6. Despite our utmost efforts to improve the quality and reliability of the product, faults will occur with a certain small probability, which is inevitable to a semi-conductor product. Therefore, you are encouraged to have sufficiently redundant or error preventive design applied to the use of the product so as not to have our product cause any social or public damage. 7. Please note that this product is not designed to be radiation-proof. Copyright©2020 THine Electronics, Inc. 12 THine Electronics, Inc. THC63LVDM83E_Rev.1.40_E 8. Testing and other quality control techniques are used to this product to the extent THine deems necessary to support warranty for performance of this product. Except where mandated by applicable law or deemed necessary by THine based on the user’s request, testing of all functions and performance of the product is not necessarily performed. 9. Customers are asked, if required, to judge by themselves if this product falls under the category of strategic goods under the Foreign Exchange and Foreign Trade Act. 10. The product or peripheral parts may be damaged by a surge in voltage over the absolute maximum ratings or malfunction, if pins of the product are shorted by such as foreign substance. The damages may cause a smoking and ignition. Therefore, you are encouraged to implement safety measures by adding protection devices, such as fuses. THine Electronics, Inc. sales@thine.co.jp Copyright©2020 THine Electronics, Inc. 13 THine Electronics, Inc.