THCV219_Rev.2.40_E
THCV219
V-by-One® HS High-speed video data transmitter
General Description
Features
THCV219 is designed to support video data
transmission between the host and display.
One high-speed lane can carry up to 32bit data and
3 bits of synchronizing signals at a pixel clock
frequency from 7.5MHz to 75MHz.
It has one high-speed data lane and, maximum
serial data rate is 3.0Gbps/lane.
Width Link
TTL Clock Freq.
24bit
Si/So
10MHz to 100MHz
32bit
Si/So
7.5MHz to 75MHz
Si/So : Single-in/Single-out,
Color depth selectable: 24(8*3)/32(10*3)bit
Single Link
AC coupling for high speed lines
Wide Range Supply Voltage 2.3~3.6V
Package: 64 pin QFN
Wide frequency range
Spread Spectrum Clocking tolerant
Up to 30kHz/0.5% (center spread)
V-by-One® HS standard Version1.4 compliant
AEC-Q100 ESD Protection
Block Diagram
COL
LFSEL
BET
PDN
RF
CMLDRV
PRE
AVCC
Serializer
TXp
TXn
PLL
Formatter
R9-R0
G9-G0
B9-B0
CONT2,CONT1
HSYNC
VSYNC
DE
ASYNDE
CLKIN
CMOS Input
THCV219
Controls
LDO
HTPDN
LOCKN
CAPOUT
CAPINA
VCC
CAPINP
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THCV219_Rev.2.40_E
Contents Page
General Description................................................................................................................................................. 1
Features ................................................................................................................................................................... 1
Block Diagram ........................................................................................................................................................ 1
Pin Configuration .................................................................................................................................................... 3
Pin Description ........................................................................................................................................................ 4
Functional Description ............................................................................................................................................ 5
Absolute Maximum Ratings* ................................................................................................................................ 10
Recommended Operating Conditions.................................................................................................................... 10
Supply Current ...................................................................................................................................................... 10
Electrical Specifications ........................................................................................................................................ 11
AC Timing Diagrams and Test Circuits................................................................................................................. 12
Data Mapping ........................................................................................................................................................ 15
Package.................................................................................................................................................................. 16
Notices and Requests............................................................................................................................................. 17
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THCV219_Rev.2.40_E
33 G3
34 B2
35 VCC
36 B3
37 CONT1
38 R0
39 R1
40 G0
41 G1
42 B0
43 B1
44 VCC
45 CLKIN
46 CONT2
47 PDN
48 TEST1
Pin Configuration
LFSEL 49
32 G2
PRE 50
31 R3
THCV219
AVCC 51
TEST2 52
30 R2
29 VCC
CAPOUT 53
28 DE
CAPINP 54
27 VSYNC
CAPINA 55
26 HSYNC
GND 56
25 B9
TXP 57
24 GND
TXN 58
(TOP VIEW)
23 B8
GND 59
65 EXPGND
22 B7
LOCKN 60
21 B6
HTPDN 61
20 B5
BET 62
19 VCC
●
COL 63
18 B4
G8 16
G7 15
VCC 14
G6 13
G5 12
G4 11
GND 10
R9 9
R8 8
R7 7
R6 6
VCC 5
R5 4
R4 3
RF 2
17 G9
ASYNDE 1
CMLDRV 64
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Pin Description
Pin Name
R9-R0
G9-G0
B9-B0
CONT1,2
DE
VSYNC
HSYNC
CLKIN
TXN/P
LOCKN
HTPDN
PDN
PRE
CMLDRV
COL**
LFSEL**
ASYNDE
RF
BET
TEST1
TEST2
CAPOUT
CAPINP
CAPINA
VCC
Pin #
type* Description
9,8,7,6,4,
I3
pixel data inputs
3,31,30,39,38
17,16,15,13,12,
I3
pixel data inputs
11,33,32,41,40
25,23,22,21,20,
I3
pixel data inputs
18,36,34,43,42
37,46
I3
User defined data inputs. Active only in 32bit mode.
28
I3
DE input
27
I3
Vsync input
26
I3
Hsync input
45
I3
Pixel clock input
58,57
CO High-speed CML signal output.
Lock detect input.
60
I3L
Must be connected to Rx LOCKN with a 10kΩ pull-up resistor.
Hot plug detect input.
61
I3L
Must be connected to Rx HTPDN with a 10kΩ pull-up resistor.
Power down input.
47
I3L
H: Normal operation L: Power down
Pre-Emphasis level select input.
50
I3
H : Pre-Emphasis Enable L : Pre-Emphasis Disable
CML Outputs drive strength select input.
64
I3
H : Normal drive strength L : Weak drive strength
Data width setting.
63
I3
H : 24bit L : 32bit
Frequency range setting.
49
I3
H: Low frequency operation L: Normal Operation
Asynchronous DE input.
1
I3
H: Normal operation (ASYNDE function disable)
L: DE input invert operation (ASYNDE function enable)
Input clock triggering edge select input for latching input data
2
I3
H: Rising edge L: Falling edge
Field-BET entry.
62
I3
H : Field BET Operation L : Normal Operation
48
Test pin, must be “L” for normal operation.
52
Test pin, must be “L” for normal operation.
Decoupling capacitor pins.
53
This pin should be connected to external decoupling capacitors.
Recommended Capacitance is 2.2uF
54
Reference Input for PLL circuit.Must be tied CAPOUT.
55
Reference Input for Analog circuit.Must be tied CAPOUT.
5,14,19,29,
PS Digital Power supply Pins
35,44
51
PS Analog Power supply Pin
10,24,56,59
PS Ground Pins
65
PS Exposed Pad Ground
AVCC
GND
EXPGND
*type symbol
I3=3.3v CMOS input, I3L=Low Speed 3.3v CMOS input
CO=CML output, PS=Power Supply
**COL, LFSEL pin
COL pin and/or LFSEL pin level shall not be changed during operation. If ether pin level is changed during operation,
PDN shall be toggled (H-> L -> H) after the change.
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THCV219_Rev.2.40_E
Functional Description
Functional Overview
With V-by-One® HS proprietary encoding scheme and CDR (Clock and Data Recovery) architecture,
THCV219 enables transmission of 8/10 bit RGB, 2bits of user-defined data (CONT), synchronizing signals
HSYNC, VSYNC, and DE by a pair cable with minimal external components.
THCV219 inputs CMOS/TTL data (including video data, CONT, HSYNC, VSYNC, and DE) and serializes
video data and synchronizing signals separately, depending on the polarity of DE. DE is a signal which indicates
whether video or synchronizing data are active. When DE is high, it serializes video data inputs into differential
data streams. And it transmits serialized synchronizing data when DE is low.
THCV219 can operate for a wide range of a serial bit rate from 600Mbps to 3.0Gbps.
It does not need any external frequency reference, such as a crystal oscillator.
Internal Reference Output/Input Function (CAPOUT,CAPINA,CAPINP)
An internal regulator produces the 1.2V (CAPOUT). This 1.2V linear regulator can not supply any other
external loads. Bypass CAPOUT to GND with 2.2uF.
CAPINP supplies reference voltage for internal PLL, and CAPINA supplies reference voltage for any internal
analog circuit. Bypass CAPINP/CAPINA to GND with 0.1uF to remove high frequency noise. CAPOUT,
CAPINA and CAPINP must be tied together.
Analog power supply AVCC is supposed to be stabilized with de-coupling capacitor and series noise filter (for
example, ferrite bead).
THCV219
2.2uF
Power
Supply
AVCC
CAPOUT
0.1uF
CAPINA
0.1uF
CAPINP
Figure 1. Connection of CAPOUT, CAPINA, CAPINP and Decoupling Capacitor
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Data Enable
Figure 2 is the conceptual diagram of the basic operation of the chipset.THCV220 in Figure 2 is an example of
V-by-One® HS Receiver.
There are some requirements for DE. Figure 3 shows the timing diagram of it.
THCV219
THCV220
R/G/B
CONT
1
R/G/B
CONT
0
VSYNC
HSYNC
V,HSYNC
CTL
DE=1, R/G/B,CONT
DE=0, CTL
DE=1, V,HSYNC=Fixed
DE=0, V,HSYNC
DE
CTL are particular assigned bit among R/G/B,CONT
that can carry arbitrary data during DE=0 period.
Figure 2. Conceptual diagram of the basic operation of the chipset
THCV219
Input
tDEH
tDEL
CLKIN
(RF=H)
DE
Low
High
High
Low
Low
High
Valid Data
Invalid
Invalid
Valid Data
Valid Data
Invalid
Valid Data
Valid Data
HSYNC
VSYNC
Invalid
Invalid
Invalid
Valid Data
RGB
CONT
THCV220
Output*
tDEH
tDEL
CLKOUT
(RF=H)
DE
Low
High
High
Low
Low
High
Valid Data
Keep the last data
of DE=L period
Keep the last data
of DE=L period
Valid Data
Valid Data
Keep the last data
of DE=L period
Valid Data
Valid Data
HSYNC
VSYNC
Keep the
last data
Keep the
last data
Keep the
last data
Valid Data
RGB
CONT
Particular assigned bit ‘CTL’ is transmitted expect the first
and last pixel of Blanking period. Ohters are Low fixed.
*Refer to the data sheet of THCV220 for output operation
Figure 3. Data and synchronizing signals transmission timing diagram
Table 1. DE requirement
symbol
tDEH
tDEL
Parameter
DE=High Duration
DE=Low Duration
min.
2tTCIP
2tTCIP
typ.
max.
Unit
sec
sec
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ASYNDE
If ASYNDE input is Low, DE input is inverted before V-by-One® HS processing. RGB/CONT Data is
transmitted during DE input=Low. Please be careful this inverted DE is outputted from V-by-One® HS receiver,
which may cause polarity mismatch against following system requirement.
Color Depth and Frequency Range Select function
The mode selected by the combination of the COL and LFSEL pin settings is shown in Table 2.
The 32bit mode and 24bit mode correspond to the 4Byte mode and 3Byte mode in the V-by-One® HS standard,
respectively.
Low Frequency mode is a THine proprietary feature. To use this mode, a Receiver device with this function
must be used. The Receiver device must also be set to Low Frequency mode.
Table 2. operation mode select
COL
LFSEL
Description
Freq. Range(Hz)
L
32bit
15 to 75M
H
32bit Low frequency mode
7.5 to 30M
L
24bit
20 to 100M
H
24bit Low frequency mode
10 to 40M
L
H
Hot-Plug Function
HTPDN indicates connecting condition between the Transmitter and the Receiver. HTPDN of the transmitter
side is high when the Receiver is not active or not connected. Then Transmitter can enter into the power down
mode. HTPDN is set to Low by the Receiver when Receiver is active and connects to the Transmitter, and then
Transmitter must start up and transmit CDR training pattern for link training. HTPDN is open drain output at the
receiver side. Pull-up resistor is needed at the transmitter side.
HTPDN connection between the Transmitter and the Receiver can be omitted as an application option. In this
case, HTPDN at the Transmitter side should always be taken as Low.
Lock Detect Function
LOCKN indicates whether the CDR PLL is in the lock state or not. LOCKN at the Transmitter input is set to
High by pull-up resistor when Receiver is not active or at the CDR PLL training state. LOCKN is set to Low by
the Receiver when CDR lock is done. Then the CDR training mode finishes and Transmitter shifts to the normal
mode. LOCKN is open drain output at the receiver side. Pull-up resistor is needed at the transmitter side.
When HTPDN is included in an application, the LOCKN signal should only be considered when the HTPDN is
pulled low by the Receiver.
V-by-One®
HS Rx
THCV219
10kΩ
Vcc
(Tx side)
10kΩ
THCV219
10kΩ
Vcc
(Tx side)
V-by-One®
HS Rx
HTPDN
HTPDN
HTPDN
HTPDN
LOCKN
LOCKN
LOCKN
LOCKN
With HTPDN connect
Without HTPDN connect
Figure 4. Hot-plug and Lock detect scheme
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THCV219_Rev.2.40_E
Pre-emphasis and Drive Select Function
Pre-emphasis can equalize severe signal degradation caused by long-distance or high-speed transmission.
The PRE pin selects the strength of pre-emphasis.
CMLDRV controls CML output swing level. See Table 3.
Table 3. Pre-emphasis and Drive Select function table
Description
PRE
CMLDRV
Swing level
L
400mV diff p-p
H
600mV diff p-p
L
400mV diff p-p
6dB
H
600mV diff p-p
3.5dB
L
H
Pre-emphasis
0dB
Power Down Function
Setting the PDN pin low places THCV219 in the power-down mode. Internal circuitry turns off and the TXP/N
outputs turn to High level.
Table 4. Power Down function table
PDN
Description
L
Power Down
H
Normal Operation
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THCV219_Rev.2.40_E
Field BET Operation
In order to help users to check validity of CML high-speed serial line, THCV219 has an operation mode in
which they act as a bit error tester (BET). In this mode, THCV219 internally generates test pattern which is then
serialized onto the CML high-speed line. THCV220 which is an example or Rx device also has BET function
mode. THCV220 receives the data stream and checks bit errors.
This "Field BET" mode is activated by setting BET= H both on THCV219 andTHCV220. The generated data
pattern is then 8b/10b encoded, scrambled, and serialized onto the CML channel. As for THCV220, the internal
test pattern check circuit gets enabled and reports result on a certain pin named BETOUT. The BETOUT pin
goes LOW whenever bit errors occur, or it stays HIGH when there is no bit error. Please refer to Table 5.
Table 5. Field BET operation pin settings
THCV219
THCV220
Condition
BET
BET
L
L
Normal Operation
H
H
Field BET Operation
Table 6. THCV220 Field BET result
BETOUT
Output
L
Bit error occurred
H
No error
THCV219
THCV220
Test Pattern
Generator
Test Pattern
Checker
BET=H
BET=H
TTL data inputs
are ignored
CLKIN
BETOUT
Test Point
for
Field BET
Figure 5. Field BET Configuration
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Absolute Maximum Ratings*
Parameter
Supply Voltage(VCC,AVCC)
CMOS Input Voltage
CML Transmitter Output Voltage
Output Current
Storage Temperature
Junction Temperature
Reflow Peak Temperature/Time
min.
-0.3
-0.3
-0.3
-30
-55
-
typ.
-
max.
+4.0
VCC+0.3
CAPINA+0.3
30
+125
+125
+260/10sec
Unit
V
V
V
mA
℃
℃
℃
“Absolute Maximum Ratings” are those values beyond which the safety of the device can not be guaranteed.
They are not meant to imply that the device should be operated at these limits. The tables of “Electrical
Characteristics” specify conditions for device operation.
Recommended Operating Conditions
Parameter
min.
2.3
2.6
3.0
-40
Supply Voltage（VCC,AVCC）
CAPOUT and CAPINA Voltage
Operating Temperature
typ.
2.5
2.8
3.3
1.20
-
max.
2.7
3.0
3.6
85
Unit
V
V
V
V
℃
Supply Current
symbol
Parameter
ITCCW
Transmitter Supply Current
ITCCS
Transmitter Power Down
Supply Current
Over recommended operating supply and temperature ranges unless otherwise specified.
conditions
min.
typ.
max.
Unit
COL=L
100
mA
PRE=H
PDN=L
1.2
10
mA
All Inputs =Fixed LorH
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Electrical Specifications
CMOS DC Specifications
symbol
IIH
IIL
Parameter
Input Leak Current High
Input Leak Current Low
symbol
Parameter
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
symbol
Parameter
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
symbol
Parameter
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
Over recommended operating supply and temperature ranges unless otherwise specified.
conditions
min.
typ.
max.
Unit
-10
+10
uA
-10
+10
uA
conditions
I3
I3L
I3
I3L
min.
2.0
2.1
0
0
typ.
-
max.
VCC
VCC
0.8
0.7
VCC=3.3±0.3V
Unit
V
V
V
V
conditions
I3
I3L
I3
I3L
min.
1.8
1.9
0
0
typ.
-
max.
VCC
VCC
0.7
0.6
VCC=2.8±0.2V
Unit
V
V
V
V
conditions
I3
I3L
I3
I3L
min.
1.7
1.6
0
0
typ.
-
max.
VCC
VCC
0.7
0.5
VCC=2.5±0.2V
Unit
V
V
V
V
CML DC Specifications
symbol
Parameter
VTOD
CML Differential Mode Output Voltage
PRE
CML Pre-emphasis Level
VTOC
CML Common Mode Output Voltage
ITOH
ITOS
CML Output Leak Current High
CML Output Short Circuit Current
Over recommended operating supply and temperature ranges unless otherwise specified.
conditions
min.
typ.
max.
Unit
CMLDRV=L
133
200
267
mV
CMLDRV=H
200
300
400
mV
PRE=L
0
%
PRE=H, CMLDRV=L
100
%
PRE=H, CMLDRV=H
50
%
PRE=L
1.2 - VTOD
V
1.2 - 2 * VTOD
PRE=H, CMLDRV=L
V
1.2 - 1.5 * VTOD
PRE=H, CMLDRV=H
V
PDN=L, TXP/N=1.2V
±30
uA
PDN=L, TXP/N=0V
-80
mA
AC Specifications
symbol
tTRF
tTCIP
tTCH
tTCL
tTS
tTH
tTCD
tTPD
tTPLL0
tTPLL1
tTNP0
tTNP1
Over recommended operating supply and temperature ranges unless otherwise specified.
conditions
min.
typ.
max.
Unit
50
150
ps
COL=H, LFSEL=L
10
50
ns
COL=H, LFSEL=H
25
100
ns
CLKIN Period
COL=L, LFSEL=L
13.34
66.66
ns
COL=L, LFSEL=H
33.34
133.33
ns
CLK IN High Time
0.35tTCIP
0.5tTCIP
0.65tTCIP
ns
CLK IN Low Time
0.35tTCIP
0.5tTCIP
0.65tTCIP
ns
TTL Data Setup to CLK IN
2.0
ns
TTL Data Hold to CLK IN
0.6
ns
COL=H
typ. - tTCIP
10.6tTCIP+1.7
typ. + tTCIP
ns
Input Clock to Output Data Delay
COL=L
typ. - tTCIP
9.8tTCIP+1.7
typ. + tTCIP
ns
Power On to PDN High Delay
0
ns
PDN High to CML Output Delay
10
ms
PDN Low to CML Output High Fix Delay
20
ns
LOCKN High to Training Pattern Output Delay
10
ms
LOCKN Low to Data Pattern Output Delay
10
ms
Parameter
CML Output Rise and Fall Time(20%-80%)
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THCV219_Rev.2.40_E
AC Timing Diagrams and Test Circuits
CMOS/TTL Input Switching Characteristics
tTCIP
tTCH (RF=L)
tTCL (RF=H)
tTCH (RF=H)
tTCL (RF=L)
RF=L
CLKIN
VCC/2
VCC/2
VCC/2
RF=H
tTH
tTS
R9-0,G9-0,B9-0
CONT1,CONT2
HSYNC,VSYNC
DE,ASYNDE
VCC/2
VCC/2
Figure 6. CMOS/TTL Input Switching Timing Diagrams
CML Output Switching Characteristics
TXp
75～200nF
50ohm
75～200nF
50ohm
TXn
< 5mm
80%
80%
Vdiff = (TXp) - (TXn)
20%
20%
tTRF
tTRF
Figure 7. CML buffer Switching Timing Diagrams and Test Circuit
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THCV219_Rev.2.40_E
THCV219
V-by-One® HS Rx
CAP
C=75～
200nF
TXp
50ohm
C=75～
200nF
RXp
TXn
CML Receiver
RXn
Zdiff=100ohm
50ohm
CML
Transmitter
Vbias
GND
Figure 8. CML buffer scheme
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Latency Characteristics
R/F=H
CLKIN
VCC/2
R/F=L
R9-0,G9-0,B9-0
CONT1,CONT2
HSYNC,VSYNC
DE,ASYNDE
VCC/2
VCC/2
tTCD
tTCIP
Vdiff = (TXp) - (TXn)
pixel 1st bit
Figure 9. THCV219 Latency
Data output Sequence
VCC
CLKIN
RGB,CONT
H,VSYNC,DE
Data Pattern
HTPDN
PDN
tTPD
tTPLL0
tTNP1
LOCKN
TXp/n
tTPLL1
Fix to CAPINA
Training
pattern
tTNP0
Normal
pattern
Training
pattern
Figure 10. THCV219 Sequence
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THCV219_Rev.2.40_E
Data Mapping
Table 7. CMOS/TTL Input Data Mapping
Data Signals
10bit
8bit
(30bpp)
(24bpp)
R0 *1
R1 *1
R2
R0
R3
R1
R4
R2
R5
R3
R6
R4
R7
R5
R8
R6
R9
R7
G0 *1
G1 *1
G2
G0
G3
G1
G4
G2
G5
G3
G6
G4
G7
G5
G8
G6
G9
G7
B0 *1
B1 *1
B2 *1
B0 *1
B3 *1
B1 *1
B4 *1
B2 *1
B5 *1
B3 *1
B6 *1
B4 *1
B7 *1
B5 *1
B8 *1
B6 *1
B9 *1
B7 *1
CONT1 *1
CONT2 *1
HSYNC
HSYNC
VSYNC
VSYNC
DE
DE
Transmitter
Input Pin Name
10bit
8bit
(30bpp)
(24bpp)
R0
R1
R2
R2
R3
R3
R4
R4
R5
R5
R6
R6
R7
R7
R8
R8
R9
R9
G0
G1
G2
G2
G3
G3
G4
G4
G5
G5
G6
G6
G7
G7
G8
G8
G9
G9
B0
B1
B2
B2
B3
B3
B4
B4
B5
B5
B6
B6
B7
B7
B8
B8
B9
B9
CONT1
CONT2
HSYNC
HSYNC
VSYNC
VSYNC
DE
DE
Symbol defined
by V-by-One® HS
D30
D31
D0
D1
D2
D3
D4
D5
D6
D7
D28
D29
D8
D9
D10
D11
D12
D13
D14
D15
D26
D27
D16
D17
D18
D19
D20
D21
D22
D23
D25
D24
HSYNC
VSYNC
DE
*1 CTL bits, which are carried during DE=Low except the 1st and the last pixel.
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THCV219_Rev.2.40_E
Package
TOP VIEW
9.0
LASER MARK
FOR PIN1
9.0
BOTTOM VIEW
1.10
6.00
17
32
16
33
0.09 R
0.45
6.00
PIN1 ID
0.20 R
1
48
SIDE VIEW
0.5
0.4
0.65
0.25
1.10
49
0.9 MAX
64
THine Electronics, Inc.
Copyright©2022 THine Electronics, Inc.
16/17
Security E
THCV219_Rev.2.40_E
Notices and Requests
1. The product specifications described in this material are subject to change without prior notice.
2. The circuit diagrams described in this material are examples of the application which may not always apply to
the customer's design. We are not responsible for possible errors and omissions in this material. Please note if
errors or omissions should be found in this material, we may not be able to correct them immediately.
3. This material contains our copyright, know-how or other proprietary. Copying or disclosing to third parties
the contents of this material without our prior permission is prohibited.
4. Note that if infringement of any third party's industrial ownership should occur by using this product, we will
be exempted from the responsibility unless it directly relates to the production process or functions of the
product.
5. Product Application
5.1 Application of this product is intended for and limited to the following applications: audio-video
device, office automation device, communication device, consumer electronics, smartphone, feature
phone, and amusement machine device. This product must not be used for applications that require
extremely high-reliability/safety such as aerospace device, traffic device, transportation device, nuclear
power control device, combustion chamber device, medical device related to critical care, or any kind of
safety device.
5.2 This product is not intended to be used as an automotive part, unless the product is specified as a
product conforming to the demands and specifications of ISO/TS16949 ("the Specified Product") in this
data sheet. THine Electronics, Inc. (“THine”) accepts no liability whatsoever for any product other than
the Specified Product for it not conforming to the aforementioned demands and specifications.
5.3 THine accepts liability for demands and specifications of the Specified Product only to the extent
that the user and THine have been previously and explicitly agreed to each other.
6. Despite our utmost efforts to improve the quality and reliability of the product, faults will occur with a certain
small probability, which is inevitable to a semi-conductor product. Therefore, you are encouraged to have
sufficiently redundant or error preventive design applied to the use of the product so as not to have our
product cause any social or public damage.
7. Please note that this product is not designed to be radiation-proof.
8. Testing and other quality control techniques are used to this product to the extent THine deems necessary
to support warranty for performance of this product. Except where mandated by applicable law or
deemed necessary by THine based on the user’s request, testing of all functions and performance of the
product is not necessarily performed.
9. Customers are asked, if required, to judge by themselves if this product falls under the category of strategic
goods under the Foreign Exchange and Foreign Trade Control Law.
10. The product or peripheral parts may be damaged by a surge in voltage over the absolute maximum ratings or
malfunction, if pins of the product are shorted by such as foreign substance. The damageｓ may cause a
smoking and ignition. Therefore, you are encouraged to implement safety measures by adding protection
devices, such as fuses.
THine Electronics, Inc.
https://www.thine.co.jp
Copyright©2022 THine Electronics, Inc.
17/17
THine Electronics, Inc.
Security E
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