THCV235_THCV236_Rev.3.70_E
THCV235 and THCV236
SerDes transmitter and receiver with bi-directional transceiver
General Description
Features
The THCV235 and THCV236 are designed to
support video data transmission between the host and
display.
One high-speed lane can carry up to 32bit data and
3bits of synchronizing signals at a pixel clock
frequency from 6MHz to 160MHz by converting
RGB444 to YCbCr422.
The chipset, which has one high-speed data lane,
can transmit video data up to 1080p/60Hz.
The maximum serial data rate is 4.00Gbps/lane.
Color depth selectable:24/32bit
RGB YCbCr422 color space conversion
function
Wide frequency range
AC coupling for high-speed lanes
CDR requires no external frequency reference
Wide range supply voltage from 1.7V to 3.6V
Additional spread spectrum on data stream
2-wire serial interface bridge function(400kbps)
Remote side GPIO control and monitoring
Low speed data bridge function
QFN64(9mm x 9mm) with exposed pad ground
V-by-One® HS standard version1.4 compliant
EU RoHS compliant
Block Diagram
Settings
2-wire I/F
SDA/SCL
Controls
RCMP
RCMN
OSC
LDO
Copyright©2022 THine Electronics, Inc.
Controls
LVCMOS output
TCMP
TCMN
Formatter
YCbCr to RGB
RXP
RXN
Deserializer
TXP
TXN
CDR
Serializer
THCV236
PLL
Formatter
RGB to YCbCr
D31-D0
HSYNC
VSYNC
DE
CLKIN
LVCMOS input
THCV235
D31-D0
HSYNC
VSYNC
DE
CLKOUT
Settings
2-wire I/F
SDA/SCL
OSC
CAPOUT
CAPINA
CAPINP
LDO
CAPOUT
CAPINA
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THCV235_THCV236_Rev.3.70_E
Contents Page
General Description .............................................................................................................................................. 1
Features .................................................................................................................................................................. 1
Block Diagram ....................................................................................................................................................... 1
Pin Configuration .................................................................................................................................................. 4
Pin Description ...................................................................................................................................................... 5
Pin Description for THCV235 .......................................................................................................................... 5
Pin Description for THCV236 .......................................................................................................................... 9
Functional Overview ........................................................................................................................................... 13
Functional Description ........................................................................................................................................ 13
Internal Reference Output/Input Function (CAPOUT, CAPINA, CAPINP) ............................................ 13
Power Down (PDN1, PDN0) ........................................................................................................................... 13
Main-Link Mode Setting................................................................................................................................. 14
V-by-One® HS Mode (MAINMODE=0) ........................................................................................................ 14
Sync Free Mode (MAINMODE=1) ................................................................................................................ 14
Color Space Conversion .................................................................................................................................. 14
Pre-emphasis and Drive Select Function (THCV235 only) ......................................................................... 14
Permanent Clock Output (THCV236 only) .................................................................................................. 15
Spread Spectrum Clock Generator (SSCG).................................................................................................. 15
Hot-Plug Function ........................................................................................................................................... 18
Lock Detect Function ...................................................................................................................................... 18
Field BET Operation ....................................................................................................................................... 20
Data Width and Frequency Range Select Function ..................................................................................... 22
Data Mapping .................................................................................................................................................. 24
Sub-Link Mode Setting ................................................................................................................................... 26
2-wire serial I/F Mode ..................................................................................................................................... 26
Low Speed Data Bridge Mode ........................................................................................................................ 39
Register Map ........................................................................................................................................................ 40
Absolute Maximum Ratings ............................................................................................................................... 50
Recommended Operating Conditions................................................................................................................ 50
Electrical Specification........................................................................................................................................ 50
LVCMOS DC Specification ............................................................................................................................ 50
CML DC Specification .................................................................................................................................... 51
CML Bi-Directional DC Specification ........................................................................................................... 51
Supply Current ................................................................................................................................................ 52
Switching Characteristics ............................................................................................................................... 52
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AC Timing Diagrams and Test Circuits ............................................................................................................ 56
LVCMOS Input, Output Switching Characteristics .................................................................................... 56
CML Output Switching Characteristics ........................................................................................................ 57
CML Bi-directional Output Test Circuit ....................................................................................................... 58
Lock and Unlock Sequence ............................................................................................................................. 60
GPIO Switching Characteristics .................................................................................................................... 63
PCB Layout Guideline regarding VDD and AVDD for THCV236 ................................................................. 66
Package ................................................................................................................................................................. 67
Notices and Requests ........................................................................................................................................... 68
Copyright©2022 THine Electronics, Inc.
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THCV235_THCV236_Rev.3.70_E
Pin Configuration
VDD
HSYNC
DE
D30
D31
SSEN/GPIO0
BET/GPIO1
CAPOUT
MAINMODE/TCMP
HFSEL/TCMN
TXP
TXN
CAPINA
CAPINP
LOCKN/MSSEL
HTPDN/SUBMODE
47
48
VSYNC
D29
46 D28
45 D27
44 D26
43 D25
42 D24
41 VDD
40 AVDD
39 D23
38 D22
37 D21
36 D20
35 D19
34 D18
33 D17
THCV235 (QFN 64pin)
49
32
50
31
51
30
52
29
53
28
54
27
55
26
(TOP VIEW)
56
57
25
24
65 EXPGND
58
23
59
22
60
21
61
20
62
19
63
18
64
17
VDD
D16
D15
D14
D13
D12
CLKIN
VDD
D11
D10
D9
D8
D7
D6
D5
D4
16
15
14
13
11
12
10
9
8
7
6
5
4
3
2
1
VDD
D3
D2
D1
D0
LATEN/SD3/AIN1/GPIO4
CMLDRV/SD2/AIN0/GPIO3
PRE/SD1
COL1/SD0
COL0/INT/GPIO2
RF/BETOUT
TEST2
TEST1
LFSEL
PDN1
PDN0
VDD
HSYNC
DE
D1
D0
HTPDN/SUBMODE
LOCKN/MSSEL
CAPOUT
RXN
RXP
CAPINA
MAINMODE/RCMN
HFSEL/RCMP
RXDEFSEL
OE
BET
47
48
VSYNC
D2
46 D3
45 D4
44 D5
43 D6
42 D7
41 VDD
40 AVDD
39 D8
38 D9
37 D10
36 D11
35 D12
34 D13
33 D14
THCV236 (QFN 64pin)
49
32
50
31
51
30
52
29
53
28
54
27
55
26
(TOP VIEW)
56
57
25
24
65 EXPGND
58
23
59
22
60
21
61
20
62
19
63
18
64
17
VDD
D15
D16
D17
D18
D19
CLKOUT
VDD
D20
D21
D22
D23
D24/GPIO3
D25/GPIO4
D26
D27
16
15
14
13
11
12
9
10
8
7
6
5
4
3
2
1
VDD
D28
D29
D30
D31
LATEN/SD3/AIN1/GPIO0
TTLDRV/SD2/AIN0/GPIO1
OUTSEL/SD1
COL1/SD0
COL0/INT/GPIO2
RF/BETOUT
TEST2
TEST1
LFSEL
PDN1
PDN0
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Pin Description
Pin Description for THCV235
Pin Name
TXP
TXN
MAINMODE/
TCMP
59
60
57
Pin No.
Type
CO
CO
I/CB
HFSEL/TCMN
58
I/CB
HTPDN/
SUBMODE
64
IL
LOCKN/MSSEL
63
IL
LATEN/SD3/AIN1/
GPIO4
11
B
Copyright©2022 THine Electronics, Inc.
Description
High-Speed CML Signal Output(Main-Link)
High-Speed CML Signal Output(Main-Link)
MAINMODE : Setting V-by-One® HS Mode or Sync Free
Mode when PDN1=0.
0 : V-by-One® HS Mode
1 : Sync Free Mode
TCMP : CML Signal Bi-directional Input/Output(Sub-Link)
when PDN1=1.
HFSEL : High Frequency mode select when PDN1=0.
0 : High Frequency mode Disable
1 : High Frequency mode Enable
TCMN : CML Signal Bi-directional Input/Output(Sub-Link)
when PDN1=1.
HTPDN : Hot Plug Detect Input when PDN1=0.
SUBMODE : Sub-Link Mode Select when PDN1=1.
0: 2-wire serial interface(I/F) Mode(default No Clock
Stretching mode)
1: Low Speed Data Bridge Mode
Forbid the different setting between THCV235 and THCV236.
LOCKN : Lock Detect Input when PDN1=0.
MSSEL : Sub-Link Master/Slave Select when PDN1=1.
0 : Sub-Link Master side(inside 2-wire serial I/F is slave)
1 : Sub-Link Slave side(inside 2-wire serial I/F is master)
Sub-Link Master is connected to HOST MPU.
Forbid the same setting between THCV235 and THCV236.
LATEN : Latch select input under Field BET(Main-Link or
Sub-Link).
0 : NOT Latched result
1 : Latched result
SD3 : Sub-Link Data Input/Output when PDN1=1 and
SUBMODE=1.
When Sub-Link is Master (MSSEL=0), SD3 is output.
When Sub-Link is Slave (MSSEL=1), SD3 is input.
AIN1 : Device ID setting for 2-wire serial I/F when
SUBMODE=0 and MSSEL=0. See Table 26.
GPIO4 : General Purpose Input/Output when SUBMODE=0
and MSSEL=1.
When GPIO4 is used as Open-Drain Output, it must be
connected with a pull-up resistor to VDD.
When GPIO4 is used as push pull output or input, no external
component is required.
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THCV235_THCV236_Rev.3.70_E
CMLDRV/SD2/
AIN0/GPIO3
10
B
PRE/SD1
9
B
COL1/SD0
8
B
COL0/INT/GPIO2
7
B
Copyright©2022 THine Electronics, Inc.
CMLDRV : High-Speed CML Output Drive Strength Select
when PDN1=0.
0 : Weak Drive Strength (600mV diff p-p)
1 : Normal Drive Strength (800mV diff p-p)
SD2 : Sub-Link Data Input/Output when PDN1=1 and
SUBMODE=1.
When Sub-Link is Master (MSSEL=0), SD2 is input.
When Sub-Link is Slave (MSSEL=1), SD2 is output.
AIN0 : Device ID setting for 2-wire serial I/F when
SUBMODE=0 and MSSEL=0. See Table 26.
GPIO3 : General Purpose Input/Output when SUBMODE=0
and MSSEL=1.
When GPIO3 is used as Open-Drain Output, it must be
connected with a pull-up resistor to VDD.
When GPIO3 is used as push pull output or input, no external
component is required.
PRE : Pre-Emphasis Level Select Input when PDN1=0.
0 : Pre-Emphasis Disable
1 : Pre-Emphasis Enable (when CMLDRV=1. See Table 4)
SD1 : Sub-Link Data Input/Output when PDN1=1.
When SUBMODE=0, SD1 is used as SCL input/output for
2-wire serial I/F, requires pull-up resistor to VDD.
When SUBMODE=1 and MSSEL=0, SD1 is input.
When SUBMODE=1 and MSSEL=1, SD1 is output.
COL1 : Color Space Converter Enable when PDN1=0 and
MAINMODE=0.
0 : Color Space Converter Disable
1 : Color Space Converter Enable
Data Width Setting when PDN1=0 and MAINMODE=1.
See Table 20.
SD0 : Sub-Link Data Input/Output when PDN1=1.
When SUBMODE=0, SD0 is used as SDA input/output for
2-wire serial I/F, requires pull-up resistor to VDD.
When SUBMODE=1 and MSSEL=0, SD0 is input.
When SUBMODE=1 and MSSEL=1, SD0 is output.
COL0 : Data Width Setting when PDN1=0. See Table 20.
INT : Interrupt signal output for Sub-Link when
SUBMODE=0 and MSSEL=0. It must be connected with a
pull-up resistor to VDD.
L : Interrupt occurred
H : Steady state
GPIO2 : General Purpose Input/Output when SUBMODE=0
and MSSEL=1.
When GPIO2 is used as Open-Drain Output, it must be
connected with a pull-up resistor to VDD.
When GPIO2 is used as push pull output or input, no external
component is required.
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THCV235_THCV236_Rev.3.70_E
BET/GPIO1
55
BO
SSEN/GPIO0
54
BO
CLKIN
D31-D0
26
53,52,47-42,
39-33,31-27,
24-17,15-12
51
50
48
6
DE
HSYNC
VSYNC
RF/BETOUT
I
I
BET : Field BET entry when PDN1=0 or Sub-Link is active
and Low Speed Data Bridge Mode(PDN1=1, SUBMODE=1).
0 : Normal Operation
1 : Field BET Operation
GPIO1 : General Purpose Input/Output when SUBMODE=0.
GPIO1 has Open-Drain Output buffer, it must be connected
with a pull-up resistor to VDD.
SSEN : Spread Spectrum Clock Generator(SSCG) Enable
when PDN1=0 or Sub-Link is active and Low Speed Data
Bridge Mode(PDN1=1, SUBMODE=1).
0 : SSCG Disable
1 : SSCG Enable
GPIO0 : General Purpose Input/Output when SUBMODE=0.
GPIO0 has Open-Drain Output buffer, it must be connected
with a pull-up resistor to VDD.
Clock Input
Pixel Data Input
DE Input
HSYNC Input
VSYNC Input
RF : Input Clock Triggering edge select. See Figure 19
0 : Falling Edge
1 : Rising Edge
BETOUT : Field BET Result Output when Field BET mode
LFSEL
3
I
Low Frequency mode select
0 : Low Frequency mode Disable
1 : Low Frequency mode Enable
PDN1
2
IL
Sub-Link Power Down
0 : Power Down. Main-Link setting by external pin
1 : Normal Operation. Main-Link Setting by 2-wire serial I/F
PDN0
1
IL
Main-Link Power Down
0 : Power Down
1 : Normal Operation
TEST2
5
I
Test pin. Must be tied to Ground for normal operation.
TEST1
4
IL
Test pin. Must be tied to Ground for normal operation.
CAPOUT
56
PWR Decoupling Capacitor Pin, 1.2V output.
CAPINA
61
PWR Reference Input for Analog Circuit. Must be tied to CAPOUT.
CAPINP
62
PWR Reference Input for Analog Circuit. Must be tied to CAPOUT.
VDD
49,41,32,25,16 PWR 1.7-3.6V Digital Power Supply Pin for LVCMOS I/O
AVDD
40
PWR 1.7-3.6V Analog Power Supply Pin for LDO
EXPGND
65
GND Exposed Pad Ground. Must be tied to the PCB ground plane
through an array of vias.
CO : CML Output buffer , CB : CML Bi-directional buffer
I : LVCMOS Input buffer , IL : Low Speed LVCMOS Input buffer
B : LVCMOS Bi-directional buffer , BO : Open-Drain LVCMOS Bi-directional buffer
PWR : Power supply , GND : Ground
Copyright©2022 THine Electronics, Inc.
I
I
I
B
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Table 1. Pin Sharing Description (THCV235)
Sub-Link State →
Sub-Link
Power Down
Sub-Link
Master/Slave →
PDN1
HTPDN/SUBMODE
LOCKN/MSSEL
BET/GPIO1
Low Speed Data
Bridge Mode
2-wire serial
I/F Mode
-
Master
Slave
Master
Slave
0
*
*
0
1
1
0
0
1
1
1
0
1
0
0
*
1
0
1
*
INT
SD0(SDA)
SD1(SCL)
AIN0
AIN1
GPIO2(*4)
SD0(SDA)
SD1(SCL)
GPIO3(*5)
GPIO4(*5)
GPIO0(*4)
GPIO1(*4)
GPIO0(*4)
GPIO1(*4)
RF
BETOUT(*2)
COL0/INT/GPIO2
COL0
COL0
COL0
COL1/SD0
COL1
SD0(input)
SD0(output)(*6)
PRE/SD1
PRE
SD1(input)
SD1(output)(*6)
CMLDRV/SD2/AIN0/GPIO3
CMLDRV
SD2(input)
SD2(output)(*6)
-(*1)
SD3(output)(*6)
SD3(input)
LATEN/SD3/AIN1/GPIO4
LATEN(*3)
SSEN/GPIO0
SSEN
SSEN
SSEN
BET/GPIO1
BET
BET
BET
MAINMODE/TCMP
MAINMODE
TCMP
HFSEL/TCMN
HFSEL
TCMN
LOCKN/MSSEL
LOCKN
MSSEL
HTPDN/SUBMODE
HTPDN
SUBMODE
*1 There is no function. LVCMOS IO has input state. Must be fixed at 0 or 1 input.
*2 When Field BET mode (Main-Link or Sub-Link), it functions as BETOUT output.
*3 When Field BET mode (Main-Link or Sub-Link), it functions as LATEN input.
*4 Programmable GPIO input is default on register setting.
*5 Through GPIO open-drain output is default on register setting.
*6 Low Speed Data Bridge Mode output is LVCMOS push pull buffer.
RF/BETOUT
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Pin Description for THCV236
Pin Name
RXP
RXN
HFSEL/RCMP
58
57
61
Pin No.
Type
CI
CI
CB/I
MAINMODE/
RCMN
60
CB/I
HTPDN/
SUBMODE
54
BO
LOCKN/
MSSEL
55
BO
LATEN/SD3/
AIN1/GPIO0
11
B
Copyright©2022 THine Electronics, Inc.
Description
High-Speed CML Signal Input(Main-Link)
High-Speed CML Signal Input(Main-Link)
HFSEL : High Frequency Mode select when PDN1=0.
0 : High Frequency Mode Disable
1 : High Frequency Mode Enable
RCMP : CML Signal Bi-directional Input/Output(Sub-Link) when
PDN1=1.
MAINMODE : Setting V-by-One® HS Mode or Sync Free Mode
when PDN1=0.
0 : V-by-One® HS Mode
1 : Sync Free Mode
RCMN : CML Signal Bi-directional Input/Output(Sub-Link)
when PDN1=1.
HTPDN : Hot Plug Detect Output when PDN1=0. Must be
connected to Tx HTPDN with 10kΩ pull-up resistor.
SUBMODE : Sub-Link Mode Select when PDN1=1.
0 : 2-wire serial I/F Mode (default No Clock Stretching mode)
1 : Low Speed Data Bridge Mode
Forbid the different setting between THCV235 and THCV236.
LOCKN : Lock Detect Output when PDN1=0. Must be connected
to Tx LOCKN with 10kΩ pull-up resistor.
MSSEL : Sub-Link Master/Slave Select when PDN1=1.
0 : Sub-Link Master side(inside 2-wire serial I/F is slave)
1 : Sub-Link Slave side(inside 2-wire serial I/F is master)
Sub-Link Master is connected to HOST MPU.
Forbid the same setting between THCV235 and THCV236.
LATEN : Latch select input under Field BET(Main-Link or
Sub-Link).
0 : NOT Latched result
1 : Latched result
SD3 : Sub-Link Data Input/Output when PDN1=1 and
SUBMODE=1.
When Sub-Link is Master (MSSEL=0), SD3 is output.
When Sub-Link is Slave (MSSEL=1), SD3 is input.
AIN1 : Device ID setting for 2-wire serial I/F when
SUBMODE=0 and MSSEL=0. See Table 26.
GPIO0 : General Purpose Input/Output when SUBMODE=0 and
MSSEL=1.
When GPIO0 is used as Open-Drain Output, it must be connected
with a pull-up resistor to VDD.
When GPIO0 is used as push pull output or input, no external
component is required.
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TTLDRV/SD2/
AIN0/GPIO1
10
B
OUTSEL/SD1
9
B
COL1/SD0
8
B
COL0/INT/
GPIO2
7
B
CLKOUT
D31-D26
26
12-15,17,18
O
O
Copyright©2022 THine Electronics, Inc.
TTLDRV : TTL Output Drive Strength Select when PDN1=0.
0 : Weak Drive Strength
1 : Normal Drive Strength
SD2 : Sub-Link Data Input/Output when PDN1=1 and
SUBMODE=1.
When Sub-Link is Master (MSSEL=0), SD2 is input.
When Sub-Link is Slave (MSSEL=1), SD2 is output.
AIN0 : Device ID setting for 2-wire serial I/F when
SUBMODE=0 and MSSEL=0. See Table 26.
GPIO1 : General Purpose Input/Output when SUBMODE=0 and
MSSEL=1.
When GPIO1 is used as Open-Drain Output, it must be connected
with a pull-up resistor to VDD.
When GPIO1 is used as push pull output or input, no external
component is required.
OUTSEL : Permanent Clock Output Enable when PDN1=0.
0 : Permanent Clock Output Disable
1 : Permanent Clock Output Enable
SD1 : Sub-Link Data Input/Output when PDN1=1.
When SUBMODE=0, SD1 is used as SCL input/output for 2-wire
serial I/F, requires pull-up resistor to VDD.
When SUBMODE=1 and MSSEL=0, SD1 is input.
When SUBMODE=1 and MSSEL=1, SD1 is output.
COL1 : Color Space Converter Enable when PDN1=0 and
MAINMODE=0.
0 : Color Space Converter Disable
1 : Color Space Converter Enable
Data Width Setting when PDN1=0 and MAINMODE=1. See
Table 20.
SD0 : Sub-Link Data Input/Output when PDN1=1.
When SUBMODE=0, SD0 is used as SDA input/output for 2-wire
serial I/F, requires pull-up resistor to VDD.
When SUBMODE=1 and MSSEL=0, SD0 is input.
When SUBMODE=1 and MSSEL=1, SD0 is output.
COL0 : Data Width Setting when PDN1=0. See Table 22.
INT : Interrupt signal output for Sub-Link when SUBMODE=0
and Sub-Link Master. It must be connected with a pull-up resistor
to VDD.
L : Interrupt occurred
H : Steady state
GPIO2 : General Purpose Input/Output when SUBMODE=0 and
MSSEL=1.
When GPIO2 is used as Open-Drain Output, it must be connected
with a pull-up resistor to VDD.
When GPIO2 is used as push pull output or input, no external
component is required.
Clock Output
Pixel Data Output
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D25/GPIO4
19
B
D24/GPIO3
20
B
D23-D0
21-24,27-31,33-39,
42-47,52,53
51
50
48
63
O
DE
HSYNC
VSYNC
OE
D25 : Pixel Data Output
GPIO4 : General Purpose Input/Output when SUBMODE=0,
MSSEL=0 and RXDEFSEL=0.
When GPIO4 is used as Open-Drain Output, it must be connected
with a pull-up resistor to VDD.
When GPIO4 is used as push pull output or input, no external
component is required.
D24 : Pixel Data Output
GPIO3 : General Purpose Input/Output when SUBMODE=0,
MSSEL=0 and RXDEFSEL=0.
When GPIO3 is used as Open-Drain Output, it must be connected
with a pull-up resistor to VDD. When GPIO3 is used as push pull
output or input, no external component is required.
Pixel Data Output
DE Output
HSYNC Output
VSYNC Output
Output Enable
0 : LVCMOS Output Disable (Hi-Z) except for HTPDN,
LOCKN when PDN1=0 and except for BETOUT when BET=1.
1 : LVCMOS Output Enable
BET
64
IL
Field BET entry
0 : Normal Operation
1 : Field BET Operation
RF/BETOUT
6
B
RF : Output Clock Triggering edge select. See Table 20.
0 : Falling Edge
1 : Rising Edge
BETOUT : Field BET Result Output
RXDEFSEL
62
I
Internal Register Default Setting Select. See Table 44, Table 45
0 : for THCV231
1 : for THCV235
LFSEL
3
I
Low Frequency mode select
0 : Low Frequency mode Disable
1 : Low Frequency mode Enable
PDN1
2
IL
Sub-Link Power Down
0 : Power Down. Main-Link setting by external pin
1 : Normal Operation. Main-Link Setting by 2-wire serial I/F
PDN0
1
IL
Main-Link Power Down
0 : Power Down
1 : Normal Operation
TEST2
5
I
Test pin. Must be tied to Ground for normal operation.
TEST1
4
IL
Test pin. Must be tied to Ground for normal operation.
CAPOUT
56
PWR Decoupling Capacitor Pin, 1.2V output.
CAPINA
59
PWR Reference Input for Analog Circuit. Must be tied to CAPOUT.
VDD
49,41,32,25,16
PWR 1.7-3.6V Digital Power Supply Pin for LVCMOS I/O
AVDD
40
PWR 1.7-3.6V Analog Power Supply Pin for LDO
EXPGND
65
GND Exposed Pad Ground. Must be tied to the PCB ground plane
through an array of vias.
CI : CML Input buffer , CB : CML Bi-directional buffer
I : LVCMOS Input buffer , IL : Low Speed LVCMOS Input buffer , O: LVCMOS Output buffer
B : LVCMOS Bi-directional buffer , BO : Open-Drain LVCMOS Bi-directional buffer
PWR : Power supply , GND : Ground
Copyright©2022 THine Electronics, Inc.
O
O
O
IL
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Table 2. Pin Sharing Description (THCV236)
Sub-Link State →
Sub-Link
Master/Slave →
PDN1
HTPDN/SUBMODE
LOCKN/MSSEL
BET
RXDEFSEL
Sub-Link
Power Down
Low Speed Data
Bridge Mode
-
Master
Slave
Master 1
Master 2
Slave
0
*
*
0
*
1
1
0
0
*
1
1
1
0
*
1
0
0
0
1
1
0
0
0
0
1
0
1
0
*
INT
SD0(SDA)
SD1(SCL)
AIN0
AIN1
GPIO2(*4)
SD0(SDA)
SD1(SCL)
GPIO1(*4)
GPIO0(*4)
GPIO3(*5)
GPIO4(*5)
D24
D25
RF/BETOUT
COL0/INT/GPIO2
COL1/SD0
OUTSEL/SD1
TTLDRV/SD2/AIN0/GPIO1
LATEN/SD3/AIN1/GPIO0
D24/GPIO3
D25/GPIO4
HTPDN/SUBMODE
LOCKN/MSSEL
MAINMODE/RCMN
HFSEL/RCMP
2-wire serial
I/F Mode
COL0
COL1
OUTSEL
TTLDRV
-(*1)
COL0
SD0(input)
SD1(input)
SD2(input)
SD3(output)(*6)
D24
D25
HTPDN
LOCKN
MAINMODE
HFSEL
D24
D25
RF
BETOUT(*2)
COL0
INT
SD0(output)(*6)
SD0(SDA)
SD1(output)(*6)
SD1(SCL)
SD2(output)(*6)
AIN0
SD3(input)
AIN1
LATEN(*3)
D24
D24
D25
D25
SUBMODE
MSSEL
RCMN
RCMP
*1 There is no function. LVCMOS IO has input state. Must be fixed at 0 or 1 input.
*2 When Field BET mode (Main-Link or Sub-Link), it functions as BETOUT output.
*3 When Field BET mode (Main-Link or Sub-Link), it functions as LATEN input.
*4 Programmable GPIO input is default on register setting.
*5 Through GPIO input is default on register setting.
*6 Low Speed Data Bridge Mode output is LVCMOS push pull buffer.
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Functional Overview
With High Speed CML SerDes, proprietary encoding scheme and CDR (Clock and Data Recovery)
architecture, the THCV235 and THCV236 enable transmission of 24/30bit video data, 2bits of user defined data,
synchronizing signals HSYNC,VSYNC and DE(Data Enable) as well as any data (up to 35 bit) through
Main-Link by single differential pair cable with minimal external components. In addition, the THCV235 and
THCV236 have Sub-Link which enables bi-directional transmission of 2-wire serial interface signals, GPIO
signals and also HTPDN/LOCKN signals for Main-Link through the other 1-pair of CML-Line. It does not need
any external frequency reference, such as a crystal oscillator. The THCV235 - THCV236 system is able to watch
and control peripheral devices via 2-wire serial interface or GPIOs. They also can report interrupt events caused
by change of GPIO inputs and internal statuses.
Functional Description
Internal Reference Output/Input Function (CAPOUT, CAPINA, CAPINP)
An internal regulator produces the 1.2V (CAPOUT). This 1.2V linear regulator can’t supply any other
external loads. Bypass CAPOUT to GND with 10uF.
CAPINP (THCV235 only) supplies reference voltage for internal PLL, and CAPINA supplies reference
voltage for any internal analog circuit. Bypass CAPINP/CAPINA to GND with 0.1uF to remove high frequency
noise. CAPOUT, CAPINA and CAPINP must be tied together.
Power supply AVDD is supposed to be stabilized with de-coupling capacitor and series noise filter (for example,
ferrite bead).
Figure 1. Connection of CAPOUT, CAPINA, CAPINP and Decoupling Capacitor
Power Down (PDN1, PDN0)
PDN1 and PDN0 turn off internal circuitry of Main-Link and Sub-Link separately.
Table 3. Power Down Setting
PDN1
0
0
1
1
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PDN0
0
1
0
1
Operation
Both Main-Link and Sub-Link power down
Only Main-Link is active
Only Sub-Link is active
Both Main-Link and Sub-Link active
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Main-Link Mode Setting
Two modes of Main-Link operation are available. Mode select is done by MAINMODE pin (when PDN1=0) or
MAINMODE register (when PDN1=1).
V-by-One® HS Mode (MAINMODE=0)
V-by-One® HS Mode is compliant with V-by-One® HS standard Version1.4. (See Figure 3 and Table 14)
Sync Free Mode (MAINMODE=1)
Incoming data can be transmitted by Sync Free Mode without DE requirement. (See Table 14)
Color Space Conversion
The THCV235 converts RGB444 to YCbCr422 and the THCV236 converts back to RGB. This function can
only be used in V-by-One® HS mode and enabled by COL1=1 setting. COL1 is external pin (when PDN1=0) or
internal register (when PDN1=1). Color space conversion coefficients are compliant with ITU-R BT.709-5.
Pre-emphasis and Drive Select Function (THCV235 only)
Pre-emphasis can equalize severe signal degradation caused by long-distance or high-speed transmission. PRE
pin or PRE register selects the strength of pre-emphasis. CMLDRV pin or CMLDRV register controls CML
Main-Link output swing level. See Table 4 and Table 5.
Table 4. Pre-emphasis and Drive Select function table (PDN1=0)
CMLDRV
(pin)
0
1
PRE
(pin)
0
1
*
Condition
Pre-emphasis Level
0dB
600mV diff p-p
3.5dB
800mV diff p-p
0dB
Swing Level
Table 5. Pre-emphasis and Drive Select function table (PDN1=1)
CMLDRV[1:0]
(register)
00
01
10
11
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PRE
(register)
0
1
0
1
*
*
Condition
Pre-emphasis Level
0dB
400mV diff p-p
6dB
0dB
600mV diff p-p
3.5dB
800mV diff p-p
0dB
Forbidden
Swing Level
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THCV235_THCV236_Rev.3.70_E
Permanent Clock Output (THCV236 only)
When there is no input from Main-Link, the THCV236 will output internal oscillator clock from CLKOUT pin.
This function is controlled by OUTSEL pin or OUTSEL_ENABLE register and OUTSEL_SETTING register.
See Table 6 and Table 7.
Table 6. Permanent Clock Output function table (PDN1=0)
Output Clock
Frequency(*1)
40MHz
OUTSEL (pin)
0
1
*1 typical value
Table 7. Permanent Clock Output function table (PDN1=1)
OUTSEL_
ENABLE
(register)
0
1
OUTSEL_
SETTING
(register)
*
00
01
10
11
Output Clock
Frequency(*1)
80MHz
40MHz(default)
20MHz
10MHz
*1 typical value
Spread Spectrum Clock Generator (SSCG)
The THCV235 serial data output and the THCV236 parallel data and clock outputs are modulated by
programmable SSCG. The THCV235 SSCG is enabled by SSEN pin or SSEN register. The THCV236 SSCG is
enabled by only SSEN register. The modulation rate and modulation frequency variation of output spread is
controlled through the SSCG control registers on each device. Do not enable spread spectrum for both the
THCV235 and THCV236 at the same time.
Table 8. SSCG enable signal (THCV235)
PDN1
0
1
SUBMODE
*
(Function as HTPDN)
0
1
Mode Entry Signal
SSEN (pin)
SSEN (register)
SSEN (pin)
Description
0:SSCG Disable
1:SSCG Enable
Table 9. SSCG enable signal (THCV236)
PDN1
SUBMODE
Mode Entry Signal
Description
*
*
SSEN(register)
0:SSCG Disable
1:SSCG Enable
When customer use the mode and frequency range shown in Table 10, register setting is required according to
Table 11.
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Table 10. Main-Link mode and frequency range requiring register setting
Mode Setting
MAINMODE
HFSEL
0
0
0
0
0
1
1
0
1
0
1
0
1
1
*1 Don’t care
*2 See Table 11
LFSEL
0
0
0
0
0
0
0
COL1
(*1)
COL0
0
1
(*1)
(*1)
0
0
1
0
1
0
(*1)
(*1)
(*1)
Freq.Range[MHz]
(SSCG Enable)
min
max
26.6
50
33.3
66.6
50
100
26.6
40
26.6
50
33.3
66.6
50
100
Register
Setting
(*2)
Case1
Case2
Case3
Case1
Case1
Case2
Case3
Table 11. SSCG register setting
Step
1
2
3
4
Register Address(HEX)
Sub-Link
Sub-Link
Master side
Slave side
0x70
0xF0
0x76
0xF6
0x78
0xF8
0x7C
0xFC
Register Value(HEX)
Case3
THCV235
THCV236
0x01
0x02
0x02
0x01
0x3C
0x30
0x20
0x35
0x34
0x24
Case1
Case2
Description
Set 1 to PLL_SET_EN
Set PLL_SET0
Set PLL_SET1
Set PLL_SET2
Modulation frequency fmod can be determined by HFSEL and LFSEL settings, input clock frequency and
FMOD register setting (default value 0xD). Refer to following formula.
f mod
f CLKSSCG
128 FMOD
fCLKSSCG is the frequency listed in Table 12 and Table 13.
Table 12. fCLKSSCG (THCV235)
HFSEL
0
0
1
1
LFSEL
0
1
0
1
fCLKSSCG
(1/tTCIP)/2
1/tTCIP
(1/tTCIP)/4
Forbidden Setting
Table 13. fCLKSSCG (THCV236)
HFSEL
0
0
1
1
LFSEL
0
1
0
1
fCLKSSCG
(1/tRCP)/2
1/tRCP
(1/tRCP)/4
Forbidden Setting
Up to 0.5 % spread at the 30kHz modulation frequency is stable for most cases. In case of using out of this
range, please verify at the actual system.
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Data Enable
0 is the conceptual diagram of the V-by-One® HS mode operation (MAINMODE=0) of the chipset.
Figure 2. Conceptual Diagram of the Basic Operation of the Chipset in V-by-One® HS mode
There are some requirements for DE. 0 shows the timing diagram of it.
Note: In V-by-One® HS Mode (MAINMODE=0) and High Frequency Mode (HFSEL=1), the period between rising edges of DE (tDEINT),
high time of DE (tDEH) should always satisfy following equations.
tDEH = tTCIP*(2m)
tDEINT = tTCIP*(2n)
m,n=2,3,4,5,6……
Figure 3. Data and Synchronizing Signals Transmission Timing Diagram in V-by-One® HS mode
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Table 14. DE Requirement
Symbol
tDEH
tDEL
Parameter
DE=1 Duration
DE=0 Duration
Condition
MAINMODE=0
HFSEL=0
MAINMODE=0
HFSEL=1
MAINMODE=1
MAINMODE=0
HFSEL=0
MAINMODE=0
HFSEL=1
MAINMODE=1
Min
Typ
Max
Unit
2×tTCIP
-
-
ns
4×tTCIP
-
-
ns
Don’t care
2×tTCIP
-
-
ns
4×tTCIP
-
-
ns
Don’t care
Hot-Plug Function
HTPDN signal indicates connecting condition between the Transmitter and the Receiver. HTPDN of the
transmitter side is high when the Receiver is not active or not connected. Then Transmitter can enter into the
power down mode. HTPDN is set to low by the Receiver when Receiver is active and connects to the
Transmitter, and then Transmitter must start up and transmit CDR training pattern for link training.
When PDN1 = 0 (Sub-Link Power Down), HTPDN is transferred to Transmitter by HTPDN pin.
HTPDN is open-drain output at the receiver side. Pull-up resistor is needed at the transmitter side.
HTPDN connection between the Transmitter and the Receiver can be omitted as an application option. In this
case, HTPDN at the Transmitter side should always be taken as low.
When PDN1 = 1 (Sub-Link Active), HTPDN is transferred to Transmitter via Sub-Link line.
HTPDN/SUBMODE pin functions as Sub-Link mode select (SUBMODE). HOST MPU can confirm HTPDN
state by reading Sub-Link Master register (0x00 bit0 HTPDN).
Lock Detect Function
LOCKN indicates whether the receiver CDR PLL is in the lock state or not. LOCKN at the Transmitter input is
set to High by pull-up resistor when Receiver is not active or at the CDR PLL training state. LOCKN is set to
low by the Receiver when CDR lock is done. Then the CDR training mode finishes and Transmitter shifts to the
normal operation.
When PDN1 = 0 (Sub-Link Power Down), LOCKN is transferred to Transmitter by LOCKN pin. LOCKN is
open-drain output at the receiver side. Pull-up resistor is needed at the transmitter side.
When HTPDN is included in an application, the LOCKN signal should only be considered when the HTPDN is
pulled low by the Receiver.
When PDN1 = 1 (Sub-Link Active), LOCKN is transferred via Sub-Link line. LOCKN/MSSEL pin functions
as Sub-Link Master/Slave select (MSSEL). HOST MPU can confirm LOCKN state by reading Sub-Link Master
register (0x00 bit1 LOCKN).
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THCV235_THCV236_Rev.3.70_E
Table 15 HTPDN,LOCKN transmission route setting
PDN1
0
1
HTPDN,LOCKN
HTPDN, LOCKN are transmitted via external DC signal.
HTPDN, LOCKN are transmitted via Sub-Link.
Figure 4. Hot-plug and Lock Detect Scheme when PDN1=0
Figure 5. HTPDN,LOCKN transmission route when PDN1=1
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Field BET Operation
In order to help users to check validity of CML serial line (Main-Link and Sub-Link), the THCV235 and
THCV236 have an operation mode in which they act as a bit error tester (BET). In Main-Link Field BET mode,
the THCV235 internally generates test pattern which is then serialized onto the Main-Link CML line. The
THCV236 also has BET function mode. The THCV236 receives the data stream and checks bit errors. The
generated data pattern is then 8b/10b encoded, scrambled, and serialized onto the CML channel. As for the
THCV236, the internal test pattern check circuit gets enabled and reports result on a certain pin named BETOUT.
In Sub-Link Field BET mode, Sub-Link Master device internally generates test pattern which is then serialized
onto the Sub-Link CML line. Sub-Link Slave device also has BET function mode. Sub-Link Slave device
receives the data stream and checks bit errors. Note that Sub-Link Slave device must be set this mode prior to
Sub-Link Master device. Pattern check result is output from BETOUT pin of the Sub-Link Slave device. The
BETOUT pin goes LOW whenever bit errors occur, or it stays HIGH when there is no bit error.
In Main-Link Field BET mode, user can select two kinds of check result, latched result or NOT latched result
by setting LATEN pin input. The latched result is reset by setting LATEN=0. In Sub-Link Field BET mode, only
latched result is available. In order to reset the latched result, please once turn off the power and entry Sub-Link
Field BET from power on sequence.
LATEN/SD3/AIN1/GPIO4 pin (THCV235) and LATEN/SD3/AIN1/GPIO0 pin (THCV236) function as
LATEN in Field BET mode (Main-Link or Sub-Link).
It is not possible to realize Main-Link Field BET and Sub-Link Field BET at the same time.
Table 16. Main-Link Field BET Operation Settings
Register value with brace (e.g. {0}) means default.
PDN0
(pin)
THCV235/236 Common
PDN1
SUBMODE
BET_SEL
(pin)
(pin)
(register)
0x53[0]
0
1
THCV235
BET
(pin) : SUBMODE=1
(register) 0x53[1] : SUBMODE=0
THCV236
BET
LATEN
(pin)
(pin)
-
0(*1)
1
1
1
0(*1)
1
1
0
{0}
1
1
1
0
1
0
1
0
1
Sub-Link
Power
Down
Normal
Operation
Condition
Output Latch
Select
Not Latched Result
Latched Result
Not Latched Result
Latched Result
Not Latched Result
Latched Result
*1 When PDN0=1, PDN1=0 and BET=1 or PDN0=1, PDN1=1, SUBMODE=1 and BET=1, BET_SEL is set to 0 automatically.
Table 17. THCV236 Main-Link Field BET Result
BETOUT
L
H
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Output
Bit Error Occurred
No Error
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Table 18. Sub-Link Field BET Operation Setting
Register value with brace (e.g. {0}) means default.
SUBMODE=1.
Common
Master
Slave
Initial
0
1
BET_SEL
(register)
0x53[0]
{0}
0
-
0
BET_SEL
(register)
0xD3[0]
{0}
1
1(*2)
1
↓
↓
↓
↓
-
↓
1(*1)
↓
↓
1
2
↓
↓
1(*1)
↓
-
1
↓
↓
↓
↓
MSSEL
(pin)
LATEN
(pin)
BET_SEL
(register)
0xD3[0]
{0}
MSSEL
(pin)
LATEN
(pin)
Step
PDN0
(pin)
PDN1
(pin)
MSSEL
(pin)
LATEN
(pin)
BET
(pin)
MSSEL
(pin)
LATEN
(pin)
BET
(pin)
0
SUBMODE=0.
Common
Master
Slave
Initial
0
1
BET_SEL
(register)
0x53[0]
{0}
0
-
BET
(pin) : THCV236
(register)0x53[1] : THCV235
0
1
1(*2)
BET
(pin) : THCV236
(register)0xD3[1] : THCV235
0
1
↓
↓
1
↓
-
↓
1
↓
↓
↓
2
↓
↓
↓
↓
-
↓
↓
↓
↓
1
3
↓
↓
↓
↓
-
1
↓
↓
↓
↓
Step
PDN0
(pin)
PDN1
(pin)
*1 When PDN0=0, PDN1=1, SUBMODE=1 and BET=1, BET_SEL is set to 1 automatically.
*2 Forbidden 0 setting
Table 19. Sub-Link Slave device Sub-Link Field BET Result
BETOUT
L
H
Output
Bit Error Occurred
No Error
Figure 6. Main-Link Field BET Configuration
Figure 7. Sub-Link Field BET Configuration
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THCV235_THCV236_Rev.3.70_E
Data Width and Frequency Range Select Function
The THCV235 and THCV236 support a variety of data width and frequency range. Frequency range is
different depending on the mode setting and SSCG enable and disable setting. Refer to Table 20 and Table 21 for
details.
Table 20. Main-Link Operation Mode Select (PDN1=1 and SUBMODE=0)
Freq.Range
[MHz]
SSCG
SSCG
Disable
Enable (*1)
Mode Setting
MAIN
MODE
0
0
0
0
0
0
0
0
0
HFSEL
LFSEL
COL1
COL0
min
max
min
max
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
0
0
0
15
20
15
20
7.5
10
7.5
10
50
70
50
70
50
70
50
70
12
15
20
6
7.5
10
50
70
50
70
50
70
-
100
133.3
100
133.3
15
20
15
20
70
160
70
160
70
160
70
160
80
100
133.3
12
15
20
70
160
70
160
70
160
-
26.6
33.3
26.6
33.3
16.4
19.2
16.4
19.2
50
70
50
70
50
70
50
70
26.6
26.6
33.3
16.4
16.4
19
50
70
50
70
50
70
-
100
133.3
100
133.3
32.5
38
32.5
38
70
160
70
160
70
160
70
160
80
100
133.3
32.6
32.6
38
70
160
70
160
70
160
-
0
1
0
0
1
0
1
0
1
0
0
1
0
1
1
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
*
0
0
1
1
0
0
1
1
*
0
1
0
1
0
1
0
1
1
1
0
0
0
1
1
0
0
1
1
1
0
1
0
1
1
1
1
0
1
1
*
1
*
Main-Link
CML
Bit Rate
Data Width
Comment
Data
Sync
x40
x30
x40
x30
x80
x60
x80
x60
32
24
32
24
32
24
32
24
3
3
3
3
3
3
3
3
x25
20
3
x20
16
3
x25
30
3
x20
24
3
x50
x40
x30
x100
x80
x60
-
35
30
22
35
30
22
-
x25
19
x20
15
x15
11
-
-
Color Space Conversion
Color Space Conversion
Color Space Conversion
Color Space Conversion
(*2)
(*2)
Color Space Conversion. (*2)
Color Space Conversion
Color Space Conversion. (*2)
Color Space Conversion
Forbidden
Forbidden
Forbidden
(*2)
(*2)
(*2)
Forbidden
Forbidden
*1 Note that register setting is required depending on the mode setting and used frequency range. See Table 10.
*2 Register setting is required. See Table 21.
Table 21. Register setting (HFSEL=1 and Frequency range is from 50MHz to 70MHz)
Step
1
2
3
4
Register Address(HEX)
Sub-Link
Sub-Link
Master side
Slave side
0x70
0xF0
0x76
0xF6
0x78
0xF8
0x7C
0xFC
Copyright©2022 THine Electronics, Inc.
Register Value(HEX)
THCV235
THCV236
0x01
0x02
0x01
0x20
0x24
22/68
Description
Set 1 to PLL_SET_EN
Set PLL_SET0
Set PLL_SET1
Set PLL_SET2
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THCV235_THCV236_Rev.3.70_E
Table 22. Main-Link Operation Mode Select (PDN1=0 or PDN1=1 and SUBMODE=1)
Freq.Range
[MHz]
Mode Setting
MAIN
MODE
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
SSCG
Disable
SSCG
Enable
(THCV235 Only)
HFSEL
LFSEL
COL1
COL0
min
max
min
max
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
*
0
0
1
1
0
0
1
1
0
0
1
1
*
0
1
0
1
0
1
0
1
0
1
0
1
*
0
1
0
1
0
1
0
1
0
1
0
1
*
15
20
15
20
7.5
10
7.5
10
70
70
70
70
12
15
20
6
7.5
10
70
70
70
-
100
133.3
100
133.3
15
20
15
20
160
160
160
160
80
100
133.3
12
15
20
160
160
160
-
50
66.6
50
66.6
16.4
19.2
16.4
19.2
100
100
100
100
40
50
66.6
16.4
16.4
19.2
100
100
100
-
100
133.3
100
133.3
32.5
38
32.5
38
160
160
160
160
80
100
133.3
32.5
32.5
38
160
160
160
-
Copyright©2022 THine Electronics, Inc.
23/68
Main-Link
CML
Bit Rate
x40
x30
x40
x30
x80
x60
x80
x60
x25
x20
x25
x20
x50
x40
x30
x100
x80
x60
x25
x20
x15
-
Data Width
Comment
Data
Sync
32
24
32
24
32
24
32
24
20
16
30
24
3
3
3
3
3
3
3
3
3
3
3
3
35
30
22
35
30
22
19
15
11
-
Color Space Conversion
Color Space Conversion
Color Space Conversion
Color Space Conversion
Color Space Conversion
Color Space Conversion
Forbidden
Forbidden
Forbidden
Forbidden
Forbidden
THine Electronics, Inc.
SC: E
THCV235_THCV236_Rev.3.70_E
Data Mapping
Table 23. V-by-One® HS Mode Data Mapping
MAINMODE
HFSEL
LFSEL
COL1
COL0
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
HSYNC
VSYNC
DE
0
0
0
0
0
R2
R3
R4
R5
R6
R7
R8
R9
G2
G3
G4
G5
G6
G7
G8
G9
B2(*1)
B3(*1)
B4(*1)
B5(*1)
B6(*1)
B7(*1)
B8(*1)
B9(*1)
CONT1
(*1,*2)
CONT2
(*1,*2)
B0(*1)
B1(*1)
G0(*1)
G1(*1)
R0(*1)
R1(*1)
HSYNC
VSYNC
DE
0
0
0
0
1
R0
R1
R2
R3
R4
R5
R6
R7
G0
G1
G2
G3
G4
G5
G6
G7
B0(*1)
B1(*1)
B2(*1)
B3(*1)
B4(*1)
B5(*1)
B6(*1)
B7(*1)
HSYNC
VSYNC
DE
0
0
0
1
0
R2
R3
R4
R5
R6
R7
R8
R9
G2
G3
G4
G5
G6
G7
G8
G9
B2(*1)
B3(*1)
B4(*1)
B5(*1)
B6(*1)
B7(*1)
B8(*1)
B9(*1)
CONT1
(*1,*2)
CONT2
(*1,*2)
B0(*1)
B1(*1)
G0(*1)
G1(*1)
R0(*1)
R1(*1)
HSYNC
VSYNC
DE
0
0
0
1
1
R0
R1
R2
R3
R4
R5
R6
R7
G0
G1
G2
G3
G4
G5
G6
G7
B0(*1)
B1(*1)
B2(*1)
B3(*1)
B4(*1)
B5(*1)
B6(*1)
B7(*1)
HSYNC
VSYNC
DE
0
0
1
0
0
R2
R3
R4
R5
R6
R7
R8
R9
G2
G3
G4
G5
G6
G7
G8
G9
B2(*1)
B3(*1)
B4(*1)
B5(*1)
B6(*1)
B7(*1)
B8(*1)
B9(*1)
CONT1
(*1,*2)
CONT2
(*1,*2)
B0(*1)
B1(*1)
G0(*1)
G1(*1)
R0(*1)
R1(*1)
HSYNC
VSYNC
DE
0
0
1
0
1
R0
R1
R2
R3
R4
R5
R6
R7
G0
G1
G2
G3
G4
G5
G6
G7
B0(*1)
B1(*1)
B2(*1)
B3(*1)
B4(*1)
B5(*1)
B6(*1)
B7(*1)
HSYNC
VSYNC
DE
0
0
1
1
0
R2
R3
R4
R5
R6
R7
R8
R9
G2
G3
G4
G5
G6
G7
G8
G9
B2(*1)
B3(*1)
B4(*1)
B5(*1)
B6(*1)
B7(*1)
B8(*1)
B9(*1)
CONT1
(*1,*2)
CONT2
(*1,*2)
B0(*1)
B1(*1)
G0(*1)
G1(*1)
R0(*1)
R1(*1)
HSYNC
VSYNC
DE
0
0
1
1
1
R0
R1
R2
R3
R4
R5
R6
R7
G0
G1
G2
G3
G4
G5
G6
G7
B0(*1)
B1(*1)
B2(*1)
B3(*1)
B4(*1)
B5(*1)
B6(*1)
B7(*1)
0
1
0
0
0
Cb/Cr2
Cb/Cr3
Cb/Cr4
Cb/Cr5
Cb/Cr6
Cb/Cr7
Cb/Cr8
Cb/Cr9
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
-
0
1
0
0
1
Cb/Cr0
Cb/Cr1
Cb/Cr2
Cb/Cr3
Cb/Cr4
Cb/Cr5
Cb/Cr6
Cb/Cr7
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
-
0
1
0
1
0
R2
R3
R4
R5
R6
R7
R8
R9
G2
G3
G4
G5
G6
G7
G8
G9
B2
B3
B4
B5
B6
B7
B8
B9
0
1
0
1
1
R0
R1
R2
R3
R4
R5
R6
R7
G0
G1
G2
G3
G4
G5
G6
G7
B0
B1
B2
B3
B4
B5
B6
B7
-
-
-
-
-
-
-
-
-
-
HSYNC
VSYNC
DE
Y0(*1)
Y1(*1)
Cb/Cr0(*1)
Cb/Cr1(*1)
HSYNC
VSYNC
DE
HSYNC
VSYNC
DE
B0
B1
G0(*1)
G1(*1)
R0(*1)
R1(*1)
HSYNC
VSYNC
DE
HSYNC
VSYNC
DE
*1 CTL bits, which are carried during DE=0 except the first pixel and the last pixel (when COL1=0) or the first 3pixels and the last 3pixels (when COL1=1).
*2 User defined data inputs (THCV235) and outputs (THCV236).
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THCV235_THCV236_Rev.3.70_E
Table 24. Sync Free Mode Data Mapping
MAINMODE
1
1
1
HFSEL
0
0
0
LFSEL
0
0
0
COL1
0
0
1
COL0
0
1
0
D0
D0
D0
D0
D1
D1
D1
D1
D2
D2
D2
D2
D3
D3
D3
D3
D4
D4
D4
D4
D5
D5
D5
D5
D6
D6
D6
D6
D7
D7
D7
D7
D8
D8
D8
D8
D9
D9
D9
D9
D10
D10
D10
D10
D11
D11
D11
D11
D12
D12
D12
D12
D13
D13
D13
D13
D14
D14
D14
D14
D15
D15
D15
D15
D16
D16
D16
D16
D17
D17
D17
D17
D18
D18
D18
D18
D19
D19
D19
D20
D20
D20
D21
D21
D21
D22
D22
D22
D23
D23
D23
D24
D24
D24
D25
D25
D25
D26
D26
D26
D27
D27
D28
D28
D29
D29
D30
D30
D31
D31
HSYNC(*1)
HSYNC
HSYNC
HSYNC
VSYNC(*1)
VSYNC
VSYNC
VSYNC
DE(*1)
DE
DE
DE
*1 Any signal as well as sync signal can be transmitted.
Copyright©2022 THine Electronics, Inc.
1
0
0
1
1
-
1
0
1
0
0
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
HSYNC
VSYNC
DE
1
0
1
0
1
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
HSYNC
VSYNC
DE
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1
0
1
1
0
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
HSYNC
VSYNC
DE
1
0
1
1
1
-
1
1
0
0
0
D0/C0
D1/C1
D2/C2
D3/C3
D4/C4
D5/C5
D6/C6
D7/C7
D8/Y0
D9/Y1
D10/Y2
D11/Y3
D12/Y4
D13/Y5
D14/Y6
D15/Y7
HSYNC
VSYNC
DE/FIELD
1
1
0
0
1
D0/RAW4
D1/RAW5
D2/RAW6
D3/RAW7
D4/RAW8
D5/RAW9
D6/RAW10
D7/RAW11
D8/RAW0
D9/RAW1
D10/RAW2
D11/RAW3
HSYNC
VSYNC
DE
1
1
0
1
0
D0/YC0
D1/YC1
D2/YC2
D3/YC3
D4/YC4
D5/YC5
D6/YC6
D7/YC7
HSYNC
VSYNC
DE
1
1
0
1
1
-
THine Electronics, Inc.
SC: E
THCV235_THCV236_Rev.3.70_E
Sub-Link Mode Setting
PDN1=1 setting makes Sub-Link active and two modes of Sub-Link operation are available. Sub-Link
operation mode is select by SUBMODE pin.
When SUBMODE=0, Sub-Link is 2-wire serial I/F Mode.
When SUBMODE=1, Sub-Link is Low Speed Data Bridge Mode.
SUBMODE must be same setting at the THCV235 and THCV236.Bi-directional communication is done
between Sub-Link Master device and Sub-Link Slave device in both modes. MSSEL pin selects Master/Slave
side of Sub-Link and 2-wire serial interface in the devices. MSSEL must be different setting at the THCV235
and THCV236. See Table 25 about Sub-Link operation mode settings.
Table 25. Sub-Link operation mode, Master/Slave Setting
SUBMODE
0
1
MSSEL
0
1
0
1
Operation Mode
2-wire serial I/F
Low Speed Data Bridge
Sub-Link
Master/Slave
Sub-Link Master (2-wire serial Slave)
Sub-Link Slave (2-wire serial Master)
Sub-Link Master
Sub-Link Slave
2-wire serial I/F Mode
2-wire serial I/F Mode enables register access, using GPIO (General Purpose Input/Output) pin and interrupt
function. Sub-Link Master device has 2-wire serial slave block and can be connected to HOST MPU, Sub-Link
Slave device has 2-wire serial master block and can be connected to remote side 2-wire serial slave devices.
HOST MPU can access register of Sub-Link Master device, Sub-Link Slave device and remote side 2-wire
serial slave devices.
2-wire serial I/F Device ID setting
AIN1 and AIN0 pins determine Device ID setting of the THCV235 and THCV236. Only Sub-Link Master
device's AIN1 and AIN0 pin works. AIN1 and AIN0 choose one of 4 addresses which give an identification
address to the THCV235 and THCV236 under 2-wire serial interface bus topology.
This Device ID is used as I2C Slave Address, while I2C Master Device connected to the Sub-Link Master
device accesses to the Sub-Link Master device.
This Device ID is also used as 2WIRE_TARGEET_DEV_ADR in the Sub-Link Master device's 0x20 Register
to set the target device ID as the Sub-Link Slave device.
Table 26. 2-wire serial I/F Device ID select (Sub-Link Master device Only)
AIN1
0
0
1
1
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AIN0
0
1
0
1
Device ID (7’h)
0x0B
0x34
0x77
0x65
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THCV235_THCV236_Rev.3.70_E
2-wire serial I/F Clock Stretching
In principle, when Sub-Link bridges 2-wire serial interface communication from Sub-Link Master to Sub-Link
Slave or remote side 2-wire serial slave devices, time lag occurs between HOST MPU side 2-wire serial access
and Sub-Link Slave internal bus access or remote side 2-wire serial access.
2WIRE_MODE (Sub-Link Master side register, 0x0F bit1-0) selects whether 2-wire serial slave of Sub-Link
Master perform clock stretching.
When 2WIRE_MODE = 00, Sub-Link Master device wait HOST MPU until Sub-Link Slave register access or
remote side 2-wire serial slave register access is completed by clock stretching.
When 2WIRE_MODE = 01, Sub-Link Master device informs HOST MPU that Sub-Link Slave register access
or remote side 2-wire serial register access has been completed by interruption (INT pin) without clock
stretching.
Figure 8. 2WIRE_MODE Operation
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THCV235_THCV236_Rev.3.70_E
Read/Write access to Sub-Link Master Register
HOST MPU can directly access Sub-Link Master’s register by 2-wire serial I/F. Register address of Sub-Link
Master is from 0x00 to 0x7F. See Register Map for more information.
Figure 9. Host to Sub-Link Master Register access configuration
Figure 10. 2-wire serial I/F write to Sub-Link Master register protocol
Figure 11. 2-wire serial I/F read to Sub-Link Master register protocol
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THCV235_THCV236_Rev.3.70_E
Read/Write access to Sub-Link Slave Register
HOST MPU can access to Sub-Link Slave’s register via Sub-Link Master by Sub-Link Master register settings.
Register address of Sub-Link Slave is from 0x80 to 0xFF. See Register Map for more information.
Figure 12. Host MPU to Sub-Link Slave Register access configuration
Table 27. Sub-Link slave register Write Procedure
Step
Description
R/W
Address
1
Write 1 or 0 and clear(auto clear) access status register (2WIRE_ACS_END_INT).
W
0x02 bit7
2
Set the data for Sub-Link Slave to write (Max 16byte).
W
0x10-0x1F
W
0x20
W
0x21
Set Device ID of Sub-Link Master device.
3
(Value corresponding to AIN1 and AIN0 setting. e.g.[AIN1,AIN0]=[0,0] → 7’h0B)
Set the byte number written to Sub-Link Slave (Max 16byte)
4
(Byte number = register value + 1)
5
Set the start address of Sub-Link Slave register to write.
W
0x23
6
Write 1 to WR_START_8B. (Start write access to Sub-Link Slave register)
W
0x25 (*1)
7
2-wire serial slave of Sub-Link Master perform clock stretching until Sub-Link Slave
-
-
-
-
R
0x02 bit7
(*2)
7
(*3)
8
register access is completed.
When write access is completed, 2WIRE_ACS_END_INT register value become 1
and interrupt occurs (INT=H → L).
If write access was normally ended, read value should be “0x1”.
*1 It’s Prohibit that HOST MPU start access to Sub-Link Slave or remote 2-wire serial slave before the previous access to
Sub-Link Slave or remote side 2-wire serial slave is completed.
*2 When 2WIRE_MODE = 00 (Clock Stretching Mode)
*3 When 2WIRE_MODE = 01 (No Clock Stretching Mode)
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THCV235_THCV236_Rev.3.70_E
Table 28. Sub-Link slave register Read Procedure
Step
1
Description
Write 1 or 0 and clear(auto clear) access status register (2WIRE_ACS_END_INT).
R/W
Address
W
0x02 bit7
W
0x20
W
0x22
Set Device ID of Sub-Link Master device.
2
(Value corresponding to AIN1 and AIN0 setting. e.g.[AIN1,AIN0]=[0,0] → 7’h0B)
Set the byte number read from Sub-Link Slave(Max 16byte).
3
(Byte number = register value + 1)
4
Set the start address of Sub-Link Slave register to read.
W
0x24
5
Write 1 to RD_START_8B. (Start read access to Sub-Link Slave register)
W
0x26 (*1)
-
-
-
-
2-wire serial slave of Sub-Link Master perform clock stretching until Sub-Link Slave
6
register access is completed. When read access is completed, SCL is released and
(*2)
read data is stored in Sub-Link Master register (Address 0x10-0x1F).
When read access is completed, read data is stored in Sub-Link Master register
6
(Address 0x10-0x1F) and 2WIRE_ACS_END_INT register value become 1 and
(*3)
interrupt occurs (INT=H → L).
7
If read access was normally ended, read value should be “0x1”.
R
0x02
8
HOST MPU read data stored in Sub-Link Master register.
R
0x10-0x1F
*1 It’s Prohibit that HOST MPU start access to Sub-Link Slave or remote 2-wire serial slave before the previous access to
Sub-Link Slave or remote side 2-wire serial slave is completed.
*2 When 2WIRE_MODE = 00 (Clock Stretching Mode)
*3 When 2WIRE_MODE = 01 (No Clock Stretching Mode)
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Read/Write access to remote side 2-wire serial slave devices connected to Sub-Link Slave Device
HOST MPU can access to remote side 2-wire serial slave register via Sub-Link Master and Sub-Link Slave by
Sub-Link Master register settings. Sub-Link Slave has 2-wire serial master block. Up to 8 devices are
connectable to 2-wire serial master of Sub-Link Slave device.
Figure 13. Host to 2-wire serial Slave devices connected to Sub-Link Slave device access configuration
Table 29. Remote side 2-wire serial slave register Write Procedure for 8bit register address
Step
Description
R/W
Address
W
0x04-0x0B
Set slave address of remote side 2-wire serial slave device (Low-order 7bits),
1
and enable this address (High-order 1bit).
2
Write 1 or 0 and clear(auto clear) access status register (2WIRE_ACS_END_INT).
W
0x02 bit7
3
Set the data for remote side 2-wire serial slave to write (Max 14byte).
W
0x10-0x1D
W
0x20
W
0x21
W
0x23
W
0x25 (*1)
-
-
-
-
Set slave address of access target 2-wire serial slave (choose the value set in
4
0x04-0x0B[6:0]), and set 0 to 0x20 bit7.
Set the byte number written to remote side 2-wire serial slave (Max 14byte).
5
(Byte number = register value + 1)
6
Set the start address of remote side 2-wire serial slave register to write.
Write 1 to WR_START_8B. (Start write access to remote side 2-wire serial slave
7
register)
8
(*2)
8
(*3)
2-wire serial slave of Sub-Link Master perform clock stretching until remote side
2-wire serial slave register access is completed.
When write access is completed, 2WIRE_ACS_END_INT register value become 1
and interrupt occurs (INT=H → L).
9
If wire access was normally ended, read value should be “0x1”.
R
0x02
10
Repeat from step2 to step9 if needed.
-
-
*1 It’s Prohibit that HOST MPU start access to Sub-Link Slave or remote 2-wire serial slave before the previous access to
Sub-Link Slave or remote side 2-wire serial slave is completed.
*2 When 2WIRE_MODE = 00 (Clock Stretching Mode)
*3 When 2WIRE_MODE = 01 (No Clock Stretching Mode)
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Table 30. Remote side 2-wire serial slave register Write Procedure for 16bit register address
Step
Description
R/W
Address
W
0x04-0x0B
Set slave address of remote side 2-wire serial slave device (Low-order 7bits),
1
and enable this address (High-order 1bit).
2
Write 1 or 0 and clear(auto clear) access status register (2WIRE_ACS_END_INT).
W
0x02 bit7
3
Set the data for remote side 2-wire serial slave to write (Max 14byte).
W
0x10-0x1D
W
0x20
W
0x21
W
0x27
W
0x28
W
0x2B (*1)
-
-
-
-
Set slave address of access target 2-wire serial slave (choose the value set in
4
0x04-0x0B[6:0]), and set 1 to 0x20 bit7.
Set the byte number written to remote side 2-wire serial slave (Max 14byte).
5
(Byte number = register value + 1)
Set the low-order bits([7:0]) of start address of remote side 2-wire serial slave register
6
to write.
Set the high-order bits([15:8]) of start address of remote side 2-wire serial slave
7
register to write.
Write 1 to WR_START_16B. (Start write access to remote side 2-wire serial slave
8
register)
9
(*2)
9
2-wire serial slave of Sub-Link Master perform clock stretching until remote side 2-wire
serial slave register access is completed.
When write access is completed, 2WIRE_ACS_END_INT register value become 1
(*3)
and interrupt occurs (INT=H → L).
10
If write access was normally ended, read value should be “0x1”.
R
0x02
11
Repeat from step2 to step10 if needed.
-
-
*1 It’s Prohibit that HOST MPU start access to Sub-Link Slave or remote 2-wire serial slave before the previous access to
Sub-Link Slave or remote side 2-wire serial slave is completed.
*2 When 2WIRE_MODE = 00 (Clock Stretching Mode)
*3 When 2WIRE_MODE = 01 (No Clock Stretching Mode)
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Table 31. Remote side 2-wire serial slave register Read Procedure for 8bit register address
Step
Description
R/W
Address
W
0x04-0x0B
W
0x02 bit7
W
0x20
W
0x22
W
0x24
W
0x26 (*1)
-
-
-
-
Set slave address of remote side 2-wire serial slave device (Low-order 7bits),
1
and enable this address (High-order 1bit).
2
Write 1 or 0 and clear(auto clear) access status register (2WIRE_ACS_END_INT).
Set slave address of access target 2-wire serial slave (choose the value set in
3
0x04-0x0B[6:0]), and set 0 to 0x20 bit7.
Set the byte number read from remote side 2-wire serial slave(Max 14byte).
4
(Byte number = register value + 1)
5
Set the start address of remote side 2-wire serial slave register to read.
Write 1 to RD_START_8B. (Start read access to remote side 2-wire serial slave
6
register)
2-wire serial slave of Sub-Link Master perform clock stretching until Sub-Link Slave
7
register access is completed. When read access is completed, SCL is released and
(*2)
read data is stored in Sub-Link Master register (Address 0x10-0x1F).
When read access is completed, read data is stored in Sub-Link Master register
7
(Address 0x10-0x1F) and 2WIRE_ACS_END_INT register value become 1 and
(*3)
interrupt occurs (INT=H → L).
8
If read access was normally ended, read value should be “0x1”.
R
0x02
9
HOST MPU read data stored in Sub-Link Master register.
R
0x10-0x1F
10
Repeat from step2 to step10 if needed.
-
-
*1 It’s Prohibit that HOST MPU start access to Sub-Link Slave or remote 2-wire serial slave before the previous access to
Sub-Link Slave or remote side 2-wire serial slave is completed.
*2 When 2WIRE_MODE = 00 (Clock Stretching Mode)
*3 When 2WIRE_MODE = 01 (No Clock Stretching Mode)
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Table 32. Remote side 2-wire serial slave register Read Procedure for 16bit register address
Step
Description
R/W
Address
W
0x04-0x0B
W
0x02 bit7
W
0x20
W
0x22
W
0x29
W
0x2A
W
0x2C (*1)
-
-
-
-
Set slave address of remote side 2-wire serial slave device (Low-order 7bits),
1
and enable this address (High-order 1bit).
2
Write 1 or 0 and clear(auto clear) access status register (2WIRE_ACS_END_INT).
Set slave address of access target 2-wire serial slave (choose the value set in
3
0x04-0x0B[6:0]), and set 1 to 0x20 bit7.
4
Set the byte number read from remote side 2-wire serial slave(Max 14byte).
Set the low-order bits([7:0]) of start address of remote side 2-wire serial slave register to
5
read.
Set the high-order bits([15:8]) of start address of remote side 2-wire serial slave register
6
to read.
Write 1 to RD_START_16B. (Start read access to remote side 2-wire serial slave
7
register)
2-wire serial slave of Sub-Link Master perform clock stretching until Sub-Link Slave
8
register access is completed. When read access is completed, SCL is released and read
(*2)
data is stored in Sub-Link Master register (Address 0x10-0x1F).
When read access is completed, read data is stored in Sub-Link Master register
8
(Address 0x10-0x1F) and 2WIRE_ACS_END_INT register value become 1 and interrupt
(*3)
occurs (INT=H → L).
9
If read access was normally ended, read value should be “0x1”.
R
0x02
10
HOST MPU read data stored in Sub-Link Master register.
R
0x10-0x1F
11
Repeat from step2 to step10 if needed.
-
-
*1 It’s Prohibit that HOST MPU start access to Sub-Link Slave or remote 2-wire serial slave before the previous access to
Sub-Link Slave or remote side 2-wire serial slave is completed.
*2 When 2WIRE_MODE = 00 (Clock Stretching Mode)
*3 When 2WIRE_MODE = 01 (No Clock Stretching Mode)
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GPIO
The GPIO pin provides up to 5-I/O ports (THCV235) or 3-I/O ports (THCV236) and 2 types of GPIO are
available (“Through GPIO” and “Programmable GPIO”). The number of available GPIO pin depends on
Sub-Link operation mode settings (See Table 34 and Table 35). All GPIO pins have another function if being set
(See Table 1, Table 2). GPIO type is selected by GPIO_TYPE register (0x40(Sub-Link Master), 0xC0(Sub-Link
Slave)). Programmable GPIO is available by all GPIO pins. Through GPIO is available by only GPIO4 and
GPIO3 pin. See Through GPIO section and Programmable GPIO section about detail of respective GPIO type.
Table 33. GPIO Type
GPIO#
GPIO4
GPIO3
GPIO2
GPIO1
GPIO0
Through GPIO
GPIO Type
Programmable GPIO
Available
Available
Unavailable
Table 34. GPIO setting of THCV235
Function
Sub-Link
Sub-Link
Master
Slave
AIN1
GPIO4
AIN0
GPIO3
INT
GPIO2
GPIO1
GPIO1
GPIO0
GPIO0
Pin Name
LATEN/SD3/AIN1/GPIO4
CMLDRV/SD2/AIN0/GPIO3
COL0/INT/GPIO2
BET/GPIO1
SSEN/GPIO0
Table 35. GPIO setting of THCV236
Pin Name
D25/GPIO4
D24/GPIO3
COL0/INT/GPIO2
TTLDRV/SD2/AIN0/GPIO1
LATEN/SD3/AIN1/GPIO0
Copyright©2022 THine Electronics, Inc.
Function
Sub-Link
Master
RXDEFSEL=0 RXDEFSEL=1
GPIO4
D25
GPIO3
D24
INT
INT
AIN0
AIN0
AIN1
AIN1
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Sub-Link
Slave
D25
D24
GPIO2
GPIO1
GPIO0
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Through GPIO
Input to GPIO4 and GPIO3 of Sub-Link Master device is output from GPIO4 and GPIO3 of Sub-Link Slave
device respectively. Note that these GPIO signals can’t be transferred from Sub-Link Slave device to Sub-Link
Master device and Through GPIO function is available only when THCV235 is Sub-Link Slave and THCV236
is Sub-Link Master and RXDEFSEL=0. Register settings are required. See Table 36.
It’s possible to confirm GPIO4 and GPIO3 input value to Sub-Link Master by register read (0x41
GPIO_INPUT_MONITOR). Each GPIO output signal goes to Low when Sub-Link communication fails.
Sub-Link communication status can be observed by register read (0x82 bit2 COMERR_INT).
When the THCV236 is Sub-Link Master and RXDEFSEL=1 (THCV236 has no GPIO4 and GPIO3 input pin as
Through GPIO), Through GPIO outputs of THCV235 (Sub-Link Slave) keep low.
*1 See Table 36
Figure 14. Through GPIO (Only GPIO4 and GPIO3)
Table 36. THCV235, THCV236(RXDEFSEL=0) Through GPIO register setting
Device
Sub-Link
Master/Slave
GPIO
Input/Output
Number
GPIO4 , GPIO3
Input/Output Configuration
(I:Input, O:Output)
Register Settings
GPIO Type
Input
Output
GPIO4
GPIO3
Address
(HEX)
GPIO IO Direction
Value
(BIN)
Address
(HEX)
Value
(BIN)
THCV235
Slave
0
2
O
O
0xC0
XXX11XXX
0xC3
XXX00XXX
THCV236
Master
2
0
I
I
0x40
XXX11XXX
0x43
XXX11XXX
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Programmable GPIO
Settings input/output and reading/writing are controlled by register settings in the Sub-Link Master. HOST
MPU commands register setting in the Sub-Link Master.
*1 See Table 37, Table 38
Figure 15. Programmable GPIO
Register settings are required according to the number of GPIO used by customer. See Table 37 and Table 38.
When the number of GPIO used by customer is less than the value listed in Table 37 and Table 38, choose any
setting which includes that.
Table 37. THCV235 Programmable GPIO register setting
Sub-Link
Master/Slave
Master
Slave
GPIO4 – GPIO0
Input/Output Configuration
(I:Input, O:Output, -:Unavailable)
GPIO
Input/Output
Number
Register Settings
GPIO Type
Input
Output
GPIO4
GPIO3
GPIO2
GPIO1
GPIO0
2
1
0
5
4
3
2
1
0
0
1
2
0
1
2
3
4
5
I
I
I
I
I
O
I
I
I
I
O
O
I
I
I
O
O
O
I
I
O
I
I
O
O
O
O
I
O
O
I
O
O
O
O
O
GPIO IO Direction
Address
(HEX)
Value
(BIN)
Address
(HEX)
0x40
XXXXXX00
0x43
0xC0
XXX00000
Value
(BIN)
XXXXXX11
XXXXXX10
XXXXXX00
XXX11111
XXX11110
XXX11100
XXX11000
XXX10000
XXX00000
0xC3
Table 38. THCV236 Programmable GPIO register setting
Sub-Link
Master/Slave
GPIO
Input/Output
Number
GPIO4 – GPIO0
Input/Output Configuration
(I:Input, O:Output, -:Unavailable)
Register Settings
GPIO Type
GPIO IO Direction
Input
Output
GPIO4
GPIO3
GPIO2
GPIO1
GPIO0
Address
(HEX)
Master
2
1
0
0
1
2
I
I
O
I
O
O
-
-
-
0x40
XXX00XXX
0x43
Slave
3
2
1
0
0
1
2
3
-
-
I
I
O
O
I
O
I
O
I
I
O
O
0xC0
XXXXX000
0xC3
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Value
(BIN)
Address
(HEX)
Value
(BIN)
XXX11XXX
XXX10XXX
XXX00XXX
XXXXX111
XXXXX101
XXXXX010
XXXXX000
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THCV235_THCV236_Rev.3.70_E
Interruption
INT pin outputs interrupt event indicator on Sub-Link Master side of the system. The INT signal is active low.
Being set by 2-wire serial interface, the THCV235 and THCV236 can monitor any changes of GPIO input pins,
Sub-Link communication statuses and internal statuses as an interrupt. About the way to make interruption occur
and the way to clear the interruption, see Table 40 (Address 0x02, 0x03) and Table 41 (Address 0x82, 0x83).
Figure 16. 2-wire serial I/F Interrupt to HOST access configuration
Table 39. Interrupt output
INT
L
H
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State
Interrupt occurred
Steady state
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Low Speed Data Bridge Mode
Low speed data input to SD2, SD1 and SD0 of Sub-Link Master device is output respectively from SD2, SD1
and SD0 of Sub-Link Slave device by LVCMOS push pull output buffer. Low speed data input to SD3 of
Sub-Link Slave device is output from SD3 of Sub-Link Master device by LVCMOS push pull output buffer.
At Low Speed Data Bridge Mode, access to register of the THCV235 and THCV236 is unable.
Figure 17. Low Speed Data Bridge Mode configuration
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Register Map
HOST MPU can set various operating conditions of the THCV235 and THCV236 through internal registers.
The THCV235 and THCV236 have two types of register address map depending upon Sub-Link configuration.
Sub-Link Master (2-wire serial slave) is connected to external HOST MPU (2-wire serial master).
Sub-Link Slave (2-wire serial master) is connected to external 2-wire serial slave devices.
Sub-Link Master device has address 0x00-0x7F, Sub-Link Slave device has address 0x80-0xFF. See Figure 18.
Figure 18. Sub-Link Master/Slave device Register Address configuration
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Table 40. Sub-Link Master Control Register
Address
(Hex)
Bit#
R/W
Default
(Hex)
0x00
7:3
R
0x00
0x01
Register Name
Note
Reserved
2
R
0
INT
1
R
1
LOCKN
0
R
1
HTPDN
7:1
R
0x00
0
RW
0
SFTRST
7
RW
0
2WIRE_ACS_END_INT
6
RW
0
LOCKN_INT
5
RW
0
HTPDN_INT
4
R
0
SLAVESIDE_INT
0x02
0x03
Description
3
R
0
GPIO_INT
2
RW
0
COMERR_INT
1
RW
0
2WIRE_TIMEOUT_INT
0
RW
0
SLINK_TIMEOUT_INT
7
R
(*2)
6
RW
0
LOCKN_INT_ENABLE
5
RW
0
HTPDN_INT_ENABLE
4
RW
0
SLAVESIDE_INT_ENABLE
3
RW
0
GPIO_INT_ENABLE
2
RW
0
COMERR_INT_ENABLE
1
RW
0
2WIRE_TIMEOUT_INT_ENABLE
0
RW
0
SLINK_TIMEOUT_INT_ENABLE
2WIRE_ACS_END_INT_ENABLE
*1
These registers are always active independent of Interrupt permission register.
*2
When No clock stretching mode, the value is 1 fixed, otherwise 0 fixed.
Copyright©2022 THine Electronics, Inc.
-
Interrupt condition
0: Steady state
1: Interrupt occurred(INT output =L)
V-by-One® HS lock status
0: Locked (LOCKN=L)
1: Unlocked
V-by-One® HS plug status
0: Connected (HTPDN=L)
1: Not connected or Rx inactive
Reserved
Sub-Link soft reset
Write 1: Sub-Link reset
Automatically cleared into 0 after reset action. 0 is always read.
Cause of interrupt access completion to register of Sub-Link Slave or
Remote side 2-wire serial Slave device
0: Access incomplete
1: Access complete
Any write action: clear this bit into 0
Cause of interrupt LOCKN
0: No change on lock status ever
1: Lock status has once changed
Any write action: clear this bit into 0
Cause of interrupt HTPDN
0: No change on plug status ever
1: Plug status has once changed
Any write action: clear this bit into 0
Cause of interrupt Sub-Link Slave side
0: No interrupt at Sub-Link Slave ever
1: Interrupted at Sub-Link Slave once
This bit is cleared when cause of interrupt register at Sub-Link Slave (0x82)
is cleared.
Cause of interrupt Sub-Link Master GPIO
0: No change in Master GPIO inputs ever
1: Master GPIO inputs have once changed.
This bit is cleared when GPIOn_INPUT_MONITOR (n=4~0) register (0x41)
is read.
Cause of interrupt Sub-Link communication Error
0: No communication error on Sub-Link ever
1: Communication error on Sub-Link once happened
Any write action: clear this bit into 0
Cause of interrupt 2-wire serial time out
0: 2-wire serial access in time ever
1: 2-wire serial access has once had time out
Any write action: clear this bit into 0
Cause of interrupt Sub-Link time out
0: Sub-Link access in time ever
1: Sub-Link has once had time out
Any write action: clear this bit into 0
0: "2WIRE_ACS_END_INT" is blocked to take interrupt action
1: "2WIRE_ACS_END_INT" is allowed to take action on INT output
0: "LOCKN_INT" is blocked to take interrupt action
1: "LOCKN_INT" is allowed to take action on INT output
0: "HTPDN_INT" is blocked to take interrupt action
1: "HTPDN_INT" is allowed to take action on INT output
0: "SLAVESIDE_INT" is blocked to take interrupt action
1: "SLAVESIDE_INT" is allowed to take action on INT output
0: "GPIO_INT" is blocked to take interrupt action
1: "GPIO_INT" is allowed to take action on INT output
0: "COMERR_INT" is blocked to take interrupt action
1: "COMERR_INT" is allowed to take action on INT output
0: "2WIRE_TIMEOUT_INT" is blocked to take interrupt action
1: "2WIRE_TIMEOUT_INT" is allowed to take action on INT output
0: "SLINK_TIMEOUT_INT" is blocked to take interrupt action
1: "SLINK_TIMEOUT_INT" is allowed to take action on INT output
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-
-
-
(*1)
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Table 40. Sub-Link Master Control Register (continued)
Address
(Hex)
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D-0x3F
*3
Bit#
R/W
Default
(Hex)
Register Name
Description
Note
0: Value in "2WIRE_DEV_ADDR_0" is inactive
1: Value in "2WIRE_DEV_ADDR_0" is active
6:0
RW
0x00
2WIRE_DEV_ADDR_0
Remote side 2-wire serial Slave Device Address #0
0: Value in "2WIRE_DEV_ADDR_1" is inactive
7
RW
0
2WIRE_DEV_ADDR_1_ENABLE
1: Value in "2WIRE_DEV_ADDR_1" is active
6:0
RW
0x00
2WIRE_DEV_ADDR_1
Remote side 2-wire serial Slave Device Address #1
0: Value in "2WIRE_DEV_ADDR_2" is inactive
7
RW
0
2WIRE_DEV_ADDR_2_ENABLE
1: Value in "2WIRE_DEV_ADDR_2" is active
6:0
RW
0x00
2WIRE_DEV_ADDR_2
Remote side 2-wire serial Slave Device Address #2
0: Value in "2WIRE_DEV_ADDR_3" is inactive
7
RW
0
2WIRE_DEV_ADDR_3_ENABLE
1: Value in "2WIRE_DEV_ADDR_3" is active
6:0
RW
0x00
2WIRE_DEV_ADDR_3
Remote side 2-wire serial Slave Device Address #3
0: Value in "2WIRE_DEV_ADDR_4" is inactive
7
RW
0
2WIRE_DEV_ADDR_4_ENABLE
1: Value in "2WIRE_DEV_ADDR_4" is active
6:0
RW
0x00
2WIRE_DEV_ADDR_4
Remote side 2-wire serial Slave Device Address #4
0: Value in "2WIRE_DEV_ADDR_5" is inactive
7
RW
0
2WIRE_DEV_ADDR_5_ENABLE
1: Value in "2WIRE_DEV_ADDR_5" is active
6:0
RW
0x00
2WIRE_DEV_ADDR_5
Remote side 2-wire serial Slave Device Address #5
0: Value in "2WIRE_DEV_ADDR_6" is inactive
7
RW
0
2WIRE_DEV_ADDR_6_ENABLE
1: Value in "2WIRE_DEV_ADDR_6" is active
6:0
RW
0x00
2WIRE_DEV_ADDR_6
Remote side 2-wire serial Slave Device Address #6
0: Value in "2WIRE_DEV_ADDR_7" is inactive
7
RW
0
2WIRE_DEV_ADDR_7_ENABLE
1: Value in "2WIRE_DEV_ADDR_7" is active
6:0
RW
0x00
2WIRE_DEV_ADDR_7
Remote side 2-wire serial Slave Device Address #7
7:0
RW
0x00
Reserved
7:0
R
0x00
Reserved
7:2
R
0x00
Reserved
1:0
RW
0x0
Reserved. Must be 0
7:2
R
0x00
Reserved
00: clock stretching mode
01: No clock stretching mode
1:0
RW
0x1
2WIRE_MODE
10: Reserved (Forbidden)
11: Reserved (Forbidden)
7:0
RW
0x00
2WIRE_DATA0
2-wire serial I/F Write/Read Data #0
7:0
RW
0x00
2WIRE_DATA1
2-wire serial I/F Write/Read Data #1
7:0
RW
0x00
2WIRE_DATA2
2-wire serial I/F Write/Read Data #2
7:0
RW
0x00
2WIRE_DATA3
2-wire serial I/F Write/Read Data #3
7:0
RW
0x00
2WIRE_DATA4
2-wire serial I/F Write/Read Data #4
7:0
RW
0x00
2WIRE_DATA5
2-wire serial I/F Write/Read Data #5
7:0
RW
0x00
2WIRE_DATA6
2-wire serial I/F Write/Read Data #6
7:0
RW
0x00
2WIRE_DATA7
2-wire serial I/F Write/Read Data #7
7:0
RW
0x00
2WIRE_DATA8
2-wire serial I/F Write/Read Data #8
7:0
RW
0x00
2WIRE_DATA9
2-wire serial I/F Write/Read Data #9
7:0
RW
0x00
2WIRE_DATA10
2-wire serial I/F Write/Read Data #10
7:0
RW
0x00
2WIRE_DATA11
2-wire serial I/F Write/Read Data #11
7:0
RW
0x00
2WIRE_DATA12
2-wire serial I/F Write/Read Data #12
7:0
RW
0x00
2WIRE_DATA13
2-wire serial I/F Write/Read Data #13
7:0
RW
0x00
2WIRE_DATA14
2-wire serial I/F Write/Read Data #14
7:0
RW
0x00
2WIRE_DATA15
2-wire serial I/F Write/Read Data #15
Remote side 2-wire Slave device's Register Address bit width select
7
RW
0
2WIRE_ADR_SEL
0: 8bit Register Address
1: 16bit Register Address
6:0
RW
0x00
2WIRE_TARGET_DEV_ADR
2-wire serial I/F Access Target Device Address setting
7:4
R
0x0
Reserved
2-wire serial I/F Write Request Byte Number for both 8bit and 16bit Register
3:0
RW
0x0
WR_REQ_BYTE
Address device. Byte Number = register value + 1 (e.g. 0x2 for 3byte burst)
7:4
R
0x0
Reserved
2-wire serial I/F Read Request Byte Number for both 8bit and 16bit Register
3:0
RW
0x0
RD_REQ_BYTE
Address device. Byte Number = register value + 1 (e.g. 0x2 for 3byte burst)
7:0
RW
0x00
WR_START_ADR_8B
2-wire serial I/F Write Start Register Address for 8bit Register Address device
7:0
RW
0x00
RD_START_ADR_8B
2-wire serial I/F Read Start Register Address for 8bit Register Address device
7:1
R
0x00
Reserved
0
RW
0
WR_START_8B
2-wire serial I/F Write Access Start Trigger for 8bit Register Address device
7:1
R
0x00
Reserved
0
RW
0
RD_START_8B
2-wire serial I/F Read Access Start Trigger for 8bit Register Address device
2-wire serial I/F Write Start Register Address(Low-order bits = [7:0]) for 16bit
7:0
RW
0x00
WR_START_ADR_16B_0
Register Address device
2-wire serial I/F Write Start Register Address(High-order bits = [15:8]) for 16bit
7:0
RW
0x00
WR_START_ADR_16B_1
Register Address device
2-wire serial I/F Read Start Register Address(Low-order bits = [7:0]) for 16bit
7:0
RW
0x00
RD_START_ADR_16B_0
Register Address device
2-wire serial I/F Read Start Register Address(High-order bits = [15:8]) for 16bit
7:0
RW
0x00
RD_START_ADR_16B_1
Register Address device
7:1
R
0x00
Reserved
0
RW
0
WT_START_16B
2-wire serial I/F Write Access Start Trigger for 16bit Register Address device
7:1
R
0x00
Reserved
0
RW
0
RD_START_16B
2-wire serial I/F Read Access Start Trigger for 16bit Register Address device
7:0
R
0x00
Reserved
Assignment of 2-wire serial slave device address connected to Sub-Link Slave outside
7
RW
0
2WIRE_DEV_ADDR_0_ENABLE
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(*3)
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Table 41. Sub-Link Slave Control Register
Address
(Hex)
0x80
0x81
Bit#
R/W
Default
(Hex)
7:0
7:1
R
R
0x00
0x00
0
RW
0
7:6
R
0x0
5
RW
0
2WIRE_RST_END_INT
4
RW
0
2WIRE_NACK_INT
3
R
0
GPIO_INT
2
RW
0
COMERR_INT
1
RW
0
2WIRE_TIMEOUT_INT
0
RW
0
SLINK_TIMEOUT_INT
7:6
R
0x0
5
RW
0
2WIRE_RST_ENABLED_INT_ENABLE
4
RW
0
2WIRE_NACK_INT_ENABLE
3
RW
0
GPIO_INT_ENABLE
2
RW
0
COMERR_INT_ENABLE
1
RW
0
2WIRE_TIMEOUT_INT_ENABLE
0
RW
0
SLINK_TIMEOUT_INT_ENABLE
7:0
R
0x00
7
R
0
6:0
RW
0x2D
7
R
0
6:0
RW
0x37
7:2
1:0
7:2
1:0
R
RW
R
RW
0x00
0x0
0x00
0x1
7:0
R
0x00
Name
2WIRE_RST
0x82
0x83
0x84
-0x8B
0x8C
0x8D
0x8E
0x8F
0x90
-0xBF
*1
Description
Note
Reserved
Reserved
2-wire serial I/F reset
Write 1: 16 pulse SCL signal is sent to 2-wire serial slave device
connected to Sub-Link Slave.
This bit is a remedy against SDA=L, 2-wire serial stuck condition.
Automatically cleared into 0 after reset action.0 is always read.
Reserved
Cause of interrupt 2-wire serial reset done
0: Normal operation
1: 2-wire serial reset signal has all finished
Any write action: clear this bit into 0
Cause of interrupt 2-wire serial Slave NACK
0: No NACK from remote side 2-wire serial slave ever
1: NACK from remote side 2-wire serial slave once come
Any write action: clear this bit into 0
Cause of interrupt Sub-Link Slave GPIO
0: No change in Slave GPIO inputs ever
1: Slave GPIO inputs have once changed.
This bit is cleared when GPIOn_INPUT_MONITOR (n=4~0) register
(0xC1) is read.
Cause of interrupt Sub-Link communication Error
0: No communication error on Sub-Link ever
1: Communication error on Sub-Link once happened
Any write action: clear this bit into 0
Cause of interrupt 2-wire serial time out
0: 2-wire serial access in time ever
1: 2-wire serial access has once had time out
Any write action: clear this bit into 0
Cause of interrupt Sub-Link time out0: Sub-Link access in time ever
1: Sub-Link has once had time out
Any write action: clear this bit into 0
Reserved
0: "2WIRE_RST_END_INT" is blocked to be reported to Master Side.
1: "2WIRE_RST_END_INT" is allowed to be reported to Master Side.
0: "2WIRE_NACK_INT" is blocked to be reported to Master Side.
1: "2WIRE_NACK_INT" is allowed to be reported to Master Side.
0: "GPIO_INT" is blocked to be reported to Master Side.
1: "GPIO_INT" is allowed to be reported to Master Side.
0: "COMERR_INT" is blocked to be reported to Master Side.
1: "COMERR_INT" is allowed to be reported to Master Side.
0: "2WIRE_TIMEOUT_INT" is blocked to be reported to Master Side.
1: "2WIRE_TIMEOUT_INT" is allowed to be reported to Master Side.
0: "SLINK_TIMEOUT_INT" is blocked to be reported to Master Side.
1: "SLINK_TIMEOUT_INT" is allowed to be reported to Master Side.
-
-
-
-
-
-
-
-
(*1)
Reserved
SCL_W_H
SCL_W_L
-
Reserved
SCL High width [tHIGH] setting. Output SCL High width is defined as below.
((SCL_W_H + 1) * 8 + 8) * tOSC
Reserved
SCL Low width [tLOW ] setting. Output SCL Low width is defined as below.
((SCL_W_L + 1) * 8 + 8) * tOSC
Reserved
Reserved. Must be 0
Reserved
Reserved
Reserved
43/68
-
Interrupt signal from Sub-Link Slave is reported to Sub-Link Master as Cause of interrupt Sub-Link Slave Side (0x02 bit4 SLAVESIDE_INT).
Copyright©2022 THine Electronics, Inc.
-
THine Electronics, Inc.
SC: E
THCV235_THCV236_Rev.3.70_E
Table 42 THCV235 GPIO Control Register Map
Address (Hex)
Sub-Link
Sub-Link
Master
Slave
0x40
0xC0
0x41
0x42
0x43
0x44
*1
*2
*3
0xC1
0xC2
0xC3
0xC4
R/W
Default
(Hex)
7:5
R
0x0
4
RW
1
GPIO4_TYPE
3
RW
1
GPIO3_TYPE
2
R
0
GPIO2_TYPE
1
R
0
GPIO1_TYPE
0
R
0
GPIO0_TYPE
7:5
4
3
2
1
0
7:5
4
3
2
1
0
7:5
R
R
R
R
R
R
R
RW
RW
RW
RW
RW
R
0x0
0
0
0
0
0
0x0
0
0
0
0
0
0x0
4:0
RW
0x07
7:5
R
0x0
4
RW
1
GPIO4_FILT_ENABLE
3
RW
1
GPIO3_FILT_ENABLE
2
RW
1
GPIO2_FILT_ENABLE
1
RW
1
GPIO1_FILT_ENABLE
0
RW
1
GPIO0_FILT_ENABLE
Bit#
Name
GPIO4_INPUT_MONITOR
GPIO3_INPUT_MONITOR
GPIO2_INPUT_MONITOR
GPIO1_INPUT_MONITOR
GPIO0_INPUT_MONITOR
GPIO4_OUT
GPIO3_OUT
GPIO2_OUT
GPIO1_OUT
GPIO0_OUT
GPIO_IO_SEL
Description
Note
Reserved
GPIO4 type select
0: Programmable GPIO
1: Through GPIO
GPIO3 type select
0: Programmable GPIO
1: Through GPIO
GPIO2 type select
0: Programmable GPIO
0 Fix
GPIO1 type select
0: Programmable GPIO
0 Fix
GPIO0 type select
0: Programmable GPIO
0 Fix
Reserved
GPIO4 input value
GPIO3 input value
GPIO2 input value
GPIO1 input value
GPIO0 input value
Reserved
GPIO4 output value setting
GPIO3 output value setting
GPIO2 output value setting
GPIO1 output value setting
GPIO0 output value setting
Reserved
GPIO input/output direction setting
See Table 36, Table 37 and Table 38
Reserved
GPIO4 input filter enable
0: Disable
1: Enable
GPIO3 input filter enable
0: Disable
1: Enable
GPIO2 input filter enable
0: Disable
1: Enable
GPIO1 input filter enable
0: Disable
1: Enable
GPIO0 input filter enable
0: Disable
1: Enable
-
-
-
-
-
(*1)
(*2)
-
(*3)
Active only when GPIO is set as input port.
Active only when GPIO type is set as "Programmable GPIO" and set as output port.
Filter eliminates input glitch shorter than tOSC/2.
Copyright©2022 THine Electronics, Inc.
44/68
THine Electronics, Inc.
SC: E
THCV235_THCV236_Rev.3.70_E
Table 42 THCV235 GPIO Control Register Map (continued)
Address (Hex)
Sub-Link
Sub-Link
Master
Slave
0x45
0xC5
0x46
0x47
-0x4F
*4
0xC6
Bit#
R/W
Default
(Hex)
7:5
R
0x0
4
RW
1
GPIO4_INT_ENABLE
3
RW
1
GPIO3_INT_ENABLE
2
RW
1
GPIO2_INT_ENABLE
1
RW
1
GPIO1_INT_ENABLE
GPIO0_INT_ENABLE
Name
Description
0
RW
1
7:5
R
0x0
4
RW
0
GPIO4_OUTBUF_SEL
3
RW
0
GPIO3_OUTBUF_SEL
2
RW
0
GPIO2_OUTBUF_SEL
1
RW
0
GPIO1_OUTBUF_SEL
0
RW
0
GPIO0_OUTBUF_SEL
0xC7
7:0
R
0x00
-0xCF
GPIO input transition is counted as GPIO_INT(0x02 or 0x82 bit3).
Copyright©2022 THine Electronics, Inc.
Note
Reserved
GPIO4 interrupt enable
0: Disable
1: Enable
GPIO3 interrupt enable
0: Disable
1: Enable
GPIO2 interrupt enable
0: Disable
1: Enable
GPIO1 interrupt enable
0: Disable
1: Enable
GPIO0 interrupt enable
0: Disable
1: Enable
Reserved
GPIO4 output buffer select
0: GPIO4 is open-drain output
1: GPIO4 is push pull output
GPIO3 output buffer select
0: GPIO3 is open-drain output
1: GPIO3 is push pull output
GPIO2 output buffer select
0: GPIO2 is open-drain output
1: GPIO2 is push pull output
GPIO1 has only open-drain output buffer. Must be 0 setting
0: GPIO1 is open-drain output
GPIO0 has only open-drain output buffer. Must be 0 setting
0: GPIO0 is open-drain output
-
(*4)
-
-
-
Reserved
45/68
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SC: E
THCV235_THCV236_Rev.3.70_E
Table 43. THCV235 Main-Link Control Register Map
Address (Hex)
Sub-Link
Sub-Link
Master
Slave
0x50
0xD0
0x51
0x52
0x53
0xD1
0xD2
0xD3
0x54
0xD4
0x55
-0x6C
0x6D
0xD5
-0xEC
0xED
0x6E
0xEE
0x6F
0x70
0xEF
0xF0
0x71
-0x75
0x76
0xF1
-0xF5
0xF6
0x77
0xF7
0x78
0x79
-0x7B
0x7C
0xF8
0xF9
-0xFB
0xFC
0x7D
-0x7F
*1
*2
*3
Bit#
R/W
Default
(Hex)
7
RW
0
MAINMODE
6
RW
0
HFSEL
5
RW
0
COL1
4
RW
0
COL0
3
RW
0
PRE
2:1
RW
0x2
0
7:6
RW
R
0
0x0
5
RW
0
4:0
RW
0x05
SPREAD
7:4
3:0
7:2
R
RW
R
0x0
0xD
0x00
FMOD
1
RW
0
BET
0
RW
0
BET_SEL
7
6:0
R
RW
0
0x3E
MAINMODE setting
0: V-by-One® HS Mode
1: Sync Free Mode
HFSEL setting
0: High Frequency Mode Disable
1: High Frequency Mode Enable
COL1 setting
when MAINMODE =0
0: Color Space Converter Disable
1: Color Space Converter Enable
when MAINMODE =1
Data Width Setting. See Table 20.
COL0 setting
Data Width Setting. See Table 20.
PRE setting
0: Pre-Emphasis Disable
1: Pre-Emphasis Enable
CMLDRV setting
00: 400mV diff p-p
01: 600mV diff p-p
10: 800mV diff p-p
11: Reserved (Forbidden)
Reserved
Reserved
SSEN setting
0: SSCG Disable
1: SSCG Enable
SSCG modulation depth setting
Spread depth = ±SPREAD x 0.1% (Center Spread)
Reserved
SSCG Modulation Frequency setting
Reserved
Field BET Mode Enable setting
0: Normal Mode
1: Field BET Operation
Main-Link / Sub-Link Field BET Mode select
0: Main-Link Field BET Mode
1: Sub-Link Field BET Mode
Reserved
Reserved. Must be default setting.
7:0
RW
0x00
Reserved
7:3
2:0
7:1
0
7:0
7:2
1
R
RW
R
RW
R
R
RW
0x00
0x1
0x00
1
0x00
0x00
0
0
RW
0
7:0
R
0x00
Reserved
7:6
5:0
7:4
3:0
7:0
R
RW
R
RW
RW
0x0
0xXX
0x0
0x0
0xXX
Reserved
7:0
RW
0x00
Reserved. Must be default setting.
7:6
5:0
R
RW
0x0
0xXX
Reserved.
Name
CMLDRV
SSEN
PLL_SET_EN
Description
SSCG PLL setting
PLL_SET1
Reserved
Reserved. Must be default setting.
SSCG PLL setting
-
-
-
(*1)
-
(*2)
-
(*3)
(*3)
-
SSCG PLL setting
0xFD
7:0
RW
0xXX
-0xFF
See Table 4 and Table 5
SSEN=1 and SPREAD=0 setting is forbidden
See Table 11, Table 21
Copyright©2022 THine Electronics, Inc.
-
Reserved
Reserved
Reserved
Reserved. Must be 1
Reserved
Reserved
Reserved. Must be 0
SSCG PLL setting register Enable
1: Enable
0: Disable
PLL_SET0
PLL_SET2
Note
(*3)
Reserved. Must be default setting.
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THine Electronics, Inc.
SC: E
THCV235_THCV236_Rev.3.70_E
Table 44. THCV236 GPIO Control Register Map
Address (Hex)
Sub-Link
Sub-Link
Master
Slave
0x40
0xC0
0x41
0x42
0x43
0x44
*1
*2
*3
*4
*5
*6
0xC1
0xC2
0xC3
0xC4
Bit#
R/W
Default
(Hex)
7:5
R
0x0
4
RW
1
GPIO4_TYPE
3
RW
1
GPIO3_TYPE
2
R
0
GPIO2_TYPE
1
R
0
GPIO1_TYPE
GPIO0_TYPE
Name
0
R
0
7:5
4
3
2
1
0
7:5
4
3
2
1
0
7:5
4
3
2:0
7:5
R
R
R
R
R
R
R
RW
RW
RW
RW
RW
R
RW
RW
RW
R
0x0
0
0
0
0
0
0x0
0
0
0
0
0
0x0
4
RW
1
GPIO4_FILT_ENABLE
3
RW
1
GPIO3_FILT_ENABLE
2
RW
1
GPIO0_FILT_ENABLE(*6)
1
RW
1
GPIO1_FILT_ENABLE
0
RW
1
GPIO2_FILT_ENABLE(*6)
(*4)
(*4)
Description
GPIO4_INPUT_MONITOR
GPIO3_INPUT_MONITOR
GPIO0_INPUT_MONITOR(*2)
GPIO1_INPUT_MONITOR
GPIO2_INPUT_MONITOR(*2)
GPIO4_OUT
GPIO3_OUT
GPIO2_OUT
GPIO1_OUT
GPIO0_OUT
GPIO_IO_SEL
0x7
0x0
Note
Reserved
GPIO4 type select
0: Programmable GPIO
1: Through GPIO
GPIO3 type select
0: Programmable GPIO
1: Through GPIO
GPIO2 type select
0: Programmable GPIO
0 Fix
GPIO1 type select
0: Programmable GPIO
0 Fix
GPIO0 type select
0: Programmable GPIO
0 Fix
Reserved
GPIO4 input value
GPIO3 input value
GPIO0 input value
GPIO1 input value
GPIO2 input value
Reserved
GPIO4 output value setting
GPIO3 output value setting
GPIO2 output value setting
GPIO1 output value setting
GPIO0 output value setting
Reserved
-
-
-
-
-
(*1)
-
(*3)
-
GPIO input/output direction setting
See Table 36, Table 37 and Table 38
-
Reserved
GPIO4 input filter enable
0: Disable
1: Enable
GPIO3 input filter enable
0: Disable
1: Enable
GPIO0 input filter enable
0: Disable
1: Enable
GPIO1 input filter enable
0: Disable
1: Enable
GPIO2 input filter enable
0: Disable
1: Enable
-
(*5)
Active only when GPIO is set as input port.
Note that GPIO2_INPUT_MONITOR corresponds to Bit#”0”, GPIO0_INPUT_MONITOR corresponds to Bit#”2”.
Active only when GPIO type is set as "Programmable GPIO" and set as output port.
Default value depends on RXDEFSEL setting when Power on sequence. RXDEFSEL=1 → default value is 0, RXDEFSEL=0 → default value is 1.
Filter eliminates input glitch shorter than tOSC/2.
Note that GPIO2_FILT_ENABLE corresponds to Bit#”0”, GPIO0_FILT_ENABLE corresponds to Bit#”2”.
Copyright©2022 THine Electronics, Inc.
47/68
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SC: E
THCV235_THCV236_Rev.3.70_E
Table 44. THCV236 GPIO Control Register Map (continued)
Address (Hex)
Sub-Link
Sub-Link
Master
Slave
0x45
0xC5
0x46
0x47
-0x4F
*7
*8
0xC6
R/W
Default
(Hex)
7:5
R
0x0
4
RW
1
GPIO4_INT_ENABLE
3
RW
1
GPIO3_INT_ENABLE
2
RW
1
GPIO0_INT_ENABLE(*8)
1
RW
1
GPIO1_INT_ENABLE
0
RW
1
GPIO2_INT_ENABLE(*8)
7:5
R
0x0
4
RW
0
GPIO4_OUTBUF_SEL
3
RW
0
GPIO3_OUTBUF_SEL
2
RW
0
GPIO2_OUTBUF_SEL
1
RW
0
GPIO1_OUTBUF_SEL
0
RW
0
GPIO0_OUTBUF_SEL
Bit#
Name
Description
Note
Reserved
GPIO4 interrupt enable
0: Disable
1: Enable
GPIO3 interrupt enable
0: Disable
1: Enable
GPIO0 interrupt enable
0: Disable
1: Enable
GPIO1 interrupt enable
0: Disable
1: Enable
GPIO2 interrupt enable
0: Disable
1: Enable
Reserved
GPIO4 output buffer select
0: GPIO4 is open-drain output
1: GPIO4 is push pull output
GPIO3 output buffer select
0: GPIO3 is open-drain output
1: GPIO3 is push pull output
GPIO2 output buffer select
0: GPIO2 is open-drain output
1: GPIO2 is push pull output
GPIO1 output buffer select
0: GPIO1 is open-drain output
1: GPIO1 is push pull output
GPIO0 output buffer select
0: GPIO0 is open-drain output
1: GPIO0 is push pull output
-
(*7)
-
-
-
-
-
0xC7
7:0
R
0x00
Reserved
-0xCF
GPIO input transition is counted as GPIO_INT(0x02 or 0x82 bit3).
Note that GPIO2_INT_ENABLE corresponds to Bit#”0”, GPIO0_INT_ENABLE corresponds to Bit#”2”.
Copyright©2022 THine Electronics, Inc.
48/68
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SC: E
THCV235_THCV236_Rev.3.70_E
Table 45. THCV236 Main-Link Control Register Map
Address (Hex)
Sub-Link
Master
0x50
0x51
0x52
0x53
Sub-Link
Slave
0xD0
0xD1
0xD2
0xD3
0x54
0xD4
0x55
-0x6C
0x6D
0xD5
-0xEC
0xED
0x6E
0xEE
0x6F
0x70
0xEF
0xF0
0x71
-0x75
0x76
0xF1
-0xF5
0xF6
0x77
0xF7
0x78
0x79
-0x7B
0x7C
0xF8
0xF9
-0xFB
0xFC
0x7D
-0x7F
*1
*2
*3
*4
Bit#
R/W
Default
(Hex)
7
RW
(*1)
MAINMODE
6
RW
(*1)
HFSEL
5
RW
0
COL1
4
RW
(*1)
COL0
3
2:1
RW
RW
0
0x0
Name
TTLDRV
Description
MAINMODE setting
0: V-by-One® HS Mode
1: Sync Free Mode
HFSEL setting
0: High Frequency Mode Disable
1: High Frequency Mode Enable
COL1 setting
when MAINMODE =0
0: Color Space Converter Disable
1: Color Space Converter Enable
when MAINMODE =1
Data Width Setting. See Table 20.
COL0 setting
Data Width Setting. See Table 20.
Reserved
Reserved
TTLDRV setting
0: Weak Drive Strength
1: Normal Drive Strength
Reserved
SSEN setting
0: SSCG Disable
1: SSCG Enable
SSCG modulation depth setting
Spread depth = ±SPREAD x 0.1% (Center Spread)
Reserved
SSCG Modulation Frequency setting
Reserved
Reserved
Main-Link / Sub-Link Field BET Mode select
0: Main-Link Field BET Mode
1: Sub-Link Field BET Mode
Reserved
Reserved. Must be default setting.
0
RW
0
7:6
R
0x0
5
RW
0
4:0
RW
0x05
7:4
3:0
7:2
1
R
RW
R
RW
0x0
0xD
0x00
0
0
RW
0
7
6:0
R
RW
0
0x3E
7:0
RW
0x00
7:3
R
0x00
2
RW
0
OUTSEL_ENABLE
1:0
RW
0x1
OUTSEL_SETTING
7:1
0
7:0
7:2
1
R
RW
R
R
RW
0x00
1
0x00
0x00
0
0
RW
0
7:0
R
0x00
Reserved
7:6
5:0
7:4
3:0
7:0
R
RW
R
RW
RW
0x0
0xXX
0x0
0x0
0xXX
Reserved
7:0
RW
0x00
Reserved. Must be default setting.
7:6
5:0
R
RW
0x0
0xXX
Reserved.
SSEN
SPREAD
FMOD
BET_SEL
Note
-
-
-
-
(*2)
-
Reserved
PLL_SET_EN
PLL_SET0
SSCG PLL setting
PLL_SET1
Reserved
Reserved. Must be default setting.
SSCG PLL setting
PLL_SET2
-
Reserved
Permanent Clock Output Enable setting
0: Permanent Clock Output Disable
1: Permanent Clock Output Enable
Permanent Clock Frequency setting
00: 80MHz (Clock Period : tOSC)
01: 40MHz (Clock Period : tOSC/2)
10: 20MHz (Clock Period : tOSC/4)
11: 10MHz (Clock Period : tOSC/8)
Reserved
Reserved. Must be 1
Reserved
Reserved
Reserved. Must be 0
SSCG PLL setting register Enable
1: Enable
0: Disable
-
(*3)
(*4)
(*4)
-
SSCG PLL setting
(*4)
0xFD
7:0
RW
0xXX
Reserved. Must be default setting.
-0xFF
Default value depends on RXDEFSEL setting when Power on sequence. RXDEFSEL=1 → default value is 0, RXDEFSEL=0 → default value is 1.
SSEN=1 and SPREAD=0 setting is forbidden.
Described value is typical value. It has variation in the range from min spec value to max spec value of tOSC.
See Table 11, Table 21
Copyright©2022 THine Electronics, Inc.
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SC: E
-
THCV235_THCV236_Rev.3.70_E
Absolute Maximum Ratings
Table 46. Absolute Maximum Ratings
Parameter
Supply Voltage(VDD,AVDD)
LVCMOS Input Voltage
LVCMOS Output Voltage
LVCMOS Bi-directional buffer Input Voltage
LVCMOS Bi-directional buffer Output Voltage
Open-Drain Output Voltage
CML Receiver Input Voltage
CML Transmitter Output Voltage
CML Bi-directional buffer Input Voltage
CML Bi-directional buffer Output Voltage
Output Current
Storage temperature
Junction temperature
Reflow Peak Temperature/Time
Maximum Power Dissipation @+25°C
Min
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-50
-55
-
Typ
-
Max
4.0
VDD+0.3
VDD+0.3
VDD+0.3
VDD+0.3
4.0
CAPINA+0.3
CAPINA+0.3
VDD+0.3
VDD+0.3
50
125
125
260/10
3.9
Unit
V
V
V
V
V
V
V
V
V
V
mA
°C
°C
°C/sec
W
Max
3.6
105
Unit
V
°C
Recommended Operating Conditions
Table 47. Recommended Operating Condition
Parameter
Supply Voltage(VDD,AVDD)
Operating Ambient Temperature
Min
1.7
-40
Typ
-
Electrical Specification
LVCMOS DC Specification
Table 48. LVCMOS DC Specification
Symbol
VIH
Parameter
High Level Input Voltage
Pin Type
I
IL,B
VIL
Low Level Input Voltage
I
IL,B
VOH
High Level Output Voltage
VOL
Low Level Output Voltage
O,B
O,B
BO
IIH
IIL
IOZH
IOZL
Input Leak Current High
Input Leak Current Low
Output Leak Current High in
Hi-Z State
Output Leak Current Low in
Hi-Z State
Copyright©2022 THine Electronics, Inc.
I,IL
I,IL
Condition
VDD=1.7-2.0V
VDD=2.0-3.0V
VDD=3.0-3.6V
VDD=1.7-3.6V
VDD=1.7-2.0V
VDD=2.0-3.0V
VDD=3.0-3.6V
VDD=1.7-3.6V
VDD=1.7-3.6V
IOH=-4mA
VDD=1.7-3.6V
IOL=4mA
VDD=1.7-3.6V
IOL=2mA
VIN=VDD
VIN=0V
O,B,BO
VIN=VDD
O,B,BO
VIN=0V
50/68
Min
0.65×VDD
0.70×VDD
2.0
0.70×VDD
0
0
0
0
Typ
-
Max
VDD
VDD
VDD
VDD
0.35×VDD
0.30×VDD
0.8
0.30×VDD
Unit
V
V
V
V
V
V
V
V
VDD-0.45
-
VDD
V
0
-
0.45
V
0
-
0.2
V
-10
-
10
-
uA
uA
-
-
10
uA
-10
-
10
uA
THine Electronics, Inc.
SC: E
THCV235_THCV236_Rev.3.70_E
CML DC Specification
Table 49. CML DC Specification(THCV235)
Symbol
VTOD
PRE
Parameter
CML Differential Output Voltage
CML Pre-emphasis Level
VTOC
CML Common Mode Output
Voltage
ITOH
ITOS
CML Output Leak Current High
CML Output Short Current
Condition(*1)
PDN1=0,CMLDRV=0
PDN1=0,CMLDRV=1
PDN1=1,CMLDRV[1:0]=00
PDN1=1,CMLDRV[1:0]=01
PDN1=1,CMLDRV[1:0]=10
PRE=0
PDN1=0,PRE=1,CMLDRV=0
PDN1=1,PRE=1,CMLDRV[1:0]=00
PDN1=1,PRE=1,CMLDRV[1:0]=01
PRE=0
PDN1=0,PRE=1,CMLDRV=0
PDN1=1,PRE=1,CMLDRV[1:0]=00
PDN1=1,PRE=1,CMLDRV[1:0]=01
PDN0=0,TXP/N=CAPINA
PDN0=0,TXP/N=0V
Min
200
300
133
200
300
-
Typ
Max
300
400
400
500
200
267
300
400
400
500
0
50
100
50
CAPINA-VTOD
CAPINA-1.5×VTOD
CAPINA-2×VTOD
CAPINA-1.5×VTOD
-30
30
-80
-
Unit
mV
mV
mV
mV
mV
%
%
%
%
mV
mV
mV
mV
uA
mA
*1 When PDN1=0, PRE and CMLDRV are external pins. When PDN1=1, PRE and CMLDRV[1:0] are registers.
Table 50. CML DC Specification(THCV236)
Symbol
VRTH
VRTL
IRIH
IRIL
IRRIH
IRRIL
RRIN
Parameter
CML Differential Input High Threshold
CML Differential Input High Threshold
CML Input Leak Current High
CML Input Leak Current Low
CML Input Current High
CML Input Current Low
CML Differential Input Resistance
Condition
PDN0=0,RXP/N=CAPINA
PDN0=0,RXP/N=0V
RXP/N=CAPINA
RXP/N=0V
-
Min
-50
-10
-10
-6
80
Typ
100
Max
50
10
10
2
120
Unit
mV
mV
uA
uA
mA
mA
Ω
CML Bi-Directional DC Specification
Table 51. CML Bi-Directional DC Specification
Symbol
VBTH
VBTL
IBIH
IBIL
RTERM
VBOD
VBOC
IBOZ
Parameter
Bi-Directional Buffer Differential
Input High Threshold
Bi-Directional Buffer Differential
Input Low Threshold
Bi-Directional Buffer
Output Leak Current High
Bi-Directional Buffer
Output Leak Current Low
Bi-Directional Buffer
Termination Resistance
Bi-Directional Buffer
Differential Output Voltage
Bi-Directional Buffer
Common Output Voltage
Bi-Directional Buffer TRI-STATE
Current
Copyright©2022 THine Electronics, Inc.
Condition
Min
Typ
Max
Unit
-
-
-
150
mV
-
-150
-
-
mV
xCMP/N=VDD(x=T,R)
-10
-
10
uA
xCMP/N=0V(x=T,R)
-10
-
10
uA
Transmitter State
Receiver State
37.5
150
50
200
62.5
250
Ω
Ω
RDIFF=400Ω
300
-
660
mV
-
VDD-0.3
-
V
-10
-
10
uA
PDN1=0
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THCV235_THCV236_Rev.3.70_E
Supply Current
Table 52. Supply Current(THCV235)
Symbol
ITCCW
ITCCS
Parameter
Transmitter Supply Current
Transmitter Power Down Supply
Current
Condition
PDN0=1,PDN1=1, HFSEL=1
PDN0=0 and PDN1=0
All Inputs = Fixed 0 or 1
Typical value is under 25°C
Min
-
Typ
-
Max
160
Unit
mA
-
2.5
20
mA
Min
Typ
Max
Unit
-
-
220
mA
-
2.5
20
mA
Table 53. Supply Current(THCV236)
Symbol
Parameter
IRCCW
Receiver Supply Current
IRCCS
Receiver Power Down Supply
Current
Condition
Cload=8pF,
PDN0=1,PDN1=1,HFSEL=1
PDN0=0 and PDN1=0
All Inputs = Fixed 0 or 1
Typical value is under 25°C
Switching Characteristics
Table 54. Switching Characteristics (THCV235)
Symbol
tTBIT
tTRF
tTCIP
tTCH
tTCL
tTS
tTH
tTPD
tTCD
tTPLL0
tTPLL1
tTNP0
tTNP1
Parameter
Unit Interval
CML Output Rise and Fall Time
(20%-80%)
CLKIN Period
CLKIN High Time
CLKIN Low Time
Data Input Setup to CLKIN
Data Input Hold to CLKIN
Power On to PDN0 High Delay
Input Clock to Output Data Delay
PDN0 High to CML Output Delay
PDN0 Low to CML Output High
Fix Delay
LOCKN High to Training Pattern
Output Delay
LOCKN Low to Data Pattern
Output Delay
Copyright©2022 THine Electronics, Inc.
Condition
-
Min
250
Typ
-
Max
1666
Unit
ps
-
50
-
150
ps
See Table 20
MAINMODE=0,
HFSEL=0,COL1=0
MAINMODE=0,
HFSEL=0,COL1=1
MAINMODE=0,
HFSEL=1,COL1=0
MAINMODE=0,
HFSEL=1,COL1=1
MAINMODE=1,
HFSEL=0
MAINMODE=1,
HFSEL=1
-
1000/Freq.Range[MHz]
0.35×tTCIP 0.5×tTCIP
0.65×tTCIP
0.35×tTCIP 0.5×tTCIP
0.65×tTCIP
2.0
1.0
0
-
ns
ns
ns
ns
ns
ns
55×tTCIP
-
62×tTCIP
ns
76×tTCIP
-
83×tTCIP
ns
107×tTCIP
-
124×tTCIP
ns
128×tTCIP
-
145×tTCIP
ns
56×tTCIP
-
65×tTCIP
ns
109×tTCIP
-
132×tTCIP
ns
-
-
10
ms
-
-
-
20
ns
-
-
-
10
ms
-
-
-
10
ms
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THCV235_THCV236_Rev.3.70_E
Table 55. Switching Characteristics (THCV236)
Symbol
tRBIT
tRCP
tRCH
tRCL
tDOUT
tRPD
tRDC
tRHPD0
tRHPD1
tRPLL0
tRPLL1
tRLCK0
tRLCK1
tROSC0
tROSC1
tROSC2
tRS
tRH
Parameter
Unit Interval
CLKOUT Period
CLKOUT High Time
CLKOUT Low Time
Data Output Period
Power On to PDN0
High Delay
Input Data to Output
Clock Delay
PDN0 High to
HTPDN Low Delay
PDN0 Low to HTPDN
High Delay
Training Pattern Input
to LOCKN Low Delay
PDN0 Low to LOCKN
High Delay
LOCKN Low to Data
Output Delay
LOCKN High to Data
Output Stop Delay
PDN0 High to
Permanent Clock
output Delay
LOCKN Low to
Permanent Clock
output Low Delay
LOCKN High to
Permanent Clock
output Delay
Data Output Setup to
CLKOUT
Data Output Hold to
CLKOUT
tTLH
Clock, Data Output
Low to High
Transition Time
tTHL
Clock, Data Output
High to Low
Transition Time
Condition
See Table 20
-
Min
Typ
Max
250
1666
1000/Freq.Range[MHz]
tRCP/2
tRCP/2
tRCP
-
Unit
ps
ns
ns
ns
ns
-
0
-
-
ns
MAINMODE=0,HFSEL=0,COL1=0
MAINMODE=0,HFSEL=0,COL1=1
MAINMODE=0,HFSEL=1,COL1=0
MAINMODE=0,HFSEL=1,COL1=1
MAINMODE=1,HFSEL=0
MAINMODE=1,HFSEL=1
60×tRCP
81×tRCP
114×tRCP
135×tRCP
61×tRCP
116×tRCP
-
67×tRCP
88×tRCP
132×tRCP
153×tRCP
70×tRCP
140×tRCP
ns
ns
ns
ns
ns
ns
-
-
-
10
ms
-
-
-
50
us
-
-
-
10
ms
-
-
-
10
us
-
-
-
5
ms
-
-
-
10
us
OUTSEL=1
-
-
5
ms
OUTSEL=1
-
-
1
ms
OUTSEL=1
-
-
10
us
-
0.45×tRCP-0.65
-
-
ns
-
0.45×tRCP-0.65
-
-
ns
-
-
2.0
3.5
0.8
1.9
2.4
4.4
1.0
2.2
ns
ns
ns
ns
ns
ns
ns
ns
Clock , TTLDRV=0
Data , TTLDRV=0
Clock , TTLDRV=1
Data , TTLDRV=1
Clock , TTLDRV=0
Data , TTLDRV=0
Clock , TTLDRV=1
Data , TTLDRV=1
Table 56. CML Bi-Directional Switching Characteristics
Symbol
tBUI
tBRF
tBPJTX
tBPJRX
Parameter
Bi-Directional Buffer Unit Interval
Bi-Directional Buffer
Rise and Fall Time(20%-80%)
Bi-Directional Buffer
Transmitter Period Jitter Accuracy
(peak to peak)
Bi-Directional Buffer
Receiver Period Jitter Tolerance
(peak to peak)
Copyright©2022 THine Electronics, Inc.
Condition
-
Min
80
Typ
100
Max
120
Unit
ns
-
150
-
1000
ps
-
-
-
1
ns
-
8
-
-
ns
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THCV235_THCV236_Rev.3.70_E
Table 57. 2-wire serial slave AC Timing (Sub-Link Master device)
Symbol
fSCL
tSU;STA
tHD;STA
tLOW
tHIGH
tHD;DAT
tSU;DAT
tr
tf
tSU;STO
tBUF
tSP
tPDS
Parameter
SCL clock frequency
Setup time (repeated) START condition
Hold time (repeated) START condition
LOW period of the SCL clock
HIGH period of the SCL clock
Data hold time: output
Data hold time: input
Data setup time: output
Data setup time: input
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
(pull-up resistor:2.5kΩ,bus capacitance:400pF)
Setup time for STOP condition
Bus free time between a STOP and START condition
Pulse width of spikes which must be suppressed by the input filter
Required wait time from PDN1 high to START condition
Min
0.6
0.6
1.3
0.6
20
500
100
-
Typ
9×tOSC
-
Max
400
300(*1)
Unit
kHz
us
us
us
us
us
ns
ns
ns
ns
-
-
300
ns
0.6
1.3
2
-
50
-
us
us
ns
ms
Max
15.625
Unit
ns
-
us
-
us
*1 Please adjust Pull-up resistor and bus capacitance to meet the spec value.
Table 58. 2-wire serial master AC Timing (Sub-Link Slave device)
Symbol
tOSC
tHD;STA
Parameter
Cycle of internal oscillator clock
Min
10.417
-
us
20
31×tOSC
100
-
Typ
12.5
(SCL_W_H × 8 – 3)
× tOSC
((SCL_W_L + 1) × 8 + 8)
× tOSC
((SCL_W_H + 1) × 8 + 8)
× tOSC
9×tOSC
-
300(*1)
us
ns
ns
ns
ns
-
-
300
ns
-
386×tOSC
-
ns
4.7
-
-
us
Hold time (repeated) START condition
-
tLOW
LOW period of the SCL clock
-
tHIGH
HIGH period of the SCL clock
-
tHD;DAT
tSU;DAT
tr
tf
tSU;STO
tBUF
Data hold time: output
Data hold time: input
Data setup time: output
Data setup time: input
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
(pull-up resistor:2.5kΩ,bus capacitance:400pF)
Setup time for STOP condition
Bus free time between a STOP and START
condition
*1 Please adjust Pull-up resistor and bus capacitance to meet the spec value.
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THCV235_THCV236_Rev.3.70_E
Table 59. 2-wire serial interface transaction wait time
Symbol
tWSSR
tRSSR
tWRS
tRPW
tRRS
tRPR
tSSEP
Parameter
Write access completion time to Sub-Link Slave
register
Read access completion time to Sub-Link Slave
register
Write start to Remote side Start Condition
generating time
Remote side Stop Condition generating to Write
access completion time
Read start to Remote side Start Condition
generating time
Remote side Stop Condition generating to Read
access completion time
Min
Typ
Max
Unit
-
-
110
us
-
-
90
us
-
-
65
us
-
-
300
us
-
-
65
us
-
-
300
us
Depending on characteristics of 2-wire
serial slave devices connected to
Sub-Link Slave
Sub-Link Slave External processing time
us
Table 60. Sub-Link control switching characteristics (2-wire serial I/F Mode)
Symbol
tPVM
tPVS
tTGPIO
tIVM
tIRM
tIVS
tIRS
tPS
tPH
Parameter
Programmable GPIO output at Sub-Link Master data valid
Programmable GPIO output at Sub-Link Slave data valid
Through GPIO delay
Sub-Link Master interrupt valid
Sub-Link Master interrupt reset delay
Sub-Link Slave interrupt valid
2WIRE_MODE=00
Sub-Link Slave interrupt reset delay
2WIRE_MODE=01
Programmable GPIO input data setup
Programmable GPIO input data hold
Min
10000×(1/fSCL)
0
Typ
-
Max
0
110
280
90
0
300
300
0
-
Unit
us
us
us
us
us
us
us
us
us
Table 61. Sub-Link control switching characteristics (Low Speed Data Bridge Mode)
Symbol
tLSD
fLSSR
Parameter
Low Speed Data input to output delay
Low Speed Data input sampling rate
Copyright©2022 THine Electronics, Inc.
Min
70
55/68
Typ
-
Max
20
-
Unit
us
kHz
THine Electronics, Inc.
SC: E
THCV235_THCV236_Rev.3.70_E
AC Timing Diagrams and Test Circuits
LVCMOS Input, Output Switching Characteristics
Figure 19. LVCMOS Input Switching Timing Diagrams
Figure 20. LVCMOS Output Switching Timing Diagrams
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CML Output Switching Characteristics
Figure 21. CML Output Switching Characteristics
Figure 22. CML Buffer Equivalent Circuit
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CML Bi-directional Output Test Circuit
Figure 23. Bi-directional CML VBOD/VBOC Test Circuit
Figure 24. Bi-directional CML Switching Timing Diagram and Test Circuit
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Latency Characteristics
Figure 25. THCV235 Latency
pixel 1st bit
tRBIT
Vdiff = (RXP) - (RXN)
tRCP
tRDC
RF=0
CLKOUT
VDD/2
RF=1
D31-D0
HSYNC,VSYNC
DE
VDD/2
VDD/2
Figure 26. THCV236 Latency
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Lock and Unlock Sequence
Figure 27. THCV235 Lock/Unlock Sequence
VDD
tRPD
PDN0
HTPDN
tRHPD1
PDN1=0 → External Pin
PDN1=1 → Register(0x00 bit0)
tRHPD0
CDR
Training
pattern
RXP/N
ALN
Training
pattern
LOCKN
tRLCK0
PDN1=0 → External Pin
PDN1=1 → Register(0x00 bit1)
CLKOUT
(OUTSEL=0)
Normal
pattern
tRPLL1
tRPLL0
Pixel Clock
D31-D0,DE
HSYNC,VSYNC
Low
Low
Permanent Clock
(Internal OSC Clock)
Invalid
Clock
Valid
Clock
tROSC1
tOSC/N
(N=1,2,4,8)(*1)
Low
Low
Pixel Clock
tROSC0
(OUTSEL=1)
Valid
Clock
Invalid
Clock
Low
Permanent Clock
(Internal OSC Clock)
CLKOUT
tRLCK1
Low
tROSC2
InValid
Data
Valid Data
InValid Data
*1 N depends on setting of OUTSEL_SETTING register (0x6D or 0xED bit1,0). See Register Map (Table 38)
Figure 28. THCV236 Lock/Unlock Sequence
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2-wire serial I/F Switching Characteristics
Figure 29. 2-wire serial interface Timing Diagram
Figure 30. Write access completion time to Sub-Link Slave register
Figure 31. Read access completion time to Sub-Link Slave register
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Figure 32. Write access completion time to Remote side 2-wire serial slave register
Figure 33. Read access completion time to Remote side 2-wire serial slave register
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GPIO Switching Characteristics
Figure 34. Through GPIO delay
Figure 35. Programmable GPIO input timing at Sub-Link Master side
Figure 36. Programmable GPIO output timing at Sub-Link Master side
Figure 37. Programmable GPIO output timing at Sub-Link Slave side
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Figure 38. GPIO input and other interrupt event timing at Sub-Link Master side
Figure 39. GPIO input and other interrupt event timing at Sub-Link Slave side
(Clock Stretching Mode)
Figure 40. GPIO input and other interrupt event timing at Sub-Link Slave side
(No Clock Stretching Mode)
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Low Speed Data Bridge Switching Characteristics
Figure 41. Low Speed Data Bridge Mode Data Delay
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PCB Layout Guideline regarding VDD and AVDD for THCV236
When power is supplied from reverse side layer to AVDD, please place ferrite bead between through-hole and
AVDD/VDD pins (Good Example1, 2). If it is needed to set ferrite beads on reverse side, please set
GND-through-hole between AVDD and VDD, and separate the distance as possible (Example). Don’t set
through-holes next to each other between ferrite beads and AVDD/VDD pins (Bad Example).
Good Example 1
Good Example 2
Example
Bad Example
3.6V-1.7V
Isolate throughholes as possible
Bottom
Layer
42
41
40
39
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Package
TOP VIEW
LASER MARK
FOR PIN1
9.00
BOTTOM VIEW
7.20
49
64
48
1
33
16
32
17
0.25
0.50
0.40
SIDE VIEW
Unit : mm
Figure 42. 64-pin QFN package physical dimension
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Notices and Requests
1. The product specifications described in this material are subject to change without prior notice.
2. The circuit diagrams described in this material are examples of the application which may not always
apply to the customer's design. THine Electronics, Inc. (“THine”) is not responsible for possible errors
and omissions in this material. Please note even if errors or omissions should be found in this material,
THine may not be able to correct them immediately.
3. This material contains THine’s copyright, know-how or other proprietary. Copying or disclosing to third
parties the contents of this material without THine’s prior permission is prohibited.
4. Note that even if infringement of any third party's industrial ownership should occur by using this
product, THine will be exempted from the responsibility unless it directly relates to the production
process or functions of the product.
5. This product is not designed for applications that require extremely high-reliability/safety such as
aerospace device, nuclear power control device, or medical device related to critical care, excluding
when this product is specified for automotive use by THine and used it for that purpose. THine accepts
no liability whatsoever for any damages, claims or losses arising out of the uses set forth above.
6. Despite our utmost efforts to improve the quality and reliability of the product, faults will occur with a
certain small probability, which is inevitable to a semi-conductor product. Therefore, you are encouraged
to have sufficiently redundant or error preventive design applied to the use of the product so as not to
have our product cause any social or public damage.
7. Please note that this product is not designed to be radiation-proof.
8. Testing and other quality control techniques are used to this product to the extent THine deems necessary
to support warranty for performance of this product. Except where mandated by applicable law or
deemed necessary by THine based on the user’s request, testing of all functions and performance of the
product is not necessarily performed.
9. Customers are asked, if required, to judge by themselves if this product falls under the category of
strategic goods under the Foreign Exchange and Foreign Trade Act.
10. The product or peripheral parts may be damaged by a surge in voltage over the absolute maximum
ratings or malfunction, if pins of the product are shorted by such as foreign substance. The damages may
cause a smoking and ignition. Therefore, you are encouraged to implement safety measures by adding
protection devices, such as fuses.
11. This product is prohibited for the purpose of developing military modernization, including the
development of weapons of mass destruction (WMD), and the purpose of violating human rights.
THine Electronics, Inc.
http://www.thine.co.jp
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