UPB1009K

NEC’s LOW POWER GPS RF RECEIVER BIPOLAR ANALOG + INTEGRATED CIRCUIT UPB1009K D ESCRIPTION The µPB1009K is a silicon monolithic IC developed for GPS receivers. This IC integrates a full VCO, second IF filter, 4-bit ADC, and digital control interface to reduce cost and mounting space. In addition, its power consumption is low. Moreover, use of a TCXO with frequency of 16.368 MHz/16.384 MHz, 14.4 MHz, 19.2 MHz, or 26 MHz switchable with an on-chip divider is possible. NEC’s stringent quality assurance and test procedures ensure the highest reliability and performance. FEATURES • Double conversion • Multiple system clocks • A/D converter • High-density RF block • Supply voltage • Low current consumption • High-density surface mountable : fREFin = 16.368 MHz, f1stIFin = 61.380 MHz, f2ndIFin = 4.092 MHz : fREFin = 14.4, 16.384, 19.2, 26 MHz, f1stIFin = 62.980 MHz, f2ndIFin = 2.556 MHz : On-chip switchable frequency divider (1/N = 100, 3/256, 9/1024, 65/4096) : On-chip 4-bit A/D converter : On-chip VCO tank circuit and 2ndIF filter : VCC = 2.7 to 3.3 V : ICC = 26.0 mA TYP. @ VCC = 3.0 V, N = 100 : 44-pin plastic QFN APPLICATIONS • Consumer use GPS receiver of reference frequency 16.368 MHz, 2nd IF frequency 4.092 MHz • Consumer use GPS receiver of reference frequency 14.4, 16.384, 19.2, 26 MHz, 2ndIF frequency 2.556 MHz UPB1009K O RDERING Part Number I NFORMATION Package 44-pin plastic QFN Supplying Form • 12 mm wide embossed taping • Pin 1 indicates pull-out direction of tape • Qty 1.5 kpcs/reel, Dry pack specification µPB1009K-E1-A Remark To order evaluation samples, contact your nearby sales office. Part number for sample order: µPB1009K 2 UPB1009K P RODUCT Type L INE-UP ( T A = +25° C, VC C = 3.0 V) Functions (Frequency unit: MHz) Pre-amplifier + RF/IF downconverter + PLL synthesizer REF = 16.368 1stIF = 61.380/2ndIF = 4.092 REF = 14.4, 16.384, 19.2, 26 1stIF = 62.980/2ndIF = 2.556 On-chip 4-bit ADC LNA + Pre-amplifier + RF/IF down-converter + PLL synthesizer REF = 27.456 1stIF = 175.164/2ndIF = 0.132 On-chip 2-bit ADC Pre-amplifier + RF/IF downconverter + PLL synthesizer REF = 16.368 1stIF = 61.380/2ndIF = 4.092 REF = 16.368 1stIF = 61.380/2ndIF = 4.092 VCC (V) 2.7 to 3.3 ICC (mA) 26.0 CG (dB) Package Status Part Number Clock Frequency Specific 1 chip IC µPB1009K 44-pin plastic QFN New Device µPB1008K 2.7 to 3.3 18.0 100 to 120 36-pin plastic QFN µPB1007K 2.7 to 3.3 25.0 100 to 120 36-pin plastic QFN Available µPB1005K 36-pin plastic QFN Remark Typical performance. Please refer to ELECTRICAL CHARACTERISTICS in detail. SYSTEM A PPLICATION E XAMPLE GPS r eceiver R F b lock d iagram PD1 and PD2 in the figure are Power Save Mode control pins. MS1 and MS2 in the figure are TXCO (GPS, W-CDMA, PDC, GSM) control pins. Caution This d iagram s chematically s hows o nly t he µ PB1009K’s i nternal f unctions o n t he s ystem. This d iagram d oes n ot p resent t he a ctual a pplication c ircuits. 3 UPB1009K PIN CONNECTION AND INTERNAL BLOCK DIAGRAM 4 UPB1009K P IN Pin No. 1 2 E XPLANATION Pin Name Function and Application Internal Equivalent Circuit PreAMPout Rext Output pin of preamplifier. Connect a resistor for the reference constantcurrent power supply to this pin. Ground this pin at 22 kΩ. Ground pin for regulator. Power supply voltage pin for preamplifier. Connect a bypass capacitor to this pin to reduce the high-frequency impedance. Ground pin of preamplifier. Input pin of preamplifier. 3 42 RegGND PreAmpVCC 43 44 PreAmpGND PreAmpin 4 5 40 1stMIXin 1stMIXGND 1stMIXVCC 1stMIX input pin. Ground pin for first MIX. Power supply voltage pin for RF mixer. Connect a bypass capacitor to this pin to reduce the high-frequency impedance. Output pin of RF mixer. Insert an IFSAW filter between this pin and pin 37. The VCO oscillation signal can be monitored on this pin. 41 1stIFout 5 UPB1009K Pin No. 6 12 MS1 MS2 Pin Name Function and Application Internal Equivalent Circuit Low : 0 to 0.3 (V) High : VCC − 0.3 to VCC (V) MS1 : L MS2 : L TCXO : 16.368, 16.384 MHz MS1 : L TCXO : 19.2 MHz MS2 : H MS1 : H TCXO : 14.4 MHz MS2 : L MS1 : H TCXO : 26 MHz MS2 : H 11 CPout Output pin of charge pump. Connect external R and C to this pin to set a dumping factor and natural angular frequency (Isink = Isource = 0.45 mA). 13 Refin Reference frequency input pin. Connect an external reference transmitter (such as TCXO) to this pin. 14 PLLVCC Power supply voltage pin of PLL. Connect a bypass capacitor to this pin to reduce the high-frequency impedance. 15 PLLGND Ground pin of PLL. 16 CLKout Clock (fTCXO) output pin (IC test pin). 6 UPB1009K Pin No. 7 Pin Name Function and Application Internal Equivalent Circuit LoVCC Power supply voltage pin of VCO. Connect a bypass capacitor to this pin to reduce the high-frequency impedance. 8 9 VCO1 VCO2 IC test pin. Leave this pin open when the µPB1009K is mounted on board. 10 LoGND Ground pin of VCO. 17 IFGND Ground pin of IF block. 18 2ndIFout Output pin of IF amplifier. 38 1stIFin Input pin of second IF mixer. 39 IFVCC Power supply voltage pin of IF block. 7 UPB1009K Pin No. 19 Pin Name Function and Application Internal Equivalent Circuit 2ndIFin Input pin of ADC buffer amplifier. 20 DCOFFout Output pin of DC trimming OP amplifier. 21 DCOFFin DC trimming pulse input pin. Connect this pin to pin 20 via a capacitor to convert an input pulse signal into DC. 22 23 GNDana GNDbuf Ground pin for OP amplifier and ADC power supply. 24 VDDana Power supply pin for OP amplifier and ADC comparator. 25 VDDbuf Power supply pin for output driver amplifier of ADC. Connect this pin to the ground pin of the A/D converter via a bypass capacitor to reduce the high-frequency impedance. 26 GNDsub Ground pin of CMOS substrate. 27 28 29 30 31 D0 D1 D2 D3 SCKin Digital signal output pins. LSB = D0, MSB = D3 Sampling clock signal input pin. 32 AGCin AGC control pulse signal input pin. 33 AGCout AGC control signal output pin. 8 UPB1009K Pin No. 34 Pin Name Function and Application Internal Equivalent Circuit VDDlogi Power supply voltage pin for power control logic. Ground pin for power control logic. Low : 0 to 0.3 (V) High : VCC − 0.3 to VCC (V) PD1 : L PD2 : L PD1 : L PD2 : H PD1 : H PD2 : L PD1 : H PD2 : H Sleep mode (all circuits off). Warm-up mode (PLL on). Calibration mode . Active mode (all circuits on). 35 36 37 GNDlogi PD1 PD2 9 UPB1009K ABSOLUTE MAXIMUM RATINGS Symbol VCC ICCTotal PD TA Tstg TA = +25°C TA = +25°C TA = +25°C Note Test Conditions Ratings 3.6 100 266 −40 to +85 −55 to +125 Unit V mA mW °C °C Parameter Supply Voltage Total Circuit Current Power Dissipation Oper ating Am bient Tem per atur e Stor age Tem per atur e N o t e Mounted on double-sided copper-clad 50 × 50 × 1.6 mm epoxy glass PWB RECOMMENDED Parameter Supply Voltage O PERATING Symbol VCC TA fRFin f1stLOin f1stIFin f2ndLOin f2ndIFin fREFin fREFout VIL1 R ANGE MIN. 2.7 −30 − − − − − − TYP. 3.0 +25 1 575.42 1 636.8/1 638.4 61.38/62.98 65.472/65.536 4.092/2.556 TCXO MAX. 3.3 +85 − − − − − − Unit V °C MHz MHz MHz MHz MHz MHz Operating Ambient Temperature RF Input Frequency 1st LO Oscillating Frequency 1st IF Input Frequency 2nd LO Input Frequency 2nd IF Input Frequency Reference Input/Output Frequency Clock mode control voltage (Low Level) Clock mode control voltage (High Level) Power-down control voltage (Low Level) Power-down control voltage (High Level) 0 − 0.3 V VIH1 VCC − 0.3 − VCC V VIL2 0 − 0.3 V VIH2 VCC − 0.3 − VCC V 10 UPB1009K P OWER-DOWN C ONTROL M ODE The µPB1009K consists of an RF block, an IF block, and a PLL block. By controlling reduction of power to each block (by applying a voltage to the PD1 and PD2 pins), the following four modes can be used. Mode No. 1 2 3 4 Mode Name Test Conditions PD1 Active mode Calibration mode Warm-up mode Sleep mode L H H L PD2 H H L L ON OFF OFF OFF RF Block IF Block (IF + ADC) ON ON OFF OFF PLL Block ON ON ON OFF Caution To use only the active mode and sleep mode, fix PD1 to L and select the desired mode with PD2. REFERENCE CLOCK CONTROL MODE The divided frequency can be selected as follows so that it can be shared with the TCXO of each system. TCXO Frequency Test Conditions PD1 16.368 MHz (GPS) 16.384 MHz (GPS) 19.2 MHz (W-CDMA) 14.4 MHz (PDC) 26 MHz (GSM) L PD2 L 1/100 16.368 MHz 16.384 MHz 19.2 MHz 14.4 MHz 26 MHz 1/N Phase Comparison Frequency L H H H L H 3/256 9/1024 65/4096 Caution When t he r eference c lock f requency i s 1 6.368 M Hz, t he 1 stIF f requency a nd 2 ndIF frequency a re 6 1.38 M Hz a nd 4 .092 M Hz, r espectively. and 2 .556 M Hz i n a ll o ther c ases. T hey a re r espectively 6 2.98 M Hz 11 UPB1009K E LECTRICAL Parameter Rest current of overall IC in each mode Sleep mode Note Warm-up mode Calibration mode Active mode Rest current of PLL block in each clock mode Current when 1/100 divider is used Current when 256/3 divider is used Current when 1024/9 divider is used Current when 4096/65 divider is used Maximum mode control pin current 6 pin MS1 H application L application 12 pin MS2 H application L application 36 pin PD1 H application L application 37 pin PD2 H application L application Circuit Current 1 Power Gain Noise Figure Saturated Output Power Input 1dB Compression Level Input 3rd Order Intercept Point Input Inpedance fRFin = 1 575.42 MHz ICC1 GLNA NFLNA No Signals, 1-pin current PRFin = −40 dBm fRFin = 1 575 MHz 1.9 12.5 − −4.0 −25 −12 − 2.3 15.0 3.0 −2.7 −21.8 −9.5 11.2 − j21.5 16.4 − j136.6 2.7 17.5 3.5 − − − − mA dB dB dBm dBm dBm Ω − −20 − −20 − −1 − −1 − − − − − − − − 20 − 20 − 1 − 1 − C HARACTERISTICS ( T A = +25° C, VC C = 3.0 V) Symbol Test Conditions MIN. TYP. MAX. Unit Rest status without input signal, including sampling clock. MS1 = L, MS2 = L Is Iw Ic Ia PD1 = L, PD2 = L PD1 = H, PD2 = L PD1 = H, PD2 = H PD1 = L, PD2 = H 1.3 10.5 18.0 22.1 2.2 13.0 22.0 26.0 3.5 15.5 25.3 30.0 mA mA mA mA Current of PLL block. Overall current in calibration mode and active mode increases from that in basic mode (MS1 = L, MS2 = L). PD1 = H, PD2 = L. Iw1 Iw2 Iw3 Iw4 MS1 = L, MS2 = L MS1 = L, MS2 = H MS1 = H, MS2 = L MS1 = H, MS2 = H 5.3 9.7 10.2 10.4 6.5 11.3 12.1 12.3 7.6 12.6 13.5 13.9 mA mA mA mA µA µA µA µA µA µA µA µA PO(SAT)LNA PRFin = −10 dBm PLNA−1 IIP3LNA ZinLNA fRFin = 1 575.42 MHz fRFin = 1 575.42 MHz, 1 576.42 MHz Calculated from S-parameter where input DC cut capacitance = 1 nF, output load L = 100 n, and DC cut capacitance = 1 nF Output Inpedance ZoutLNA − − Ω N o t e Most of the current flows into the ADC ladder resistor (VDDana ♦ GNDana) in the sleep mode, and the sleep mode current between other VCC (VDD) and GND is 10 µA maximum. 12 UPB1009K E LECTRICAL Parameter Circuit Current 2 RF Conversion Gain Noise Figure C HARACTERISTICS ( T A = +25° C, VC C = 3.0 V) Symbol Test Conditions MIN. TYP. MAX. Unit fRF = 1 575.42 MHz, f1stLOin = 1 636.80 MHz, f1stIF = 61.38 MHz ICC2 CGRF No Signals, 40 pin current PRFMIXin = −40 dBm SSBNF = 10*log (2*DSBNF (Linear value) −1) MHz PRFMIXin = −10 dBm PRFMIX-1 IIP3RFMIX fRFMIXin = 1 575.42 MHz fRFMIXin = 1 575.42 MHz, 1 576.42 MHz f1stLO = 1 636.8 MHz Leakage of 1 636.8 MHz frequency when VCO oscillates correctly. Calculated from S-parameter where input DC cut capacitance = 1 nF and output DC cut capacitance = 1 nF 2.0 14.0 − 2.5 16.1 12.8 3.0 19.0 16.0 mA dB dB Maximum IF Output Input 1dB Compression Level Input 3rd Order Intercept Point −4.0 −29.0 −19.0 −0.8 −25.5 −17.2 − − − dBm dBm dBm LO Leakage to IF Pin LO Leakage to RF Pin Input Inpedance LOIF LORF ZinMIX − − − −34.5 −54.7 50.1 − j22.3 57.3 + j2.6 −30 −30 − dBm dBm Ω Output Inpedance ZoutMIX − − Ω Circuit Current 3 IF Conversion Gain f1stFin = 61.38 MHz, f2ndLOin = 65.472 MHz, ZL = 2 kΩ ICC3 No Signals, 39 pin current 6.3 66.0 45.0 19.5 − 20.0 7.3 70.3 51.2 26.4 0.7 25.0 8.5 75.0 58.0 33.5 1.0 − mA dB dB dB dB dB CG (GV) IF VAGC = 0.5 V VAGC = 1.5 V VAGC = 2.5 V In Band Gain Fluctuation Out Of Band Attenuation ΔCG1 ΔCG2 CG Range NFIF V PIF-1 3.092 to 5.092 MHz Gain difference at 4.092 MHz and 9.092 MHz, VAGC = 0.5 V VAGC = 0 to 2.5 V VAGC = 0.5 V (at maximum gain) Pin = −50 dBm, VAGC = 0.5 V f1stIFin = 61.38 MHz VAGC = 0.5 V VAGC = 1.5 V VAGC = 2.5 V Conversion Gain Range IF ⋅ SSB Noise Figure Maximum 2ndIF Output Input 1dB Compression Level 32.5 − 1.0 −70.5 −53.5 −37.0 −56.0 −38.0 −27.0 − 43.9 13.7 1.3 −64.4 −44.9 −30.6 −51.3 −30.7 −21.4 69.3 − j4.8 163 + j3.8 − 17.5 − dB dB VPP dBm dBm dBm dBm dBm dBm Ω − − − − − − − Input 3rd Order Intercept Point IIP3IF f1stIFin1 = 61.28 MHz f1stIFin2 = 61.38 MHz VAGC = 0.5 V VAGC = 1.5 V f2ndLO = 65.472 MHz VAGC = 2.5 V Input Inpedance ZinIF Calculated from S-parameter where input DC cut capacitance = 1 nF and output DC cut capacitance = 100 nF Output Inpedance ZoutIF − − Ω 13 UPB1009K E LECTRICAL Parameter Circuit Current 4 Charge Pump Output Current ICC4 Icpsink I cpsource Loop Filer Output (High Level) Loop Filer Output (Low Level) Reference Input Level VCO Modulation Sensitivity VCO Control Voltage C/N Circuit Current 5 Resolution Sampling Clock Input Band Width Integral Non-linear Error Signal-to-noise Ratio Signal-to-noise + Distortion Ratio Number Total Harmonic Distortion Ratio ICC5 ResAD fs ADBW INL SNR SINAD ENOB THD DC characteristics IF = 5.17 MHz, fs = 20.48 MHz IF = 5.17 MHz, fs = 20.48 MHz ENOB = (SINAD−1.763)/6.02 IF = 5.17 MHz, fs = 20.48 MHz Second-degree to fifth-degree distortion components 3.1 − − 5.1 − 22.0 20.0 3.0 − 4.1 4 − − 0.2 25.3 25.1 3.9 −40 5.4 − 20 − 1.0 − − mA bits MHz MHz LSB dB dB bits dBc VREFin KV VT C/N Center frequency When PLL is Locked PLL, VCO current, MS1 = L, MS2 = L V13 pin = VCC/2 8.0 −0.55 0.35 VCC−0.3 − − − 0.5 70.0 9.5 −0.45 0.45 − − 0.2 100 1.3 81.0 10.6 −0.35 0.55 − 0.2 1.6 − 2.0 − mA mA mA V V VPP MHz V dBc/Hz C HARACTERISTICS ( T A = +25° C, VC C = 3.0 V) Symbol Test Conditions MIN. TYP. MAX. Unit Δ10 kHz − −30 Remarks 1 . Timing characteristics of ADC during normal operation A buffer amplifier is internally inserted before the ADC core of the µPB1009K. The bias of this buffer amplifier is controlled by the signal input from the DC trim pin, and is used to eliminate the DC offset of the ADC. Because the ladder resistor of the ADC is directly connected between VDDana and GNDana, changes in VDDana affect the resolution of the ADC. 14 UPB1009K As illustrated in the operation timing chart below, the data of SampleN is pipeline delayed by 1.5 clocks during normal operation, and is output at the rising edge of the sample clock with output delay time Tod. When the operation is changed from normal operation to power-down operation, the status of the output data immediately before the power-down operation is retained (drive status). The following table shows each timing parameter for reference purposes. Symbol T od Tpld T ds Parameter Output Delay Pipeline Delay Sampling Delay (Aperture Delay) Output Hold Time Test Conditions CL = 10 pF, fclk = 19.2 MHz MIN. − − − TYP. − 1.5 2 MAX. 12 − − Unit ns clock ns T oh 2 − − ns 15 UPB1009K R emarks 2 . Power-down timing characteristics of ADC The output code of the ADC of the µPB1009K is undefined for 7.5 clocks after the power-down signal is cleared when the ADC returns from the power-down status to normal operation. N o t e The output data is undefined from the start of the power-down operation to the 7.5th clock from the falling edge of the clock at which the power-down operation is cleared. 16 UPB1009K T YPICAL  C HARACTERISTICS ( T A = +25° C, VC C = 3.0 V, unless otherwise specified) IC TOTAL CHARACTERISTICS  Remark The graphs indicate nominal characteristics. 17 UPB1009K  PRE-AMPLIFIER BLOCK CHARACTERISTICS  Remark The graphs indicate nominal characteristics. 18 UPB1009K  RF MIX BLOCK CHARACTERISTICS  Remark The graphs indicate nominal characteristics. 19 UPB1009K  IF BLOCK CHARACTERISTICS  Remark The graphs indicate nominal characteristics. 20 UPB1009K  VCO MODULATION SENSITIVITY CHARACTERISTICS   C/N CHARACTERISTICS  Remark The graphs indicate nominal characteristics. 21 UPB1009K  SINAD MHz)  CHARACTERISTICS OF A/D CONVERTOR (IFin = 5.17 MHz, SCLKin = 20.48 Remark The graphs indicate nominal characteristics. 22 UPB1009K M EASUREMENT C IRCUIT 23 UPB1009K DESCRIPTION Pin No. 1 2 3 4 5 6 7 OF PINS OF TEST CIRCUIT Pin No. 14 15 16 17 18 19 20 Sampling Signal Input AGC Input Pin Function DC Offset Input Digital Signal Output Pin Pin Name DCOFFin D0 D1 D2 D3 SCKin AGCin Pin Function Preamplifier Input Preamplifier Output RF Mixer Input MS1 Prescaler Input VCO Power Control Pin Pin Name PreAmpin PreAmpout 1stMIXin MS1 Presin VCOc VT Measurement Pin (Charge Pump CPout Output) MS2 Reference Clock Input Clock Output 2ndIF Output 2ndIF Input DC Offset Output MS2 REFin CLKout 2ndIFout 2ndIFin DCOFFout 8 9 10 11 12 13 21 22 23 24 25 AGC Control Voltage Output PD1 Output (Default onboard : GND) PD1 Output (Default on board : VCC) 1stIF Input 1stIF Output AGCout PD1 PD2 1stIFin 1stIFout 24 UPB1009K A PPLICATION C IRCUIT PD1 0 1 1 0 PD2 0 0 1 1 Power-down mode Sleep mode (full off) Warm-up mode (PLL on) Calibration mode (PLL on) Active mode (full on) MS1 0 0 1 1 MS2 0 1 0 1 TCXO 16.368/16.384 MHz 19.2 MHz 14.4 MHz 26.0 MHz N 100 256/3 1024/9 4096/65 25 UPB1009K P ACKAGE 44-PIN D IMENSIONS QFN (UNIT: mm) PLASTIC Caution The island pins located on the corners are needed to fabricate products in our plant, but do not s erve a ny o ther f unction. C onsequently t he i sland p ins s hould n ot b e s oldered a nd should r emain n on-connection p ins. 26 UPB1009K NOTES ON CORRECT USE (1) Observe precautions for handling because of electro-static sensitive devices. (2) Form a ground pattern as widely as possible to minimize ground impedance (to prevent abnormal oscillation). (3) Keep the wiring length of the ground pins as short as possible. (4) Connect a bypass capacitor to the VCC pin. (5) High-frequency signal I/O pins must be coupled with the external circuit using a coupling capacitor. RECOMMENDED S OLDERING C ONDITIONS This product should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, contact your nearby sales office. Soldering Method Infrared Reflow Soldering Conditions Peak temperature (package surface temperature) Time at peak temperature Time at temperature of 220°C or higher Preheating time at 120 to 180°C Maximum number of reflow processes Maximum chlorine content of rosin flux (% mass) Peak temperature (package surface temperature) Time at temperature of 200°C or higher Preheating time at 120 to 150°C Maximum number of reflow processes Maximum chlorine content of rosin flux (% mass) Peak temperature (molten solder temperature) Time at peak temperature Preheating temperature (package surface temperature) Maximum number of flow processes Maximum chlorine content of rosin flux (% mass) Peak temperature (pin temperature) Soldering time (per side of device) Maximum chlorine content of rosin flux (% mass) : 260°C or below : 10 seconds or less : 60 seconds or less : 120±30 seconds : 3 times : 0.2%(Wt.) or below : 215°C or below : 25 to 40 seconds : 30 to 60 seconds : 3 times : 0.2%(Wt.) or below : 260°C or below : 10 seconds or less : 120°C or below : 1 time : 0.2%(Wt.) or below : 350°C or below : 3 seconds or less : 0.2%(Wt.) or below Condition Symbol IR260 VPS VP215 Wave Soldering WS260 Partial Heating HS350 Caution Do n ot u se d ifferent s oldering m ethods t ogether ( except f or p artial h eating). 27 4590 Patrick Henry Drive Santa Clara, CA 95054-1817 Telephone: (408) 919-2500 Facsimile: (408) 988-0279 Subject: Compliance with EU Directives CEL certifies, to its knowledge, that semiconductor and laser products detailed below are compliant with the requirements of European Union (EU) Directive 2002/95/EC Restriction on Use of Hazardous Substances in electrical and electronic equipment (RoHS) and the requirements of EU Directive 2003/11/EC Restriction on Penta and Octa BDE. CEL Pb-free products have the same base part number with a suffix added. The suffix –A indicates that the device is Pb-free. The –AZ suffix is used to designate devices containing Pb which are exempted from the requirement of RoHS directive (*). In all cases the devices have Pb-free terminals. All devices with these suffixes meet the requirements of the RoHS directive. This status is based on CEL’s understanding of the EU Directives and knowledge of the materials that go into its products as of the date of disclosure of this information. Restricted Substance per RoHS Lead (Pb) Mercury Cadmium Hexavalent Chromium PBB PBDE Concentration Limit per RoHS (values are not yet fixed) < 1000 PPM < 1000 PPM < 100 PPM < 1000 PPM < 1000 PPM < 1000 PPM Concentration contained in CEL devices -A Not Detected Not Detected Not Detected Not Detected Not Detected Not Detected -AZ (*) If you should have any additional questions regarding our devices and compliance to environmental standards, please do not hesitate to contact your local representative. Important Information and Disclaimer: Information provided by CEL on its website or in other communications concerting the substance content of its products represents knowledge and belief as of the date that it is provided. CEL bases its knowledge and belief on information provided by third parties and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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