CMKDM8005TR

CMKDM8005 SURFACE MOUNT SILICON DUAL P-CHANNEL ENHANCEMENT-MODE MOSFET w w w. c e n t r a l s e m i . c o m DESCRIPTION: The CENTRAL SEMICONDUCTOR CMKDM8005 consists of dual P-Channel enhancement-mode silicon MOSFETs designed for high speed pulsed amplifier and driver applications. These MOSFETs offer very low rDS(ON) and low threshold voltage. MARKING CODE: C85M APPLICATIONS: • Load switch/Level shifting • Battery charging • Boost switch • Electro-luminescent backlighting FEATURES: • ESD protection up to 1800V (Human Body Model) • 350mW power dissipation • Very low rDS(ON) • Low threshold voltage • Logic level compatible • Small, SOT-363 surface mount package MAXIMUM RATINGS: (TA=25°C) Drain-Source Voltage SYMBOL VDS SOT-363 CASE Gate-Source Voltage 20 UNITS V 8.0 V Continuous Drain Current (Steady State) VGS ID 650 mA Continuous Source Current (Body Diode) IS 250 mA IDM PD 1.0 A 350 mW Maximum Pulsed Drain Current Power Dissipation Operating and Storage Junction Temperature Thermal Resistance TJ, Tstg ΘJA -65 to +150 °C 357 °C/W ELECTRICAL CHARACTERISTICS PER TRANSISTOR: (TA=25°C unless otherwise noted) SYMBOL TEST CONDITIONS MIN TYP MAX IGSSF, IGSSR VGS=4.5V, VDS=0 10 IDSS BVDSS VGS(th) VSD rDS(ON) rDS(ON) rDS(ON) gFS Crss Ciss Coss VDS=16V, VGS=0 VGS=0, ID=250μA VDS=VGS, ID=250μA VGS=0, IS=250mA 100 20 VDS=10V, ID=200mA VDS=16V, VGS=0, f=1.0MHz VDS=16V, VGS=0, f=1.0MHz VDS=16V, VGS=0, f=1.0MHz nA V 0.5 VGS=4.5V, ID=350mA VGS=2.5V, ID=300mA VGS=1.8V, ID=150mA UNITS μA 1.0 V 1.1 V 0.25 0.36 Ω 0.37 0.5 Ω 0.8 Ω 0.2 S 25 pF 100 pF 21 pF R3 (3-June 2013) CMKDM8005 SURFACE MOUNT SILICON DUAL P-CHANNEL ENHANCEMENT-MODE MOSFET ELECTRICAL CHARACTERISTICS PER TRANSISTOR - Continued: (TA=25°C unless otherwise noted) SYMBOL TEST CONDITIONS TYP MAX UNITS Qg(tot) VDS=10V, VGS=4.5V, ID=200mA 1.2 nC Qgs VDS=10V, VGS=4.5V, ID=200mA 0.24 nC Qgd ton VDS=10V, VGS=4.5V, ID=200mA VDD=10V, VGS=4.5V, ID=200mA, RG=10Ω 0.36 38 nC ns toff VDD=10V, VGS=4.5V, ID=200mA, RG=10Ω 48 ns SOT-363 CASE - MECHANICAL OUTLINE PIN CONFIGURATION LEAD CODE: 1) Source Q1 2) Gate Q1 3) Drain Q2 4) Source Q2 5) Gate Q2 6) Drain Q1 MARKING CODE: C85M R3 (3-June 2013) w w w. c e n t r a l s e m i . c o m CMKDM8005 SURFACE MOUNT SILICON DUAL P-CHANNEL ENHANCEMENT-MODE MOSFET TYPICAL ELECTRICAL CHARACTERISTICS R3 (3-June 2013) w w w. c e n t r a l s e m i . c o m OUTSTANDING SUPPORT AND SUPERIOR SERVICES PRODUCT SUPPORT Central’s operations team provides the highest level of support to insure product is delivered on-time. • Supply management (Customer portals) • Custom bar coding for shipments • Inventory bonding • Custom product packing • Consolidated shipping options DESIGNER SUPPORT/SERVICES Central’s applications engineering team is ready to discuss your design challenges. Just ask. • Free quick ship samples (2nd day air) • Special wafer diffusions • Online technical data and parametric search • PbSn plating options • SPICE models • Package details • Custom electrical curves • Application notes • Environmental regulation compliance • Application and design sample kits • Customer specific screening • Custom product and package development • Up-screening capabilities REQUESTING PRODUCT PLATING 1. If requesting Tin/Lead plated devices, add the suffix “ TIN/LEAD” to the part number when ordering (example: 2N2222A TIN/LEAD). 2. If requesting Lead (Pb) Free plated devices, add the suffix “ PBFREE” to the part number when ordering (example: 2N2222A PBFREE). CONTACT US Corporate Headquarters & Customer Support Team Central Semiconductor Corp. 145 Adams Avenue Hauppauge, NY 11788 USA Main Tel: (631) 435-1110 Main Fax: (631) 435-1824 Support Team Fax: (631) 435-3388 www.centralsemi.com Worldwide Field Representatives: www.centralsemi.com/wwreps Worldwide Distributors: www.centralsemi.com/wwdistributors For the latest version of Central Semiconductor’s LIMITATIONS AND DAMAGES DISCLAIMER, which is part of Central’s Standard Terms and Conditions of sale, visit: www.centralsemi.com/terms w w w. c e n t r a l s e m i . c o m (001)