CMLDM7003

CMLDM7003 CMLDM7003G* CMLDM7003J SURFACE MOUNT DUAL N-CHANNEL ENHANCEMENT-MODE SILICON MOSFET w w w. c e n t r a l s e m i . c o m DESCRIPTION: These CENTRAL SEMICONDUCTOR devices are dual Enhancement-mode N-Channel Field Effect Transistors, manufactured by the N-Channel DMOS Process, designed for high speed pulsed amplifier and driver applications. The CMLDM7003 utilizes the USA pinout configuration, while the CMLDM7003J utilizes the Japanese pinout configuration. These devices offer low rDS(ON) and ESD protection up to 2kV. MARKING CODES: CMLDM7003: C30 CMLDM7003G*: C3G CMLDM7003J: C3J SYMBOL VDS VDG VGS ID IDM PD PD PD TJ, Tstg ΘJA UNITS V V V mA A mW mW mW °C °C/W SOT-563 CASE * Device is Halogen Free by design MAXIMUM RATINGS: (TA=25°C) Drain-Source Voltage Drain-Gate Voltage Gate-Source Voltage Continuous Drain Current Maximum Pulsed Drain Current Power Dissipation (Note 1) Power Dissipation (Note 2) Power Dissipation (Note 3) Operating and Storage Junction Temperature Thermal Resistance 50 50 12 280 1.5 350 300 150 -65 to +150 357 ELECTRICAL CHARACTERISTICS PER TRANSISTOR: (TA=25°C unless otherwise noted) SYMBOL TEST CONDITIONS MIN TYP MAX IGSSF, IGSSR VGS=5.0V 100 IGSSF, IGSSR VGS=10V 2.0 IGSSF, IGSSR VGS=12V 2.0 IDSS VDS=50V, VGS=0 50 BVDSS VGS=0, ID=10μA 50 VGS(th) VDS=VGS, ID=250μA 0.49 1.0 VSD VGS=0, IS=115mA 1.4 rDS(ON) VGS=1.8V, ID=50mA 1.6 3.0 rDS(ON) VGS=2.5V, ID=50mA 1.3 2.5 rDS(ON) VGS=5.0V, ID=50mA 1.1 2.0 gFS VDS=10V, ID=200mA 200 Crss VDS=25V, VGS=0, f=1.0MHz 5.0 Ciss VDS=25V, VGS=0, f=1.0MHz 50 Coss VDS=25V, VGS=0, f=1.0MHz 25 Notes: (1) Ceramic or aluminum core PC Board with copper mounting pad area of 4.0mm2 (2) FR-4 Epoxy PC Board with copper mounting pad area of 4.0mm2 (3) FR-4 Epoxy PC Board with copper mounting pad area of 1.4mm2 UNITS nA μA μA nA V V V Ω Ω Ω mS pF pF pF R6 (18-January 2010) CMLDM7003 CMLDM7003G* CMLDM7003J SURFACE MOUNT DUAL N-CHANNEL ENHANCEMENT-MODE SILICON MOSFET SOT-563 CASE - MECHANICAL OUTLINE PIN CONFIGURATIONS CMLDM7003 (USA Pinout) CMLDM7003G* CMLDM7003J (Japanese Pinout) LEAD CODE: 1) Gate Q1 2) Source Q1 3) Drain Q2 4) Gate Q2 5) Source Q2 6) Drain Q1 MARKING CODES: CMLDM7003: C30 CMLDM7003G*: C3G * Device is Halogen Free by design LEAD CODE: 1) Source Q1 2) Gate Q1 3) Drain Q2 4) Source Q2 5) Gate Q2 6) Drain Q1 MARKING CODE: C3J R6 (18-January 2010) w w w. c e n t r a l s e m i . c o m