CMLDM7120TG

CMLDM7120TG SURFACE MOUNT N-CHANNEL ENHANCEMENT-MODE SILICON MOSFET w w w. c e n t r a l s e m i . c o m DESCRIPTION: The CENTRAL SEMICONDUCTOR CMLDM7120TG is an Enhancement-mode N-Channel Field Effect Transistor, manufactured by the N-Channel DMOS Process, designed for high speed pulsed amplifier and driver applications. This MOSFET offers Low rDS(ON) and a MAX Threshold Voltage of 0.85V. MARKING CODE: CT7 SOT-563 CASE APPLICATIONS: • Load/Power switches • Power supply converter circuits • Battery powered portable equipment MAXIMUM RATINGS: (TA=25°C) Drain-Source Voltage Gate-Source Voltage Continuous Drain Current (Steady State) Maximum Pulsed Drain Current, tp=10μs Power Dissipation (Note 1) Power Dissipation (Note 2) Power Dissipation (Note 3) Operating and Storage Junction Temperature Thermal Resistance FEATURES: • Device is Halogen Free by design • ESD protection up to 2kV • Low rDS(ON) (0.25Ω MAX @ VGS=1.5V) • MAX Threshold Voltage (0.85V) • Logic level compatibility SYMBOL VDS VGS ID IDM PD PD PD TJ, Tstg ΘJA 20 8.0 1.0 4.0 350 300 150 -65 to +150 357 MAX 10 10 0.85 1.10 0.10 0.14 0.25 UNITS V V A A mW mW mW °C °C/W UNITS μA μA V V V Ω Ω Ω Ω nC nC nC S pF pF pF ns ns ELECTRICAL CHARACTERISTICS: (TA=25°C unless SYMBOL TEST CONDITIONS IGSSF, IGSSR VGS=8.0V, VDS=0 IDSS VDS=20V, VGS=0 BVDSS VGS=0, ID=250μA VGS(th) VDS=10V, ID=1.0mA VSD VGS=0, IS=1.0A rDS(ON) VGS=4.5V, ID=0.5A rDS(ON) VGS=2.5V, ID=0.5A rDS(ON) VGS=1.5V, ID=0.1A rDS(ON) VGS=1.2V, ID=0.1A Qg(tot) VDS=10V, VGS=4.5V, ID=1.0A Qgs VDS=10V, VGS=4.5V, ID=1.0A Qgd VDS=10V, VGS=4.5V, ID=1.0A gFS VDS=10V, ID=0.5A Crss VDS=10V, VGS=0, f=1.0MHz Ciss VDS=10V, VGS=0, f=1.0MHz Coss VDS=10V, VGS=0, f=1.0MHz ton VDD=10V, VGS=5.0V, ID=0.5A toff VDD=10V, VGS=5.0V, ID=0.5A otherwise noted) MIN TYP 20 0.5 0.075 0.10 0.20 0.80 2.4 0.25 0.65 2.5 45 220 120 25 140 Notes: (1) Ceramic or aluminum core PC Board with copper mounting pad area of 4.0mm2 (2) FR-4 Epoxy PC Board with copper mounting pad area of 4.0mm2 (3) FR-4 Epoxy PC Board with copper mounting pad area of 1.4mm2 R2 (2-August 2011) CMLDM7120TG SURFACE MOUNT N-CHANNEL ENHANCEMENT-MODE SILICON MOSFET SOT-563 CASE - MECHANICAL OUTLINE PIN CONFIGURATION LEAD CODE: 1) Drain 2) Drain 3) Gate 4) Source 5) Drain 6) Drain MARKING CODE: CT7 R2 (2-August 2011) w w w. c e n t r a l s e m i . c o m