CP230_10

PROCESS Power Transistor CP230 NPN - Silicon Darlington Transistor Chip PROCESS DETAILS Process Die Size Die Thickness Base Bonding Pad Area Emitter Bonding Pad Area Top Side Metalization Back Side Metalization GEOMETRY GROSS DIE PER 4 INCH WAFER 1,445 PRINCIPAL DEVICE TYPES CZT122 CJD122 EPITAXIAL BASE 80 x 80 MILS 8.0 MILS 18 x 27 MILS 34 x 34 MILS Al - 30,000Å Ti/Pd/Ag - 20,000Å R2 (22-March 2010) w w w. c e n t r a l s e m i . c o m PROCESS CP230 Typical Electrical Characteristics R2 (22-March 2010) w w w. c e n t r a l s e m i . c o m