CP235

PROCESS CP235 Power Transistor NPN - Silicon Power Transistor Chip Central TM Semiconductor Corp. PROCESS DETAILS Process Die Size Die Thickness Base Bonding Pad Area Emitter Bonding Pad Area Top Side Metallization Back Side Metallization GLASS PASSIVATED MESA 106 x 106 MILS 12 MILS 25 x 33 MILS 30 x 36 MILS Al 50,000Å Ag 10,000Å GEOMETRY GROSS DIE PER 4 INCH WAFER 950 PRINCIPAL DEVICE TYPES 2N3055 145 Adams Avenue Hauppauge, NY 11788 USA Tel: (631) 435-1110 Fax: (631) 435-1824 www.centralsemi.com R1 (20-March 2006) Central TM PROCESS CP235 Semiconductor Corp. Typical Electrical Characteristics 145 Adams Avenue Hauppauge, NY 11788 USA Tel: (631) 435-1110 Fax: (631) 435-1824 www.centralsemi.com R1 (20-March 2006)