CP341V

PROCESS CP341V Small Signal Transistors NPN - Low VCE(SAT) Transistor Chip PROCESS DETAILS Process Die Size Die Thickness Base Bonding Pad Area Emitter Bonding Pad Area Top Side Metalization Back Side Metalization GEOMETRY GROSS DIE PER 5 INCH WAFER 54,330 PRINCIPAL DEVICE TYPES CMLT3410 CMPT3410 CMST3410 CMUT3410 Epitaxial Planar 18 x 18 MILS 7.1 MILS 3.8 x 3.8 MILS 3.8 x 3.8 MILS Al/Si - 30,000Å Au - 12,000Å 145 Adams Avenue Hauppauge, NY 11788 USA Tel: (631) 435-1110 Fax: (631) 435-1824 www.centralsemi.com R0 (5- January 2006)