CP353V

PROCESS CP353V Small Signal Transistors NPN - High Current Transistor Chip PROCESS DETAILS Process Die Size Die Thickness Base Bonding Pad Area Emitter 1 Bonding Pad Area Emitter 2 Bonding Pad Area Top Side Metalization Back Side Metalization GEOMETRY EPITAXIAL PLANAR 66 x 66 MILS 7.1 MILS 7.9 x 7.9 MILS 7.9 x 9.5 MILS 7.9 x 9.5 MILS Al-Si Au 30,000Å 12,000Å GROSS DIER PER 5 INCH WAFER 3,878 PRINCIPAL DEVICE TYPES CZT853 145 Adams Avenue Hauppauge, NY 11788 USA Tel: (631) 435-1110 Fax: (631) 435-1824 www.centralsemi.com R0 (23- September 2005)