CP382X

PROCESS Small Signal Transistor CP382X NPN - Low VCE(SAT) Transistor Chip PROCESS DETAILS Die Size Die Thickness Base Bonding Pad Area Emitter Bonding Pad Area Top Side Metalization Back Side Metalization 26 x 26 MILS 5.9 MILS 5.5 x 5.5 MILS 5.5 x 5.5 MILS Al - 30,000Å Au - 12,000Å GEOMETRY GROSS DIE PER 5 INCH WAFER 25,536 PRINCIPAL DEVICE TYPES CMLT3820G CMPT3820 CXT3820 R0 (9-September 2010) w w w. c e n t r a l s e m i . c o m PROCESS CP382X Typical Electrical Characteristics R0 (9-September 2010) w w w. c e n t r a l s e m i . c o m