CP630

PROCESS CP630 Power Transistors PNP - Silicon Darlington Transistor Chip PROCESS DETAILS Process Die Size Die Thickness Base Bonding Pad Area Emitter Bonding Pad Area Top Side Metalization Back Side Metalization GEOMETRY GROSS DIE PER 4 INCH WAFER 1,445 PRINCIPAL DEVICE TYPES CZT127 CJD127 EPITAXIAL BASE 80 X 80 MILS 8 MILS 18 X 27 MILS 34 X 34 MILS Al - 30,000Å Ti/Pd/Ag (20,000Å) BACKSIDE COLLECTOR 145 Adams Avenue Hauppauge, NY 11788 USA Tel: (631) 435-1110 Fax: (631) 435-1824 www.centralsemi.com R0 (9 -May 2005)