CP705_10

PROCESS Small Signal Transistor CP705 PNP - High Current Transistor Chip PROCESS DETAILS Process Die Size Die Thickness Base Bonding Pad Area Emitter Bonding Pad Area Top Side Metalization Back Side Metalization GEOMETRY GROSS DIE PER 4 INCH WAFER 11,212 PRINCIPAL DEVICE TYPES 2N4033 CMPT4033 CXT4033 CZT4033 EPITAXIAL PLANAR 31 x 31 MILS 9.0 MILS 5.9 x 11.8 MILS 6.5 x 13.8 MILS Al - 30,000Å Au - 18,000Å R4 (22-March 2010) w w w. c e n t r a l s e m i . c o m PROCESS CP705 Typical Electrical Characteristics R4 (22-March 2010) w w w. c e n t r a l s e m i . c o m