CP707_10

PROCESS Small Signal Transistor CP707 PNP - Darlington Transistor Chip PROCESS DETAILS Process Die Size Die Thickness Base Bonding Pad Area Emitter Bonding Pad Area Top Side Metalization Back Side Metalization GEOMETRY GROSS DIE PER 4 INCH WAFER 15,165 PRINCIPAL DEVICE TYPES CMPTA63 CMPTA64 CXTA64 CZTA64 MPSA63 MPSA64 EPITAXIAL PLANAR 27 x 27 MILS 9.0 MILS 5.3 x 3.8 MILS 5.3 x 6.5 MILS Al - 30,000Å Au - 18,000Å BACKSIDE COLLECTOR R6 (22-March 2010) w w w. c e n t r a l s e m i . c o m PROCESS CP707 Typical Electrical Characteristics R6 (22-March 2010) w w w. c e n t r a l s e m i . c o m