CP741V_10

PROCESS Small Signal Transistors CP741V PNP - Low VCE(SAT) Transistor Chip PROCESS DETAILS Process Die Size Die Thickness Base Bonding Pad Area Emitter Bonding Pad Area Top Side Metalization Back Side Metalization GEOMETRY GROSS DIE PER 5 INCH WAFER 54,330 PRINCIPAL DEVICE TYPES CMLT7410 CMPT7410 CMST7410 CMUT7410 EPITAXIAL PLANAR 17.7 x 17.7 MILS 7.1 MILS 3.8 x 3.8 MILS 3.8 x 3.8 MILS Al-Si - 30,000Å Au - 12,000Å R2 (22-March 2010) w w w. c e n t r a l s e m i . c o m PROCESS CP741V Typical Electrical Characteristics R2 (22-March 2010) w w w. c e n t r a l s e m i . c o m