CTLDM7002A-M621H

CTLDM7002A-M621H SURFACE MOUNT N-CHANNEL ENHANCEMENT-MODE SILICON MOSFET w w w. c e n t r a l s e m i . c o m DESCRIPTION: The CENTRAL SEMICONDUCTOR CTLDM7002AM621H is a very low profile (0.4mm) Silicon N-Channel Enhancement-mode MOSFET in a small, thermally efficient, 1.5mm x 2mm TLM™ package. MARKING CODE: CND TLM621H CASE • Device is Halogen Free by design FEATURES: • Low rDS(ON) • Low VDS(ON) • Low Threshold Voltage • Fast Switching • Logic Level Compatible • Small, Very Low Profile, TLM™ APPLICATIONS: • Load/Power Switches • Power Supply Converter Circuits • Battery Powered Portable Equipment MAXIMUM RATINGS: (TA=25°C) Drain-Source Voltage Drain-Gate Voltage Gate-Source Voltage Continuous Drain Current Continuous Source Current (Body Diode) Maximum Pulsed Drain Current Maximum Pulsed Source Current Power Dissipation (Note 1) Operating and Storage Junction Temperature Thermal Resistance (Note 1) SYMBOL VDS VDG VGS ID IS IDM ISM PD TJ, Tstg ΘJA 60 60 40 280 280 1.5 1.5 1.6 -65 to +150 75 UNITS V V V mA mA A A W °C °C/W ELECTRICAL CHARACTERISTICS: (TA=25°C unless otherwise noted) SYMBOL TEST CONDITIONS MIN IGSSF, IGSSR IDSS IDSS ID(ON) BVDSS VGS(th) VDS(ON) VDS(ON) VSD VGS=20V, VDS=0 VDS=60V, VGS=0 VDS=60V, VGS=0, TJ=125°C VGS=10V, VDS=10V VGS=0, ID=10μA VDS=VGS, ID=250μA VGS=10V, ID=500mA VGS=5.0V, ID=50mA VGS=0, IS=400mA 500 60 1.0 MAX 100 1.0 500 UNITS nA μA μA mA V 2.5 1.0 0.15 1.2 V V V V Notes: (1) Mounted on a 4-layer JEDEC test board with one thermal vias connecting the exposed thermal pad to the first buried plane. PCB was constructed as per JEDEC standards JESD51-5 and JESD51-7. R2 (17-February 2010) CTLDM7002A-M621H SURFACE MOUNT N-CHANNEL ENHANCEMENT-MODE SILICON MOSFET ELECTRICAL CHARACTERISTICS - Continued: (TA=25°C unless otherwise noted) SYMBOL TEST CONDITIONS MIN MAX rDS(ON) VGS=10V, ID=500mA 2.0 rDS(ON) VGS=10V, ID=500mA, TJ=125°C 3.5 rDS(ON) rDS(ON) gFS Crss Ciss Coss ton, toff VGS=5.0V, ID=50mA VGS=5.0V, ID=50mA, TJ=125°C VDS=10V, ID=200mA VDS=25V, VGS=0, f=1.0MHz VDS=25V, VGS=0, f=1.0MHz VDS=25V, VGS=0, f=1.0MHz VDD=30V, VGS=10V, ID=200mA, RG=25Ω, RL=150Ω 3.0 5.0 80 5.0 50 15 20 UNITS Ω Ω Ω Ω mS pF pF pF ns TLM621H CASE - MECHANICAL OUTLINE OPTIONAL MOUNTING PADS (Dimensions in mm) PIN CONFIGURATION For standard mounting refer to TLM621H Package Details LEAD CODE: 1) Source 2) Drain 3) Drain 4) Drain 5) Drain 6) Gate MARKING CODE: CND *Exposed pad P internally connected to pins 2, 3, 4, and 5. R2 (17-February 2010) w w w. c e n t r a l s e m i . c o m