24LLC02

24LLC02 2K-Bits Serial EEPROM For Low Power OVERVIEW The 24LLC02 serial EEPROM has a 2,048-bit capacity, supporting the standard 2 C™-bus serial interface. I It is fabricated using Ceramate's most advanced CMOS technology. It has been developed for low power and low voltage applications (1.8 V to 5.5 V). One of its major feature is a hardware-based write protection circuit for the entire memory area. Hardware-based write protection is controlled by the state of the write-protect (WP) pin. Using one-page write mode, you can load up to 16 bytes of data into the EEPROM in a single write operation. Another significant feature of the 2 4LLC02 is its support for fast mode and standard mode. FEATURES I C-Bus Interface • Two-wire serial interface • Automatic word address increment EEPROM • • • • • • 2K-bit (2,048-bit/256-byte) storage area 16-byte page buffer Hardware-based write protection for the entire EEPROM (using the WP pin) EEPROM programming voltage generated on chip 1,000,000 erase/write cycles 100 years data retention • • 2 Operating Characteristics • • Operating voltage — 1.8 V to 5.5 V Operating current — Maximum write current: < 3 mA at 5.5 V — Maximum read current: < 200 µA at 5.5 V — Maximum stand-by current: < 5 µA at 5.5 V Operating temperature range — – 25°C to + 70°C (commercial) — – 40°C to + 85°C (industrial) Operating clock frequencies — 100 kHz at standard mode — 400 kHz at fast mode • Electrostatic discharge (ESD) — 5,000 V (HBM) — 500 V (MM) Packages • 8-pin P-DIP , SOP , TSSOP ORDERING INFORMATION 24 LLC 02 X X Operating Voltage LLC:1.8~5.5V,CMOS Type 02=2K Temp. grade Blank:-25℃~+70℃ Packing Blank :Tube N :Tube(DIP8) A :Taping(SOP8) T :Taping(TSSOP8) * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 1 of 19 Rev 1.0 Dec. 26, 2001 Fax:886-3-3521052 24LLC02 2K-Bits Serial EEPROM For Low Power SDA Start/Stop Logic HV Generation Timing Control WP Control Logic EEPROM Cell Array SCL Slave Address Comparator Word Address Pointer Row decoder 256 x 8 bits A0 A1 A2 Column Decoder Data Register D OUT and ACK Figure 1-1. 2 4LLC02 Block Diagram * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 2 of 19 Rev 1.0 Dec. 26, 2001 Fax:886-3-3521052 24LLC02 2K-Bits Serial EEPROM For Low Power V CC WP SCL SDA 24LLC02 A0 A1 A2 V SS NOTE: The 2 4LLC02 is available in 8-pin DIP, SOP,TSSOP package. Figure 1-2. Pin Assignment Diagram Table 1-1. 2 4LLC02 Pin Descriptions Name A0, A1, A2 Type Input Description Input pins for device address selection. To configure a device address, these pins should be connected to the VCC or V SS of the device. These pins are internally pulled down to V SS . Ground pin. Bi-directional data pin for the I C-bus serial data interface. Schmitt trigger input and open-drain output. An external pull-up resistor must be connected to VCC. Typical values for this pull-up resistor are 4.7 k Ω (100 kHz) and 1 k Ω (400 kHz). Schmitt trigger input pin for serial clock input. Input pin for hardware write protection control. If you tie this pin to V CC, the write function is disabled to protect previously written data in the entire memory; if you tie it to VSS , t he write function is enabled. This pin is internally pulled down to VSS . Single power supply. 2 Circuit Type 1 V SS SDA – I/O – 3 SCL WP Input Input 2 1 V CC – – NOTE : See the following page for diagrams of pin circuit types 1, 2, and 3. * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 3 of 19 Rev 1.0 Dec. 26, 2001 Fax:886-3-3521052 24LLC02 2K-Bits Serial EEPROM For Low Power A0, A1, A2, WP SCL Noise Filter Figure 1-3. Pin Circuit Type 1 Figure 1-4. Pin Circuit Type 2 SDA Data Out V SS Noise Filter Data In Figure 1-5. Pin Circuit Type 3 * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 4 of 19 Rev 1.0 Dec. 26, 2001 Fax:886-3-3521052 24LLC02 2K-Bits Serial EEPROM For Low Power FUNCTION DESCRIPTION I 2C-BUS INTERFACE The 2 4LLC02 supports the I C-bus serial interface data transmission protocol. The two-wire bus consists of a serial data line (SDA) and a serial clock line (SCL). The SDA and the SCL lines must be connected to V CC by a pull-up resistor that is located somewhere on the bus. 2 Any device that puts data onto the bus is defined as the “transmitter” and any device that gets data from the bus is the “receiver.” The bus is controlled by a master device which generates the serial clock and start/stop conditions , controlling bus access. Using the A0, A1, and A2 input pins, up to eight 2 4LLC02 devices can be connected 2 to the same I C-bus as slaves (see Figure 1-6). Both the master and slaves can operate as transmitter or receiver , but the master device determines which bus operating mode would be active. V CC V CC SDA SCL Slave 1 Bus Master (Transmitter/ Receiver) MCU To V CC Slave 2 2 4 2 24LLC02 LLC Tx/Rx A0 A1 A2 Slave 3 24LLC02 Tx/Rx A0 A1 A2 Slave 8 24LLC02 Tx/Rx A0 A1 A2 24LLC02 Tx/Rx A0 A1 A2 or V SS To V CC or V SS To V CC or V SS To V CC or V SS Figure 1-6. Typical Configuration (16 Kbits of Memory on the I 2 C-Bus) * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 5 of 19 Rev 1.0 Dec. 26, 2001 Fax:886-3-3521052 24LLC02 2K-Bits Serial EEPROM For Low Power I 2C-BUS PROTOCOLS Here are several rules for I 2C-bus transfers: — A new data transfer can be initiated only when the bus is currently not busy. — MSB is always transferred first in transmitting data. — During a data transfer, the data line (SDA) must remain stable whenever the clock line (SCL) is High. The I C-bus interface supports the following communication protocols: • • • Bus not busy : The SDA and the SCL lines remain High level when the bus is not active. Start condition : Start condition is initiated by a High-to-Low transition of the SDA line while SCL remains High level. All bus commands must be preceded by a start condition. Stop condition : A stop condition is initiated by a Low-to-High transition of the SDA line while SCL remains High level. All bus operations must be completed by a stop condition (see Figure 1-7). 2 ~ ~ SCL ~ ~ SDA Start Condition Data or ACK Valid Data Change Stop Condition Figure 1-7. Data Transmission Sequence • Data valid : Following a start condition, the data becomes valid if the data line remains stable for the duration of the High period of SCL. New data must be put onto the bus while SCL is Low. Bus timing is one clock pulse per data bit. The number of data bytes to be transferred is determined by the master device. The total number of bytes that can be transferred in one operation is theoretically unlimited. ACK (Acknowledge) : An ACK signal indicates that a data transfer is completed successfully. The transmitter (the master or the slave) releases the bus after transmitting eight bits. During the 9th clock, which the master generates, the receiver pulls the SDA line low to acknowledge that it successfully received the eight bits of data (see Figure 1-8). But the slave does not send an ACK if an internal write cycle is still in progress. In data read operations, the slave releases the SDA line after transmitting 8 bits of data and then monitors the line for an ACK signal during the 9th clock period. If an ACK is detected, the slave will continue to transmit data. If an ACK is not detected, the slave terminates data transmission and waits for a stop condition to be issued by the master before returning to its stand-by mode. * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 6 of 19 Rev 1.0 Dec. 26, 2001 Fax:886-3-3521052 • 24LLC02 2K-Bits Serial EEPROM For Low Power Master SCL Line Bit 1 Bit 9 Data from Transmitter ACK from Receiver ACK Figure 1-8. Acknowledge Response From Receiver • Slave Address : After the master initiates a Start condition, it must output the address of the device to be accessed. The most significant four bits of the slave address are called the “device identifier”. The identifier for the 24LLC02 is “1010B”. The next three bits comprise the address of a specific device. The device address is defined by the state of the A0, A1 and A2 pins. Using this addressing scheme, you can cascade up to eight 24LLC02 on the bus (see Table 1-2 below).are used by the master to select which of the blocks of internal memory (1 block= 256 words) are to be accessed. The bits are in effect the most significant bits of the word address. Read/Write : The final (eighth) bit of the slave address defines the type of operation to be performed. If the R /W bit is “1”, a read operation is executed. If it is “0”, a write operation is executed. • Table 1-2. Slave Device Addressing Device 24LLC02 NOTE: Device Identifier b7 1 b6 0 b5 1 b4 0 b3 A2 Device Address b2 A1 b1 A0 R/ W Bit b0 R/ W The B2, B1, B0 correspond to the MSB of the memory array address word. * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 7 of 19 Rev 1.0 Dec. 26, 2001 Fax:886-3-3521052 24LLC02 2K-Bits Serial EEPROM For Low Power BYTE WRITE OPERATION In a complete byte write operation, the master transmits the slave address, word address, and one data byte to the 24LLC02 slave device (see Figure 1-9). Start Slave Address Word Address Data Stop A C K A C K A C K Figure 1-9. Byte Write Operation Following the Start condition, the master sends the device identifier (4 bits), the device address (3 bits), and an R /W bit set to “0” onto the bus. Then the addressed 24LLC02 generates an ACK and waits for the next byte. The next byte to be transmitted by the master is the word address. This 8-bit address is written into the word address pointer of the 24LLC02. When the 24LLC02 receives the word address, it responds by issuing an ACK and then waits for the next 8-bit data. When it receives the data byte, the 24LLC02 again responds with an ACK.The master terminates the transfer by generating a Stop condition, at which time the 24LLC02 begins the internal write cycle. While the internal write cycle is in progress, all 24LLC02 inputs are disabled and the 24LLC02 does not respond to additional requests from the master. * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 8 of 19 Rev 1.0 Dec. 26, 2001 Fax:886-3-3521052 24LLC02 2K-Bits Serial EEPROM For Low Power PAGE WRITE OPERATION The 24LLC02 can also perform 16-byte page write operation. A page write operation is initiated in the same way as a byte write operation. However, instead of finishing the write operation after the first data byte is transferred, the master can transmit up to 15 additional bytes. The 24LLC02 responds with an ACK each time it receives a complete byte of data (see Figure 1-10). Start Slave Address Word Address (n) Data (n) Data ( ≤ n + 15) Stop A C K A C K A C K A C K A C K Figure 1-10. Page Write Operation The 24LLC02 automatically increments the word address pointer each time it receives a complete data byte. When one byte has been received, the internal word address pointer increments to the next address and the next data byte can be received. If the master transmits more than 16 bytes before it generates a stop condition to end the page write operation, the 24LLC02 word address pointer value “rolls over” and the previously received data is overwritten.If the master transmits less than 16 bytes and generates a stop condition, the 24LLC02 writes the received data to the corresponding EEPROM address. During a page write operation, all inputs are disabled and there is no response to additional requests from the master until the internal write cycle is completed. * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 9 of 19 Rev 1.0 Dec. 26, 2001 Fax:886-3-3521052 24LLC02 2K-Bits Serial EEPROM For Low Power POLLING FOR AN ACK SIGNAL When the master issues a stop condition to initiate a write cycle, the 24LLC02 starts an internal write cycle. The master can then immediately begin polling for an ACK from the slave device. To poll for an ACK signal in a write operation, the master issues a start condition followed by the slave address. As long as the 24LLC02 remains busy with the write operation, no ACK is returned. When the 24LLC02 completes the write operation, it returns an ACK and the master can then proceed with the next read or write operation (see Figure 1-11). Send Write Command Send Stop Condition to Initiate Write Cycle Send Start Condition Send Slave Address with R/ W bit = "0" ACK = "0" ? Yes Start Next Operation No Figure 1-11. Master Polling for an ACK Signal from a Slave Device * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 10 of 19 Rev 1.0 Dec. 26, 2001 Fax:886-3-3521052 24LLC02 2K-Bits Serial EEPROM For Low Power HARDWARE-BASED WRITE PROTECTION You can also write-protect the entire memory area of the 24LLC02. This method of write protection is controlled by the state of the Write Protect (WP) pin. When the WP pin is connected to VCC , any attempt to write a value to the memory is ignored. The 24LLC02 will acknowledge slave and word address, but it will not generate an acknowledge after receiving the first byte of the data. Thus the write cycle will not be started when the stop condition is generated . By connecting the WP pin to VSS , t he write function is allowed for the entire memory. These write protection features effectively change the EEPROM to a ROM in order to prevent data from being overwritten. Whenever the write function is disabled, a slave address and a word address are acknowledged on the bus, but data bytes are not acknowledged. CURRENT ADDRESS BYTE READ OPERATION The internal word address pointer maintains the address of the last word accessed, incremented by one. Therefore, if the last access (either read or write) was to the address “n”, the next read operation would access data at address “n+1”. When the 24LLC02 receives a slave address with the R / W bit set to “1”, it issues an ACK and sends the eight bits of data.The master does not acknowledge the transfer but it does generate a Stop condition. In this way, the 24LLC02 effectively stops the transmission (see Figure 1-12). Start Slave Address Data Stop A C K N O A C K Figure 1-12. Current Address Byte Read Operation * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 11 of 19 Rev 1.0 Dec. 26, 2001 Fax:886-3-3521052 24LLC02 2K-Bits Serial EEPROM For Low Power RANDOM ADDRESS BYTE READ OPERATION Using random read operations, the master can access any memory location at any time. Before it issues the slave address with the R /W bit set to “1”, the master must first perform a “dummy” write operation. This operation is performed in the following steps: 1. 2. 3. 4. 5. The master first issues a Start condition, the slave address, and the word address to be read. (This step sets the internal word address pointer of the 24LLC02 to the desired address.) When the master receives an ACK for the word address, it immediately re-issues a start condition followed by another slave address, with the R /W bit set to “1”. The 24LLC02 then sends an ACK and the 8-bit data stored at the desired address. At this point, the master does not acknowledge the transmission, but generates a stop condition instead. In response, the 24LLC02 stops transmitting data and reverts to its stand-by mode (see Figure 1-13). Start Slave Address Word Address Start Slave Address Data (n) Stop A C K A C K A C K N O A C K Figure 1-13. Random Address Byte Read Operation * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 12 of 19 Rev 1.0 Dec. 26, 2001 Fax:886-3-3521052 24LLC02 2K-Bits Serial EEPROM For Low Power SEQUENTIAL READ OPERATION Sequential read operations can be performed in two ways: as a series of current address reads or as random address reads. The first data is sent in the same way as the previous read mode used on the bus. The next time, however, the master responds with an ACK, indicating that it requires additional data. The 24LLC02 continues to output data for each ACK it receives. To stop the sequential read operation,the master does not respond with an ACK, but instead issues a Stop condition. Using this method, data is output sequentially with the data from address “n” followed by the data from “n+1”. The word address pointer for read operations increments all word addresses, allowing the entire EEPROM to be read sequentially in a single operation. After the entire EEPROM is read, the word address pointer “rolls over” and the 24LLC02 continues to transmit data for each ACK it receives from the master (see Figure 1-14). Start Slave Address Data (n) Data (n + x) ~ ~ A C K A C K A C K N O A C K Figure 1-14. Sequential Read Operation * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 13 of 19 Rev 1.0 Dec. 26, 2001 Fax:886-3-3521052 24LLC02 2K-Bits Serial EEPROM For Low Power ELECTRICAL DATA Table 1-3. Absolute Maximum Ratings (T A = 25 °C) Parameter Supply voltage Input voltage Output voltage Operating temperature Storage temperature Electrostatic discharge Symbol V CC V IN VO TA T STG V ESD Conditions – – – – – HBM MM Rating – 0.3 to + 7.0 – 0.3 to + 7.0 – 0.3 to + 7.0 – 40 to + 85 – 65 to + 150 5000 500 Unit V V V °C °C V Table 1-4. D.C. Electrical Characteristics (T A = – 25 °C to + 70 °C (C), – 40 °C to + 85 °C (I), V Parameter Input low voltage Input high voltage Input leakage current Output leakage current Output low voltage Symbol V IL V IH I LI I LO V OL I CC1 I CC2 Read I CC3 I CC4 Stand-by current I CC5 I CC6 V IN = 0 to V V O = 0 to V CC CC CC CC CC = 1.8 V to 5.5 V) Min – 0.7 V – – = 1.8 V – – – – – – – – CC Conditions SCL, SDA, A0, A1, A2 Typ – – – – – – – – – – – – Max 0.3 V – 10 10 0.2 0.4 3 1 0.2 60 5 1 CC Unit V V µA µA V I OL = 0.15 mA, V I OL = 2.1 mA, V = 2.5 V Supply current Write V CC = 5.5 V, 400 kHz V CC = 1.8 V, 100 kHz V CC = 5.5 V, 400 kHz V CC = 1.8 V, 100 kHz V CC = SDA = SCL = 5.5 V, all other inputs = 0 V V CC = SDA = SCL = 1.8 V, all other inputs = 0 V mA µA µA * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 14 of 19 Rev 1.0 Dec. 26, 2001 Fax:886-3-3521052 24LLC02 2K-Bits Serial EEPROM For Low Power Table 1-4. D.C. Electrical Characteristics (Continued) (T A = – 25 °C to + 70 °C (C), – 40 °C to + 85 °C (I), V Parameter Input capacitance Symbol C IN CC = 1.8 V to 5.5 V) Conditions Min – Typ – Max 10 Unit pF 25 °C, 1MHz, V CC = 5 V, V IN = 0 V, A0, A1, A2, SCL and WP pin 25 °C, 1MHz, V CC = 5 V, V SDA pin I/O Input/output capacitance C I/O – = 0 V, – 10 Table 1-5. A.C. Electrical Characteristics (T A = – 25 °C to + 70 °C (C), – 40 °C to + 85 °C (I), V Parameter Symbol CC = 1.8 V to 5.5 V) V CC = 1.8 to 5.5 V (Standard Mode) Min Max 100 – – 1 0.3 – – – – – – 3.5 100 5 0 4 4.7 – – 4 4.7 0 0.25 4 4.7 0.3 – – V CC = 2.5 to 5.5 V (Fast Mode) Min 0 0.6 1.3 – – 0.6 0.6 0 0.1 0.6 1.3 – – – Max 400 – – 0.3 0.3 – – – – – – 0.9 50 5 ns ms kHz µs Unit Conditions External clock frequency Clock high time Clock low time Rising time Falling time Start condition hold time Start condition setup time Data input hold time Data input setup time Stop condition setup time Bus free time Data output valid from clock low (note) Noise spike width Write cycle time F CLK tHIGH tLOW tR tF tHD:STA tSU:STA tHD:DAT tSU:DAT tSU:STO tBUF tAA tSP tWR – – – SDA, SCL SDA, SCL – – – – – Before new transmission – – – NOTES : 1. Upon customers request, up to 400 kHz (Max.) in standard mode and 1 MHz in fast mode are available. 2. When acting as a transmitter, the 24LLC02 must provide an internal minimum delay time to bridge the undefined period (minimum 300 ns) of the falling edge of SCL. This is required to avoid unintended generation of a start or stop condition. * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 15 of 19 Rev 1.0 Dec. 26, 2001 Fax:886-3-3521052 24LLC02 2K-Bits Serial EEPROM For Low Power tF SCL tSU:STA SDA In tLOW tHIGH tR tHD:STA tHD:DAT tSU:DAT tSU:STO tAA SDA Out tBUF Figure 1-15. Timing Diagram for Bus Operations ~ ~ SCL ~ ~ ~ ~ SDA WORDn 8th Bit ACK ~ ~ tWR Stop Condition Start Condition Figure 1-16. Write Cycle Timing Diagram * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 16 of 19 Rev 1.0 Dec. 26, 2001 Fax:886-3-3521052 24LLC02 2K-Bits Serial EEPROM For Low Power !    
  D E-PIN O0.118 NOTE 9 E1 PIN #1 INDENT O0.025 DEEP 0.006-0.008 E 7 (4X) 15 (4X) A2 B S e B1 B2 A1 A L C eB SYMBOL A A1 A2 B B1 B2 C D E E1 e L Eb s DIMENSIONS IN MILLIMETERS MIN 0.38 3.25 0.36 1.14 0.81 0.20 9.12 7.62 6.20 3.18 8.38 0.71 NOM 3.30 0.46 1.27 0.99 0.25 9.30 6.35 2.54 0.84 MAX 5.33 3.45 0.56 1.52 1.17 0.33 9.53 8.26 6.60 9.40 0.97 MIN 0.015 0.128 0.014 0.045 0.032 0.008 0.359 0.300 0.244 0.125 0.330 0.028 DIMENSIONS IN INCHS NOM 0.130 0.018 0.050 0.039 0.010 0.366 0.250 0.100 0.033 MAX 0.210 0.136 0.022 0.060 0.046 0.013 0.375 0.325 0.260 0.370 0.038 * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 17 of 19 Rev 1.0 Dec. 26, 2001 Fax:886-3-3521052 24LLC02 2K-Bits Serial EEPROM For Low Power
  
 E H L VIEW "A" D 7 (4X) 0.015x45 7 (4X) A2 A C e VIEW "A" y A1 B SYMBOL A A1 A2 B C D E e H L Y θ DIMENSIONS IN MILLIMETERS MIN 1.47 0.10 0.33 0.19 4.80 3.81 5.79 0.38 0 o DIMENSIONS IN INCHS MIN 0.058 0.004 0.013 0.0075 0.189 0.150 0.228 0.015 0 o NOM 1.60 1.45 0.41 0.20 4.85 3.91 1.27 5.99 0.71 - MAX 1.73 0.25 0.51 0.25 4.95 3.99 6.20 1.27 0.10 8 o NOM 0.063 0.057 0.016 0.008 0.191 0.154 0.050 0.236 0.028 - MAX 0.068 0.010 0.020 0.0098 0.195 0.157 0.244 0.050 0.004 8 o * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 18 of 19 Rev 1.0 Dec. 26, 2001 Fax:886-3-3521052 24LLC02 2K-Bits Serial EEPROM For Low Power
   E1 PIN 1 INDICATOR O0.70 SURFACE POLISHED E L L1 DETAIL A D e A2 E1 L1 A1 y SYMBOLS A A1 A2 B C D E E1 E L L1 Y θ DIMENSIONS IN MILLIMETERS MIN 1.05 0.05 0.20 2.90 6.20 4.30 0.50 0.90 0o NOM 1.10 0.10 1.00 0.25 0.127 3.05 6.40 4.40 0.65 0.60 1.00 4o MAX 1.20 0.15 1.05 0.28 3.10 6.60 4.50 0.70 1.10 0.10 8o * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 19 of 19 Rev 1.0 Dec. 26, 2001 Fax:886-3-3521052 C b A DETAIL A