24LLC16A

24LLC16 16K-Bit-Serial EEPROM OVERVIEW The 24LLC16 serial EEPROM has a 16 Kbits (2,048 bytes) capacity, supporting the standard I2C™-bus serial interface. It is fabricated using CERAMATE’s most advanced CMOS technology. One of its major features is a hardware-based write protection circuit for the entire memory area. Hardware-based write protection is controlled by the state of the write-protect (WP) pin. Using one-page write mode, you can load up to 16 bytes of data into the EEPROM in a single write operation. Another significant feature of the 24LLC1616 is its support for fast mode and standard mode. FEATURES I2C-Bus Interface • • Two-wire serial interface Automatic word address increment Operating Characteristics • • Operating voltage: 2.0 V to 5.5 V Operating current — Maximum write current: < 3 mA at 5.5 V — Maximum read current: < 200 µA at 5.5 V — Maximum stand-by current: < 2 µA at 2.0 V • Operating temperature range — – 25°C to + 70°C (commercial) — – 40°C to + 85°C (industrial) • Operating clock frequencies — 100 kHz at standard mode — 400 kHz at fast mode • Electrostatic discharge (ESD) — 5,000 V (HBM) — 400 V (MM) Packages • 8-pin DIP, SOP, and TSSOP EEPROM • • • • • • • 16 Kbits (2,048 bytes) storage area 16-byte page buffer Typical 3 ms write cycle time with auto-erase function Hardware-based write protection for the entire EEPROM (using the WP pin) EEPROM programming voltage generated on chip 1,000,000 erase/write cycles 100 years data retention ORDERING INFORMATION 24 LLC 16 X X Operating Voltage LLC:2.0~5.5V,CMOS Type 16=16K Temp. grade Blank:-25℃~+70℃ Packing Blank :Tube A :Taping(SOP8) T :Taping(TSSOP8) * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 1 of 22 Rev 1.0 Aug.5, 2002 Fax:886-3-3521052 24LLC16 16K-Bit-Serial EEPROM SDA Start/Stop Logic HV Generation Timing Control WP Control Logic SCL Slave Address Comparator Word Address Pointer Row decoder EEPROM Cell Array 2,048 x 8 bits A0 A1 A2 Column Decoder Data Register DOUT and ACK Figure 5-1. 24LLC16 Block Diagram * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 2 of 22 Rev 1.0 Aug.5, 2002 Fax:886-3-3521052 24LLC16 16K-Bit-Serial EEPROM VCC WP SCL SDA 24LLC16 A0 A1 A2 VSS NOTE: The 24LLC16 is available in 8-pin DIP, SOP, and TSSOP package. Figure 5-2. Pin Assignment Diagram Table 5-1. 24LLC16 Pin Descriptions Name A0, A1, A2 VSS SDA Type – – I/O No internal connection Ground pin. Bi-directional data pin for the I C-bus serial data interface. Schmitt trigger input and open-drain output. An external pull-up resistor must be connected to VDD. Schmitt trigger input pin for serial clock input. Input pin for hardware write protection control. If you tie this pin to VCC, the write function is disabled to protect previously written data in the entire memory; if you tie it to VSS, the write function is enabled. This pin is internally pulled down to VSS. Single power supply. 2 Description Circuit Type – – 3 SCL WP Input Input 2 1 VCC – – NOTE: See the following page for diagrams of pin circuit types 1, 2, and 3. * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 3 of 22 Rev 1.0 Aug.5, 2002 Fax:886-3-3521052 24LLC16 16K-Bit-Serial EEPROM WP SCL Noise Filter Figure 5-3. Pin Circuit Type 1 Figure 5-4. Pin Circuit Type 2 SDA Data Out VSS Noise Filter Data In Figure 5-5. Pin Circuit Type 3 * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 4 of 22 Rev 1.0 Aug.5, 2002 Fax:886-3-3521052 24LLC16 16K-Bit-Serial EEPROM FUNCTION DESCRIPTION I C-BUS INTERFACE 2 The 24LLC16 supports the I C-bus serial interface data transmission protocol. The two-wire bus consists of a serial data line (SDA) and a serial clock line (SCL). The SDA and the SCL lines must be connected to VCC by a pull-up resistor that is located somewhere on the bus. 2 Any device that puts data onto the bus is defined as a “transmitter” and any device that gets data from the bus is a “receiver.” The bus is controlled by a master device which generates the serial clock and start/stop conditions, 2 controlling bus access. Only one 24LLC16 devices can be connected to the I C-bus as slaves (see Figure 56). Both the master and slaves can operate as a transmitter or a receiver, but the master device determines which bus operating mode would be active. VCC R VCC R SDA SCL Master Bus Master (Transmitter/ Receiver) Slave 24LLC16 Figure 5-6. Typical Configuration * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 5 of 22 Rev 1.0 Aug.5, 2002 Fax:886-3-3521052 24LLC16 16K-Bit-Serial EEPROM I2C-BUS PROTOCOLS Here are several rules for I C-bus transfers: — A new data transfer can be initiated only when the bus is currently not busy. — MSB is always transferred first in transmitting data. — During a data transfer, the data line (SDA) must remains stable whenever the clock line (SCL) is High. 2 The I C-bus interface supports the following communication protocols: 2 • • • Bus not busy: The SDA and the SCL lines remain in High level when the bus is not active. Start condition: A start condition is initiated by a High-to-Low transition of the SDA line while SCL remains in High level. All bus commands must be preceded by a start condition. Stop condition: A stop condition is initiated by a Low-to-High transition of the SDA line while SCL remains in High level. All bus operations must be completed by a stop condition (see Figure 5-7). ~ ~ SCL ~ ~ SDA Start Condition Data or Data ACK Valid Change Stop Condition Figure 5-7. Data Transmission Sequence • Data valid: Following a start condition, the data becomes valid if the data line remains stable for the duration of the High period of SCL. New data must be put onto the bus while SCL is Low. Bus timing is one clock pulse per data bit. The number of data bytes to be transferred is determined by the master device. The total number of bytes that can be transferred in one operation is theoretically unlimited. ACK (Acknowledge): An ACK signal indicates that a data transfer is completed successfully. The transmitter (the master or the slave) releases the bus after transmitting eight bits. During the 9th clock, which the master generates, the receiver pulls the SDA line low to acknowledge that it has successfully received the eight bits of data (see Figure 5-8). But the slave does not send an ACK if an internal write cycle is still in progress. In data read operations, the slave releases the SDA line after transmitting 8 bits of data and then monitors the line for an ACK signal during the 9th clock period. If an ACK is detected, the slave will continue to transmit data. If an ACK is not detected, the slave terminates data transmission and waits for a stop condition to be issued by the master before returning to its stand-by mode. * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 6 of 22 Rev 1.0 Aug.5, 2002 Fax:886-3-3521052 • 24LLC16 16K-Bit-Serial EEPROM Master SCL Line Bit 1 Bit 9 Data from Transmitter ACK from Receiver ACK Figure 5-8. Acknowledge Response From Receiver • Slave Address: After the master initiates a start condition, it must output the address of the device to be accessed. The most significant four bits of the slave address are called the “device identifier.” The identifier for the 24LLC16 is “1010B”. The next three bits (B2, B1, B0) are for block selection. They are used by the master to select which of the blocks of internal memory (1 block=256 words) are to be accessed. (see Table 5-2 below.) These bits are in effect the three most significant bits of the word address Read/Write: The final (eighth) bit of the slave address defines the type of operation to be performed. If the R/W bit is “1”, a read operation is executed. If it is “0”, a write operation is executed. Table 5-2. Slave Address Byte Function Read Write Device Identifier b7 1 1 b6 0 0 b5 1 1 b4 0 0 b3 B2 B2 Block Select b2 B1 B1 b1 B0 B0 R/W Bit b0 1 0 • * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 7 of 22 Rev 1.0 Aug.5, 2002 Fax:886-3-3521052 24LLC16 16K-Bit-Serial EEPROM BYTE WRITE OPERATION In a complete byte write operation, the master transmits the slave address, word address, and one data byte to the 24LLC16 slave device (see Figure 5-9). Start Slave Address Word Address Data Stop A C K A C K A C K Figure 5-9. Byte Write Operation Following a start condition, the master sends the device identifier (4 bits), three “don’t care” bits, and an R/W bit set to “0” onto the bus. Then the addressed 24LLC16 generates an ACK, and waits for the next byte. The next byte to be transmitted by the master is the word address. This 8-bit address is written into the word address pointer of the 24LLC16 When the 24LLC16 receives the word address, it responds by issuing an ACK and then waits for the next 8bit data. When it receives the data byte, the 24LLC16 again responds with an ACK. The master terminates the transfer by generating a Stop condition, at which time the 24LLC16 begins the internal write cycle. While the internal write cycle is in progress, all 24LLC16 inputs are disabled and the 24LLC16 does not respond to any additional request from the master. * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 8 of 22 Rev 1.0 Aug.5, 2002 Fax:886-3-3521052 24LLC16 16K-Bit-Serial EEPROM PAGE WRITE OPERATION The 24LLC16 can also perform 16-byte page write operation. A page write operation is initiated in the same way as a byte write operation. However, instead of finishing the write operation after the first data byte is transferred, the master can transmit up to 15 additional bytes. The 24LLC166 responds with an ACK each time it receives a complete byte of data (see Figure 5-10). Start Slave Address Word Address n Data n Data (