CP494

CP494 SWITCHMODE Pulse Width Modulation Control Circuit The CP494 is a fixed frequency, pulse width modulation control circuit designed primarily for SWITCHMODE power supply control. PIN CONNECTIONS • • • • • • • • Complete Pulse Width Modulation Control Circuitry On–Chip Oscillator with Master or Slave Operation On–Chip Error Amplifiers On–Chip 5.0 V Reference Adjustable Deadtime Control Uncommitted Output Transistors Rated to 500 mA Source or Sink Output Control for Push–Pull or Single–Ended Operation Undervoltage Lockout Noninv Input 1 Inv Input 2 Compen/PWN Comp Input 3 Deadtime Control 4 CT 5 RT 6 Ground 7 C1 8 + Error 1 Amp - VCC + 2 Error Amp 5.0 V REF Noninv 16 Input Inv 15 Input 14 Vref Output 13 Contro l 12 VCC ≈ 0.1 V Oscillator Q2 11 C2 10 E2 MAXIMUM RATINGS (Full operating ambient temperature range applies, unless otherwise noted.) Rating Power Supply Voltage Collector Output Voltage Collector Output Current (Each transistor) (Note 1) Amplifier Input Voltage Range Power Dissipation @ TA ≤ 45°C Thermal Resistance, Junction–to–Ambient Operating Junction Temperature Storage Temperature Range Operating Ambient Temperature Range Symbol VCC VC1, VC2 IC1, IC2 VIR PD RqJA TJ Tstg TA Value 42 42 500 –0.3 to +42 1000 80 125 –55 to +125 0 to +70 Unit V V mA V mW °C/W °C °C °C Q1 9 E1 (Top View) Derating Ambient Temperature 1. Maximum thermal limits must be observed. TA 45 °C * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 1 of 11 Rev 1.0 Apr.19,2004 Fax:886-3-3521052 CP494 SWITCHMODE Pulse Width Modulation Control Circuit RECOMMENDED OPERATING CONDITIONS Characteristics Power Supply Voltage Collector Output Voltage Collector Output Current (Each transistor) Amplified Input Voltage Current Into Feedback Terminal Reference Output Current Timing Resistor Timing Capacitor Oscillator Frequency Symbol VCC VC1, VC2 IC1, IC2 Vin lfb lref RT CT fosc Min 7.0 – – –0.3 – – 1.8 0.0047 1.0 Typ 15 30 – – – – 30 0.001 40 Max 40 40 200 VCC – 2.0 0.3 10 500 10 200 Unit V V mA V mA mA kW mF kHz ELECTRICAL CHARACTERISTICS (VCC = 15 V, CT = 0.01 mF, RT = 12 kW, unless otherwise noted.) Characteristics REFERENCE SECTION Reference Voltage (IO = 1.0 mA) Line Regulation (VCC = 7.0 V to 40 V) Load Regulation (IO = 1.0 mA to 10 mA) Short Circuit Output Current (Vref = 0 V) OUTPUT SECTION Collector Off–State Current (VCC = 40 V, VCE = 40 V) Emitter Off–State Current VCC = 40 V, VC = 40 V, VE = 0 V) Collector–Emitter Saturation Voltage (Note 2) Common–Emitter (VE = 0 V, IC = 200 mA) Emitter–Follower (VC = 15 V, IE = –200 mA) Output Control Pin Current Low State (VOC v 0.4 V) High State (VOC = Vref) Output Voltage Rise Time Common–Emitter (See Figure 12) Emitter–Follower (See Figure 13) Output Voltage Fall Time Common–Emitter (See Figure 12) Emitter–Follower (See Figure 13) IC(off) IE(off) – – Vref Regline Regload ISC 4.75 – – 15 Symbol Min For typical values TA = 25°C, for min/max values TA is the operating ambient temperature range that applies, unless otherwise noted. Typ Max Unit 5.0 2.0 3.0 35 5.25 25 15 75 V mV mV mA 2.0 – 100 –100 mA mA V Vsat(C) Vsat(E) IOCL IOCH tr – – – – – – 1.1 1.5 10 0.2 100 100 25 40 1.3 2.5 – 3.5 200 200 ns 100 100 mA mA ns tf – – 2. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient temperature as possible. * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 2 of 11 Rev 1.0 Apr.19,2004 Fax:886-3-3521052 CP494 SWITCHMODE Pulse Width Modulation Control Circuit ELECTRICAL CHARACTERISTICS (VCC = 15 V, CT = 0.01 mF, RT = 12 kW, unless otherwise noted.) Characteristics ERROR AMPLIFIER SECTION Input Offset Voltage (VO (Pin 3) = 2.5 V) Input Offset Current (VO (Pin 3) = 2.5 V) Input Bias Current (VO (Pin 3) = 2.5 V) Input Common Mode Voltage Range (VCC = 40 V, TA = 25°C) Open Loop Voltage Gain (DVO = 3.0 V, VO = 0.5 V to 3.5 V, RL = 2.0 kW) Unity–Gain Crossover Frequency (VO = 0.5 V to 3.5 V, RL = 2.0 kW) Phase Margin at Unity–Gain (VO = 0.5 V to 3.5 V, RL = 2.0 kW) Common Mode Rejection Ratio (VCC = 40 V) Power Supply Rejection Ratio (DVCC = 33 V, VO = 2.5 V, RL = 2.0 kW) Output Sink Current (VO (Pin 3) = 0.7 V) Output Source Current (VO (Pin 3) = 3.5 V) PWM COMPARATOR SECTION (Test Circuit Figure 11) Input Threshold Voltage (Zero Duty Cycle) Input Sink Current (V(Pin 3) = 0.7 V) DEADTIME CONTROL SECTION (Test Circuit Figure 11) Input Bias Current (Pin 4) (VPin 4 = 0 V to 5.25 V) Maximum Duty Cycle, Each Output, Push–Pull Mode (VPin 4 = 0 V, CT = 0.01 mF, RT = 12 kW) (VPin 4 = 0 V, CT = 0.001 mF, RT = 30 kW) Input Threshold Voltage (Pin 4) (Zero Duty Cycle) (Maximum Duty Cycle) OSCILLATOR SECTION Frequency (CT = 0.001 mF, RT = 30 kW) Standard Deviation of Frequency* (CT = 0.001 mF, RT = 30 kW) Frequency Change with Voltage (VCC = 7.0 V to 40 V, TA = 25°C) Frequency Change with Temperature (DTA = Tlow to Thigh) (CT = 0.01 mF, RT = 12 kW) UNDERVOLTAGE LOCKOUT SECTION Turn–On Threshold (VCC increasing, Iref = 1.0 mA) TOTAL DEVICE Standby Supply Current (Pin 6 at Vref, All other inputs and outputs open) (VCC = 15 V) (VCC = 40 V) Average Supply Current (CT = 0.01 mF, RT = 12 kW, V(Pin 4) = 2.0 V) (VCC = 15 V) (See Figure 12) ICC – – – 5.5 7.0 7.0 10 15 mA – mA Vth 5.5 6.43 7.0 V fosc sfosc Dfosc (DV) Dfosc (DT) – – – – 40 3.0 0.1 – – – – 12 kHz % % % IIB (DT) DCmax 45 – Vth – 0 2.8 – 3.3 – 48 45 50 50 V – –2.0 –10 mA % VTH II– – 0.3 2.5 0.7 4.5 – V mA VIO IIO IIB VICR AVOL fC– fm CMRR PSRR IO– IO+ 70 – – 65 – 0.3 2.0 – – – 2.0 5.0 –0.1 –0.3 to VCC–2.0 95 350 65 90 100 0.7 –4.0 – – – – – – – 10 250 –1.0 mV nA mA V dB kHz deg. dB dB mA mA Symbol Min For typical values TA = 25°C, for min/max values TA is the operating ambient temperature range that applies, unless otherwise noted. Typ Max Unit * Standard deviation is a measure of the statistical distribution about the mean as derived from the formula, s N S (Xn – X)2 n=1 N–1 * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 3 of 11 Rev 1.0 Apr.19,2004 Fax:886-3-3521052 CP494 SWITCHMODE Pulse Width Modulation Control Circuit Output Control 13 6 Oscillator RT CT 5 0.12V 4 Deadtime Control 0.7V + 0.7mA + 1 2 PWM Comparator + 15 16 UV Lockout + + 3.5V 14 Ref. Output 7 Gnd 4.9V Reference Regulator 12 VCC + Deadtime Comparator D FlipFlop Ck Q Q Q1 8 9 VCC Q2 11 10 1 2 3 Feedback PWM Comparator Input Error Amp 1 Error Amp 2 This device contains 46 active transistors. Figure 1. Representative Block Diagram Capacitor CT Feedback/PWM Comp. Deadtime Control Flip-Flop Clock Input Flip-Flop Q Flip-Flop Q Output Q1 Emitter Output Q2 Emitter Output Control Figure 2. Timing Diagram * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 4 of 11 Rev 1.0 Apr.19,2004 Fax:886-3-3521052 CP494 SWITCHMODE Pulse Width Modulation Control Circuit APPLICATIONS INFORMATION Description The CP494 is a fixed–frequency pulse width modulation control circuit, incorporating the primary building blocks required for the control of a switching power supply. (See Figure 1.) An internal–linear sawtooth oscillator is frequency– programmable by two external components, RT and CT. The approximate oscillator frequency is determined by: fosc ≈ 1.1 RT • CT For more information refer to Figure 3. fosc , OSCILLATOR FREQUENCY (Hz) Output pulse width modulation is accomplished by comparison of the positive sawtooth waveform across capacitor CT to either of two control signals. The NOR gates, which drive output transistors Q1 and Q2, are enabled only when the flip–flop clock–input line is in its low state. This happens only during that portion of time when the sawtooth voltage is greater than the control signals. Therefore, an increase in control–signal amplitude causes a corresponding linear decrease of output pulse width. (Refer to the Timing Diagram shown in Figure 2.) The control signals are external inputs that can be fed into the deadtime control, the error amplifier inputs, or the feedback input. The deadtime control comparator has an effective 120 mV input offset which limits the minimum output deadtime to approximately the first 4% of the sawtooth–cycle time. This would result in a maximum duty cycle on a given output of 96% with the output control grounded, and 48% with it connected to the reference line. Additional deadtime may be imposed on the output by setting the deadtime–control input to a fixed voltage, ranging between 0 V to 3.3 V. Functional Table Input/Output Controls Grounded @ Vref Output Function Single–ended PWM @ Q1 and Q2 Push–pull Operation common mode input range from –0.3 V to (VCC – 2V), and may be used to sense power–supply output voltage and current. The error–amplifier outputs are active high and are ORed together at the noninverting input of the pulse–width modulator comparator. With this configuration, the amplifier that demands minimum output on time, dominates control of the loop. When capacitor CT is discharged, a positive pulse is generated on the output of the deadtime comparator, which clocks the pulse–steering flip–flop and inhibits the output transistors, Q1 and Q2. With the output–control connected to the reference line, the pulse–steering flip–flop directs the modulated pulses to each of the two output transistors alternately for push–pull operation. The output frequency is equal to half that of the oscillator. Output drive can also be taken from Q1 or Q2, when single–ended operation with a maximum on–time of less than 50% is required. This is desirable when the output transformer has a ringback winding with a catch diode used for snubbing. When higher output–drive currents are required for single–ended operation, Q1 and Q2 may be connected in parallel, and the output–mode pin must be tied to ground to disable the flip–flop. The output frequency will now be equal to that of the oscillator. The CP494 has an internal 5.0 V reference capable of sourcing up to 10 mA of load current for external bias circuits. The reference has an internal accuracy of $5.0% with a typical thermal drift of less than 50 mV over an operating temperature range of 0° to 70°C. 500 k 100 k CT = 0.001 mF VCC = 15 V fout fosc = 1.0 0.5 10 k 0.01 mF 1.0 k 500 1.0 k 2.0 k 5.0 k 0.1 mF 10 k 20 k 50 k 100 k 200 k RT, TIMING RESISTANCE (W) 500 k 1.0 M The pulse width modulator comparator provides a means for the error amplifiers to adjust the output pulse width from the maximum percent on–time, established by the deadtime control input, down to zero, as the voltage at the feedback pin varies from 0.5 V to 3.5 V. Both error amplifiers have a Figure 3. Oscillator Frequency versus Timing Resistance * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 5 of 11 Rev 1.0 Apr.19,2004 Fax:886-3-3521052 CP494 SWITCHMODE Pulse Width Modulation Control Circuit 120 110 100 90 80 70 60 50 40 30 20 10 0 1.0 % DT, PERCENT DEADTIME (EACH OUTPUT) A VOL , OPEN LOOP VOLTAGE GAIN (dB) 20 18 16 14 12 10 8.0 6.0 4.0 2.0 0 500 k 1.0 k 10 k 100 k fosc, OSCILLATOR FREQUENCY (Hz) 500 k 0.001 mF CT = 0.001 mF φ , EXCESS PHASE (DEGREES) VCC = 15 V DVO = 3.0 V RL = 2.0 kW AVOL 10 100 1.0 k 10 k f, FREQUENCY (Hz) 0 20 40 60 80 φ 100 120 140 160 180 100 k 1.0 M Figure 4. Open Loop Voltage Gain and Phase versus Frequency % DC, PERCENT DUTY CYCLE (EACH OUTPUT) 50 V CE(sat) , SATURATION VOLTAGE (V) 40 30 20 10 0 1 2 VCC = 15 V VOC = Vref 1. CT = 0.01 mF 2. RT = 10 kW 2. CT = 0.001 mF 2. RT = 30 kW Figure 5. Percent Deadtime versus Oscillator Frequency 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 0 100 200 300 IE, EMITTER CURRENT (mA) 400 0 1.0 2.0 3.0 3.5 VDT, DEADTIME CONTROL VOLTAGE (IV) Figure 6. Percent Duty Cycle versus Deadtime Control Voltage 2.0 VCE(sat), SATURATION VOLTAGE (V) I CC , SUPPLY CURRENT (mA) 10 9.0 8.0 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0 100 200 300 IC, COLLECTOR CURRENT (mA) 400 0 0 Figure 7. Emitter–Follower Configuration Output Saturation Voltage versus Emitter Current 1.6 1.4 1.2 1.8 1.0 0.8 0.6 0.4 5.0 10 15 20 25 30 35 40 VCC, SUPPLY VOLTAGE (V) Figure 8. Common–Emitter Configuration Output Saturation Voltage versus Collector Current Figure 9. Standby Supply Current versus Supply Voltage * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 6 of 11 Rev 1.0 Apr.19,2004 Fax:886-3-3521052 CP494 SWITCHMODE Pulse Width Modulation Control Circuit VCC = 15V VCC Deadtime Feedback RT CT (+) (-) Error (+) (-) Output Control Gnd 150 2W C1 E1 C2 E2 150 2W Output 1 Output 2 Error Amplifier Under Test + Vin Feedback Terminal (Pin 3) + Vref Other Error Amplifier Test Inputs 50k Ref Out Figure 10. Error–Amplifier Characteristics Figure 11. Deadtime and Feedback Control Circuit 15V RL 68 C Each Output Transistor Q E CL 15pF VC Each Output Transistor Q E VEE RL 68 CL 15pF 15V C 90% VCC 10% tr tf 90% 10% 10% 90% 90% VEE 10% Gnd tr tf Figure 12. Common–Emitter Configuration Test Circuit and Waveform Figure 13. Emitter–Follower Configuration Test Circuit and Waveform * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 7 of 11 Rev 1.0 Apr.19,2004 Fax:886-3-3521052 CP494 SWITCHMODE Pulse Width Modulation Control Circuit VO Vref 1 R2 2 R1 VO To Output Voltage of System R1 R2 To Output Voltage of System Error Amp + Error Amp 3 R1 1 + - Vref R2 Negative Output Voltage VO = Vref 2 Positive Output Voltage VO = Vref 1+ R1 R2 Figure 14. Error–Amplifier Sensing Techniques Output Control Output Vref Q RT 6 30k 5 0.001 CT DT R1 4 R2 Output Q Vref DT CS 4 RS Max. % on Time, each output ≈ 45 - 80 1+ R1 R2 Figure 15. Deadtime Control Circuit Figure 16. Soft–Start Circuit C1 Q1 Output Control E1 QC C1 2.4 V ≤ VOC ≤ Vref Output Control Q1 E1 1.0 mA to 250 mA Single-Ended Q2 1.0 mA to 500 mA C2 E2 Push-Pull Q2 C2 E2 1.0 mA to 250 mA 0 ≤ VOC ≤ 0.4 V QE Figure 17. Output Connections for Single–Ended and Push–Pull Configurations * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 8 of 11 Rev 1.0 Apr.19,2004 Fax:886-3-3521052 CP494 SWITCHMODE Pulse Width Modulation Control Circuit Vref 6 RT 5 CT RT CT Master RS Vin > 40V 1N975A VZ = 39V VCC 12 5.0V Ref 270 Gnd 7 Vref 6 5 RT CT Slave (Additional Circuits) Figure 18. Slaving Two or More Control Circuits Figure 19. Operation with Vin > 40 V Using External Zener +Vin = 8.0V to 20V 12 1 2 1M 33k 0.01 0.01 3 15 16 + Comp + OC VREF DT 13 4.7k 4.7k 14 + 4 5 CT 6 RT Gnd 7 15k 9 E1 10 E2 VCC C1 8 47 Tip 32 + 50 25V T1 1N4934 22 k + 50 35V 4.7k 1.0 240 +VO = 28 V IO = 0.2 A L1 CP494 C2 11 Tip 32 47 + 50 35V 1N4934 10 10k 0.001 All capacitors in mF Figure 20. Pulse Width Modulated Push–Pull Converter Test Line Regulation Load Regulation Output Ripple Short Circuit Current Efficiency Conditions Vin = 10 V to 40 V Vin = 28 V, IO = 1.0 mA to 1.0 A Vin = 28 V, IO = 1.0 A Vin = 28 V, RL = 0.1 W Vin = 28 V, IO = 1.0 A Results 14 mV 0.28% 3.0 mV 0.06% 65 mV pp P.A.R.D. 1.6 A 71% L1 - 3.5 mH @ 0.3 A T1 - Primary: 20T C.T. #28 AWG T1 - Secondary: 12OT C.T. #36 AWG T1 - Core: Ferroxcube 1408P-L00-3CB * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 9 of 11 Rev 1.0 Apr.19,2004 Fax:886-3-3521052 CP494 SWITCHMODE Pulse Width Modulation Control Circuit +Vin = 10V to 40V 1.0mH @ 2A Tip 32A +VO = 5.0 V IO = 1.0 A 47 150 12 VCC 0.1 C2 Comp 50 50V + + 3 2 1 14 5.1k MR850 500 10V 5.1k 5.1k + 1.0M 47k 8 C1 11 CP494 Vref CT 5 0.001 RT 6 47k D.T. O.C. Gnd E1 4 13 7 9 E2 10 - 15 16 + + 150 50 10V 0.1 Figure 21. Pulse Width Modulated Step–Down Converter Test Line Regulation Load Regulation Output Ripple Short Circuit Current Efficiency Conditions Vin = 8.0 V to 40 V Vin = 12.6 V, IO = 0.2 mA to 200 mA Vin = 12.6 V, IO = 200 mA Vin = 12.6 V, RL = 0.1 W Vin = 12.6 V, IO = 200 mA Results 3.0 mV 5.0 mV 40 mV pp 0.01% 0.02% P.A.R.D. 250 mA 72% * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 10 of 11 Rev 1.0 Apr.19,2004 Fax:886-3-3521052 CP494 SWITCHMODE Pulse Width Modulation Control Circuit CP494N 19.4 ± 0.3 16 9 6.5 ± 0.3 CP494 10.0 ± 0.2 16 6.2 ± 0.3 4.4 ± 0.2 9 0.51Min. 1 8 7.62 3.2 ± 0.2 4.25 ± 0.3 1 1.5 ± 0.1 8 0.11 0.3 ± 0.1 1.27 2.54 0.5 ± 0.1 0.4 ± 0.1 0.3Min. 0.15 0° ~ 15° DIP16 SOP16 * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 11 of 11 Rev 1.0 Apr.19,2004 Fax:886-3-3521052 0.15 ± 0.1