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CEB50P03

CEB50P03

  • 厂商:

    CET(华瑞)

  • 封装:

  • 描述:

    CEB50P03 - P-Channel Enhancement Mode Field Effect Transistor - Chino-Excel Technology

  • 数据手册
  • 价格&库存
CEB50P03 数据手册
CEP50P03/CEB50P03 P-Channel Enhancement Mode Field Effect Transistor FEATURES -30V, -47A, RDS(ON) =20mΩ @VGS = -10V. RDS(ON) =32mΩ @VGS = -4.5V. Super high dense cell design for extremely low RDS(ON). High power and current handing capability. Lead free product is acquired. TO-220 & TO-263 package. D D G S CEB SERIES TO-263(DD-PAK) G G D S CEP SERIES TO-220 S ABSOLUTE MAXIMUM RATINGS Parameter Drain-Source Voltage Gate-Source Voltage Drain Current-Continuous Drain Current-Pulsed a Tc = 25 C unless otherwise noted Symbol Limit VDS VGS ID IDM PD TJ,Tstg -30 Units V V A A W W/ C C ±20 -47 -188 79 0.53 -55 to 175 Maximum Power Dissipation @ TC = 25 C - Derate above 25 C Operating and Store Temperature Range Thermal Characteristics Parameter Thermal Resistance, Junction-to-Case Thermal Resistance, Junction-to-Ambient Symbol RθJC RθJA Limit 1.9 62.5 Units C/W C/W Specification and data are subject to change without notice . 1 Rev 2. 2005.May http://www.cetsemi.com CEP50P03/CEB50P03 Electrical Characteristics Parameter Off Characteristics Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current Gate Body Leakage Current, Forward Gate Body Leakage Current, Reverse On Characteristics c Gate Threshold Voltage Static Drain-Source On-Resistance Forward Transconductance Dynamic Characteristics Input Capacitance Output Capacitance Reverse Transfer Capacitance Switching Characteristics d Turn-On Delay Time Turn-On Rise Time Turn-Off Delay Time Turn-Off Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Drain-Source Diode Forward Current b Drain-Source Diode Forward Voltage c td(on) tr td(off) tf Qg Qgs Qgd IS VSD VGS = 0V, IS = -2.1A VDS = -15V, ID = -25A, VGS = -5V VDD = -15V, ID = -1A, VGS = -10V, RGEN = 6Ω 12 6 110 35 22 7 8 -2.1 -1.2 24 18 140 70 28 ns ns ns ns nC nC nC A V d TA = 25 C unless otherwise noted Symbol BVDSS IDSS IGSSF IGSSR VGS(th) RDS(on) gFS Ciss Coss Crss Test Condition VGS = 0V, ID = -250µA VDS = -24V, VGS = 0V VGS = 20V, VDS = 0V VGS = -20V, VDS = 0V VGS = VDS, ID = -250µA VGS = -10V, ID = -25A VGS = -4.5V, ID = -20A VDS = -15V, ID = -25A -1 17 25 20 2220 550 230 Min -30 -1 100 -100 -3 20 32 Typ Max Units V µA 5 5 nA nA V mΩ mΩ S pF pF pF VDS = -15V, VGS = 0V, f = 1.0 MHz Drain-Source Diode Characteristics and Maximun Ratings Notes : a.Repetitive Rating : Pulse width limited by maximum junction temperature. b.Surface Mounted on FR4 Board, t < 10 sec. c.Pulse Test : Pulse Width < 300µs, Duty Cycle < 2%. d.Guaranteed by design, not subject to production testing. 2 CEP50P03/CEB50P03 25 -VGS=10,8,7,6,5V 100 25 C -ID, Drain Current (A) 20 -ID, Drain Current (A) 80 15 60 -VGS=4V 10 40 TJ=125 C 20 -55 C 5 -VGS=3V 0 0.0 0 0.5 1.0 1.5 2.0 2.5 0 1 2 3 4 5 6 -VDS, Drain-to-Source Voltage (V) Figure 1. Output Characteristics 3000 2500 Ciss 2000 1500 1000 500 0 0 5 10 15 20 25 Coss Crss 2.2 1.9 1.6 1.3 1.0 0.7 0.4 -100 -VGS, Gate-to-Source Voltage (V) Figure 2. Transfer Characteristics RDS(ON), Normalized RDS(ON), On-Resistance(Ohms) ID=-25A VGS=-10V C, Capacitance (pF) -50 0 50 100 150 200 -VDS, Drain-to-Source Voltage (V) Figure 3. Capacitance 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 -50 TJ, Junction Temperature( C) Figure 4. On-Resistance Variation with Temperature -IS, Source-drain current (A) VGS=0V 2 VTH, Normalized Gate-Source Threshold Voltage VDS=VGS ID=-250µA 10 10 1 10 -25 0 25 50 75 100 125 150 0 0.4 0.6 0.8 1.0 1.2 1.4 TJ, Junction Temperature( C) Figure 5. Gate Threshold Variation with Temperature -VSD, Body Diode Forward Voltage (V) Figure 6. Body Diode Forward Voltage Variation with Source Current 3 CEP50P03/CEB50P03 -VGS, Gate to Source Voltage (V) 10 VDS=-15V ID=-25A 10 3 8 -ID, Drain Current (A) RDS(ON)Limit 10 2 100µs 1ms 10ms 6 5 4 10 1 DC TC=25 C TJ=175 C Single Pulse -1 2 0 0 5 10 15 20 25 30 10 0 10 10 0 10 1 10 2 Qg, Total Gate Charge (nC) Figure 7. Gate Charge -VDS, Drain-Source Voltage (V) Figure 8. Maximum Safe Operating Area VDD t on V IN D VGS RGEN G 90% toff tr 90% RL VOUT td(on) VOUT td(off) 90% 10% tf 10% INVERTED S VIN 50% 10% 50% PULSE WIDTH Figure 9. Switching Test Circuit Figure 10. Switching Waveforms r(t),Normalized Effective Transient Thermal Impedance 10 0 D=0.5 0.2 10 -1 0.1 0.05 0.02 0.01 Single Pulse PDM t1 t2 1. RθJC (t)=r (t) * RθJC 2. RθJC=See Datasheet 3. TJM-TC = P* RθJC (t) 4. Duty Cycle, D=t1/t2 10 -2 10 -4 10 -3 10 -2 10 -1 10 0 10 1 10 2 Square Wave Pulse Duration (sec) Figure 11. Normalized Thermal Transient Impedance Curve 4
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