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CED05N65

CED05N65

  • 厂商:

    CET(华瑞)

  • 封装:

  • 描述:

    CED05N65 - N-Channel Enhancement Mode Field Effect Transistor - Chino-Excel Technology

  • 数据手册
  • 价格&库存
CED05N65 数据手册
N-Channel Enhancement Mode Field Effect Transistor FEATURES 650V, 4A, RDS(ON) = 2.4Ω @VGS = 10V. Super high dense cell design for extremely low RDS(ON). High power and current handing capability. Lead free product is acquired. TO-251 & TO-252 package. CED05N65/CEU05N65 D D G S CEU SERIES TO-252(D-PAK) G D G S CED SERIES TO-251(I-PAK) S ABSOLUTE MAXIMUM RATINGS Parameter Drain-Source Voltage Gate-Source Voltage Drain Current-Continuous Drain Current-Pulsed a Tc = 25 C unless otherwise noted Symbol Limit VDS VGS ID IDM PD TJ,Tstg 650 Units V V A A W W/ C C ±30 4 16 56 0.45 -55 to 150 Maximum Power Dissipation @ TC = 25 C - Derate above 25 C Operating and Store Temperature Range Thermal Characteristics Parameter Thermal Resistance, Junction-to-Case Thermal Resistance, Junction-to-Ambient Symbol RθJC RθJA Limit 2.2 50 Units C/W C/W Details are subject to change without notice . 1 Rev 2. 2007.July http://www.cetsemi.com CED05N65/CEU05N65 Electrical Characteristics Parameter Off Characteristics Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current Gate Body Leakage Current, Forward Gate Body Leakage Current, Reverse On Characteristics b Gate Threshold Voltage Static Drain-Source On-Resistance Dynamic Characteristics c Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Switching Characteristics c Turn-On Delay Time Turn-On Rise Time Turn-Off Delay Time Turn-Off Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Drain-Source Diode Forward Current Drain-Source Diode Forward Voltage b td(on) tr td(off) tf Qg Qgs Qgd IS VSD VGS = 0V, IS = 4A VDS = 480V, ID = 4A, VGS = 10V VDD = 300V, ID = 4A, VGS = 10V, RGEN = 25Ω 23 13 35 11 8.3 3 3.1 4 1.5 46 26 70 22 11 ns ns ns ns nC nC nC A V gFS Ciss Coss Crss VDS = 10V, ID = 2A VDS = 25V, VGS = 0V, f = 1.0 MHz 3 570 105 20 S pF pF pF VGS(th) RDS(on) VGS = VDS, ID = 250µA VGS = 10V, ID = 2A 2.5 2 4.5 2.4 V Ω BVDSS IDSS IGSSF IGSSR VGS = 0V, ID = 250µA VDS = 650V, VGS = 0V VGS = 30V, VDS = 0V VGS = -30V, VDS = 0V 650 25 100 -100 V µA Tc = 25 C unless otherwise noted Symbol Test Condition Min Typ Max Units 4 nA nA Drain-Source Diode Characteristics and Maximun Ratings Notes : a.Repetitive Rating : Pulse width limited by maximum junction temperature. b.Device Mounted on FR4 Board, t < 10 sec. c.Pulse Test : Pulse Width < 300µs, Duty Cycle < 2%. d.Guaranteed by design, not subject to production testing. e.L = 10mH, IAS = 1A, VDD = 50V, RG = 25Ω, Starting TJ = 25 C 2 CED05N65/CEU05N65 6 9 VGS=10,8,7V 7.5 6 4.5 3 1.5 0 25 C TJ=125C 1 2 3 4 -55 C 5 6 ID, Drain Current (A) 4 3 2 VGS=5V 1 0 0.0 5 10 15 20 25 30 ID, Drain Current (A) 5 VDS, Drain-to-Source Voltage (V) Figure 1. Output Characteristics 1200 1000 800 600 400 200 0 Coss Crss 0 5 10 15 20 25 Ciss 1.7 1.5 1.3 1.1 0.9 0.7 0.5 -100 VGS, Gate-to-Source Voltage (V) Figure 2. Transfer Characteristics ID=2A VGS=10V RDS(ON), Normalized RDS(ON), On-Resistance(Ohms) C, Capacitance (pF) -50 0 50 100 150 200 VDS, Drain-to-Source Voltage (V) Figure 3. Capacitance 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 -50 VDS=VGS TJ, Junction Temperature( C) Figure 4. On-Resistance Variation with Temperature VGS=0V 10 1 VTH, Normalized Gate-Source Threshold Voltage IS, Source-drain current (A) ID=250µA 10 0 -25 0 25 50 75 100 125 150 10-1 0.4 0.7 1.0 1.3 1.7 2.0 TJ, Junction Temperature( C) Figure 5. Gate Threshold Variation with Temperature VSD, Body Diode Forward Voltage (V) Figure 6. Body Diode Forward Voltage Variation with Source Current 3 CED05N65/CEU05N65 VGS, Gate to Source Voltage (V) 10 8 6 4 2 0 VDS=480V ID=4A 10 1 RDS(ON)Limit ID, Drain Current (A) 100ms 1ms 10ms DC 4 10 0 10 -1 0 2 4 6 8 10 10 -2 TC=25 C TJ=175 C Single Pulse 10 0 10 1 10 2 10 3 Qg, Total Gate Charge (nC) Figure 7. Gate Charge VDD t on V IN VGS RGEN G RL D VOUT td(on) VOUT 10% VDS, Drain-Source Voltage (V) Figure 8. Maximum Safe Operating Area toff tr 90% td(off) 90% 10% tf INVERTED 90% S VIN 50% 10% 50% PULSE WIDTH Figure 9. Switching Test Circuit Figure 10. Switching Waveforms r(t),Normalized Effective Transient Thermal Impedance 10 0 D=0.5 0.2 10 -1 0.1 0.05 0.02 0.01 Single Pulse PDM t1 t2 10 -2 1. RθJA (t)=r (t) * RθJA 2. RθJA=See Datasheet 3. TJM-TA = P* RθJC (t) 4. Duty Cycle, D=t1/t2 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 Square Wave Pulse Duration (sec) Figure 11. Normalized Thermal Transient Impedance Curve 4
CED05N65 价格&库存

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