CED21A2

CED21A2

  • 厂商:

    CET(华瑞)

  • 封装:

  • 描述:

    CED21A2 - N-Channel Enhancement Mode Field Effect Transistor - Chino-Excel Technology

  • 数据手册
  • 价格&库存
CED21A2 数据手册
CED21A2/CEU21A2 N-Channel Enhancement Mode Field Effect Transistor FEATURES 20V, 20A, RDS(ON) = 40mΩ @VGS = 4.5V. RDS(ON) = 70mΩ @VGS = 2.5V. Super high dense cell design for extremely low RDS(ON). High power and current handing capability. Lead free product is acquired. TO-251 & TO-252 package. D D G S CEU SERIES TO-252(D-PAK) G D G S CED SERIES TO-251(I-PAK) S ABSOLUTE MAXIMUM RATINGS Parameter Drain-Source Voltage Gate-Source Voltage Drain Current-Continuous Drain Current-Pulsed a Tc = 25 C unless otherwise noted Symbol Limit VDS VGS ID IDM PD TJ,Tstg 20 Units V V A A W W/ C C ±12 20 60 38 0.25 -55 to 175 Maximum Power Dissipation @ TC = 25 C - Derate above 25 C Operating and Store Temperature Range Thermal Characteristics Parameter Thermal Resistance, Junction-to-Case Thermal Resistance, Junction-to-Ambient Symbol RθJC RθJA Limit 4 50 Units C/W C/W 2003.July 6 - 38 http://www.cetsemi.com CED21A2/CEU21A2 Electrical Characteristics Parameter Off Characteristics Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current Gate Body Leakage Current, Forward Gate Body Leakage Current, Reverse On Characteristics b Gate Threshold Voltage Static Drain-Source On-Resistance Forwand Transconductance Dynamic Characteristics Input Capacitance Output Capacitance Reverse Transfer Capacitance Switching Characteristics c Turn-On Delay Time Turn-On Rise Time Turn-Off Delay Time Turn-Off Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Drain-Source Diode Forward Current Drain-Source Diode Forward Voltage b td(on) tr td(off) tf Qg Qgs Qgd IS VSD VGS = 0V, IS = 4A VDS = 10V, ID = 8A, VGS = 4.5V VDD = 10V, ID = 1A, VGS = 4.5V, RGEN = 6Ω 20 12 50 10 11 3.6 2.8 20 1.3 50 30 100 25 15 ns ns ns ns nC nC nC A V c Tc = 25 C unless otherwise noted Symbol BVDSS IDSS IGSSF IGSSR VGS(th) RDS(on) gFS Ciss Coss Crss Test Condition VGS = 0V, ID = 250µA VDS = 20V, VGS = 0V VGS = 12V, VDS = 0V VGS = -12V, VDS = 0V VGS = VDS, ID = 250µA VGS = 4.5V, ID = 8A VGS = 2.5V, ID = 6.6A VDS = 10V, ID = 8A 0.5 30 55 15 511 216 73 Min 20 1 100 -100 1.5 40 70 Typ Max Units V µA nA nA V mΩ mΩ S pF pF pF 6 VDS = 15V, VGS = 0V, f = 1.0 MHz Drain-Source Diode Characteristics and Maximun Ratings Notes : a.Repetitive Rating : Pulse width limited by maximum junction temperature. b.Pulse Test : Pulse Width < 300µs, Duty Cycle < 2%. c.Guaranteed by design, not subject to production testing. 6 - 39 CED21A2/CEU21A2 30 VGS=4.5,3.5,3.0V VGS=2.0V 25 20 15 10 5 0 0 1 2 3 4 VGS=1.5V 15 25 C ID, Drain Current (A) ID, Drain Current (A) 12 9 VGS=2.5V 6 3 TJ=125 C 0 0.5 1.0 1.5 -55 C 2.0 2.5 VDS, Drain-to-Source Voltage (V) Figure 1. Output Characteristics 900 750 600 450 300 Coss 150 0 0 5 10 15 20 25 Crss 2.2 1.9 1.6 1.3 1.0 0.7 0.4 -100 VGS, Gate-to-Source Voltage (V) Figure 2. Transfer Characteristics Ciss RDS(ON), Normalized RDS(ON), On-Resistance(Ohms) ID=8A VGS=4.5V C, Capacitance (pF) -50 0 50 100 150 200 VDS, Drain-to-Source Voltage (V) Figure 3. Capacitance 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 -50 TJ, Junction Temperature( C) Figure 4. On-Resistance Variation with Temperature VGS=0V 1 VTH, Normalized Gate-Source Threshold Voltage VDS=VGS ID=250µA IS, Source-drain current (A) 25 50 75 100 125 150 10 10 0 10 -25 0 -1 0.4 0.6 0.8 1.0 1.2 1.4 TJ, Junction Temperature( C) Figure 5. Gate Threshold Variation with Temperature VSD, Body Diode Forward Voltage (V) Figure 6. Body Diode Forward Voltage Variation with Source Current 6 - 40 CED21A2/CEU21A2 VGS, Gate to Source Voltage (V) 5 VDS=8V ID=10A 10 2 RDS(ON)Limit ID, Drain Current (A) 4 10ms 10 1 100ms 1s 10s DC 3 10 0 2 1 10 -1 0 0 3 6 9 12 10 -2 TC=25 C TJ=175 C Single Pulse 10 -1 6 10 0 10 1 10 2 Qg, Total Gate Charge (nC) Figure 7. Gate Charge VDS, Drain-Source Voltage (V) Figure 8. Maximum Safe Operating Area VDD t on V IN D VGS RGEN G 90% toff tr 90% RL VOUT td(on) VOUT td(off) 90% 10% tf 10% INVERTED S VIN 50% 10% 50% PULSE WIDTH Figure 9. Switching Test Circuit Figure 10. Switching Waveforms 10 0 r(t),Normalized Effective Transient Thermal Impedance D=0.5 0.2 10 -1 0.1 0.05 PDM 0.02 10 -2 0.01 t1 t2 1. RθJC (t)=r (t) * RθJC 2. RθJC=See Datasheet 3. TJM-TC = P* RθJC (t) 4. Duty Cycle, D=t1/t2 Single Pulse 10 -3 10 -1 10 0 10 1 10 5 10 3 10 4 10 5 Square Wave Pulse Duration (msec) Figure 11. Normalized Thermal Transient Impedance Curve 6 - 41
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