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CED50N06

CED50N06

  • 厂商:

    CET(华瑞)

  • 封装:

  • 描述:

    CED50N06 - N-Channel Enhancement Mode Field Effect Transistor - Chino-Excel Technology

  • 数据手册
  • 价格&库存
CED50N06 数据手册
CED50N06/CEU50N06 N-Channel Enhancement Mode Field Effect Transistor FEATURES 60V, 36A , RDS(ON) = 18mΩ(typ) @VGS = 10V. Super high dense cell design for extremely low RDS(ON). High power and current handing capability. Lead free product is acquired. TO-251 & TO-252 package. D D G S CEU SERIES TO-252(D-PAK) G D G S CED SERIES TO-251(I-PAK) S ABSOLUTE MAXIMUM RATINGS Parameter Drain-Source Voltage Gate-Source Voltage Drain Current-Continuous Drain Current-Pulsed a Tc = 25 C unless otherwise noted Symbol Limit VDS VGS ID IDM PD TJ,Tstg 60 Units V V A A W W/ C C ±20 36 105 68 0.45 -55 to 175 Maximum Power Dissipation @ TC = 25 C - Derate above 25 C Operating and Store Temperature Range Thermal Characteristics Parameter Thermal Resistance, Junction-to-Case Thermal Resistance, Junction-to-Ambient Symbol RθJC RθJA Limit 2.2 50 Units C/W C/W Details are subject to change without notice . 6 - 66 Rev 1. 2006.Oct http://www.cetsemi.com CED50N06/CEU50N06 Electrical Characteristics Parameter Off Characteristics Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current Gate Body Leakage Current, Forward Gate Body Leakage Current, Reverse On Characteristics b Gate Threshold Voltage Static Drain-Source On-Resistance Dynamic Characteristics c Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Switching Characteristics c Turn-On Delay Time Turn-On Rise Time Turn-Off Delay Time Turn-Off Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Drain-Source Diode Forward Current Drain-Source Diode Forward Voltage b td(on) tr td(off) tf Qg Qgs Qgd IS VSD VGS = 0V, IS = 15A VDS = 48V, ID = 36A, VGS = 10V VDD = 30V, ID = 36A, VGS = 10V, RGEN = 3.6Ω 21 13 40 9 31 8 13 35 1.5 45 33 80 27 40 ns ns ns ns nC nC nC A V VGS(th) RDS(on) VGS = VDS, ID = 250µA VGS = 10V, ID = 15A 2 18 4 23 V mΩ BVDSS IDSS IGSSF IGSSR VGS = 0V, ID = 250µA VDS = 60V, VGS = 0V VGS = 20V, VDS = 0V VGS = -20V, VDS = 0V 60 1 100 -100 V µA Tc = 25 C unless otherwise noted Symbol Test Condition Min Typ Max Units nA nA 6 gFS Ciss Coss Crss VDS = 10V, ID = 15A VDS = 25V, VGS = 0V, f = 1.0 MHz 15 1278 430 80 S pF pF pF Drain-Source Diode Characteristics and Maximun Ratings Notes : a.Repetitive Rating : Pulse width limited by maximum junction temperature. b.Pulse Test : Pulse Width < 300µs, Duty Cycle < 2%. c.Guaranteed by design, not subject to production testing. 6 - 67 CED50N06/CEU50N06 120 125 VGS=10V 25 C ID, Drain Current (A) 80 VGS=7V 60 40 20 0 0 1 2 3 4 5 6 ID, Drain Current (A) 100 VGS=8V 100 75 VGS=6V VGS=5V VGS=4V 50 25 TJ=125 C 0 0 2 4 6 8 10 -55 C VDS, Drain-to-Source Voltage (V) Figure 1. Output Characteristics 1800 1500 Ciss 1200 900 600 300 Crss 0 0 5 10 15 20 25 2.6 2.2 1.8 1.4 1.0 0.6 0.2 -100 VGS, Gate-to-Source Voltage (V) Figure 2. Transfer Characteristics Coss RDS(ON), Normalized RDS(ON), On-Resistance(Ohms) ID=15A VGS=10V C, Capacitance (pF) -50 0 50 100 150 200 VDS, Drain-to-Source Voltage (V) Figure 3. Capacitance 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 -50 TJ, Junction Temperature( C) Figure 4. On-Resistance Variation with Temperature VGS=0V 1 VTH, Normalized Gate-Source Threshold Voltage VDS=VGS ID=250µA IS, Source-drain current (A) 25 50 75 100 125 150 10 10 0 10 -25 0 -1 0.4 0.6 0.8 1.0 1.2 1.4 TJ, Junction Temperature( C) Figure 5. Gate Threshold Variation with Temperature VSD, Body Diode Forward Voltage (V) Figure 6. Body Diode Forward Voltage Variation with Source Current 6 - 68 CED50N06/CEU50N06 VGS, Gate to Source Voltage (V) 15 V =48V DS ID=36A 10 3 ID, Drain Current (A) 12 9 6 3 0 10 2 RDS(ON)Limit 100ms 1ms 10ms DC 10 1 10 0 0 10 20 30 40 10 -1 TC=25 C TJ=175 C Single Pulse 10 -2 6 10 0 10 -1 10 1 10 2 Qg, Total Gate Charge (nC) Figure 7. Gate Charge VDD t on V IN VGS RGEN G RL D VOUT td(on) VOUT 10% VDS, Drain-Source Voltage (V) Figure 8. Maximum Safe Operating Area toff tr 90% td(off) 90% 10% tf INVERTED 90% S VIN 50% 10% 50% PULSE WIDTH Figure 9. Switching Test Circuit Figure 10. Switching Waveforms r(t),Normalized Effective Transient Thermal Impedance 10 0 D=0.5 0.2 10 -1 0.1 0.05 0.02 0.01 Single Pulse PDM t1 t2 10 -2 1. RθJC (t)=r (t) * RθJC 2. RθJC=See Datasheet 3. TJM-TC = P* RθJC (t) 4. Duty Cycle, D=t1/t2 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 Square Wave Pulse Duration (sec) Figure 11. Normalized Thermal Transient Impedance Curve 6 - 69
CED50N06 价格&库存

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