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CED6186

CED6186

  • 厂商:

    CET(华瑞)

  • 封装:

  • 描述:

    CED6186 - N-Channel Enhancement Mode Field Effect Transistor - Chino-Excel Technology

  • 数据手册
  • 价格&库存
CED6186 数据手册
N-Channel Enhancement Mode Field Effect Transistor FEATURES 60V, 28A, RDS(ON) = 23mΩ @VGS = 10V. RDS(ON) = 38mΩ @VGS = 4.5V. Super high dense cell design for extremely low RDS(ON). High power and current handing capability. Lead free product is acquired. TO-251 & TO-252 package. CED6186/CEU6186 PRELIMINARY D D G S CEU SERIES TO-252(D-PAK) G D G S CED SERIES TO-251(I-PAK) S ABSOLUTE MAXIMUM RATINGS Parameter Drain-Source Voltage Gate-Source Voltage Drain Current-Continuous Drain Current-Pulsed a Tc = 25 C unless otherwise noted Symbol Limit VDS VGS ID IDM PD TJ,Tstg 60 Units V V A A W W/ C C ±20 28 112 38 0.25 -55 to 175 Maximum Power Dissipation @ TC = 25 C - Derate above 25 C Operating and Store Temperature Range Thermal Characteristics Parameter Thermal Resistance, Junction-to-Case Thermal Resistance, Junction-to-Ambient Symbol RθJC RθJA Limit 4 50 Units C/W C/W Details are subject to change without notice . 1 Rev 1. 2010.July http://www.cetsemi.com CED6186/CEU6186 Electrical Characteristics Parameter Off Characteristics Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current Gate Body Leakage Current, Forward Gate Body Leakage Current, Reverse On Characteristics b Gate Threshold Voltage Static Drain-Source On-Resistance Forward Transconductance Dynamic Characteristics Input Capacitance Output Capacitance Reverse Transfer Capacitance Switching Characteristics c Turn-On Delay Time Turn-On Rise Time Turn-Off Delay Time Turn-Off Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Drain-Source Diode Forward Current Drain-Source Diode Forward Voltage b td(on) tr td(off) tf Qg Qgs Qgd IS VSD VGS = 0V, IS = 28A VDS = 48V, ID = 28A, VGS = 10V VDD = 30V, ID = 19A, VGS = 10V, RGEN = 4.7Ω 15 5 38 10 24 6 6 28 1.2 30 10 76 20 31 ns ns ns ns nC nC nC A V c Tc = 25 C unless otherwise noted Symbol BVDSS IDSS IGSSF IGSSR VGS(th) RDS(on) gFS Ciss Coss Crss Test Condition VGS = 0V, ID = 250µA VDS = 60V, VGS = 0V VGS = 20V, VDS = 0V VGS = -20V, VDS = 0V VGS = VDS, ID = 250µA VGS = 10V, ID = 19A VGS = 4.5V, ID = 10A VDS = 10V, ID = 28A 1 18 27 23 1120 125 75 Min 60 1 100 -100 3 23 38 Typ Max Units V µA nA nA V mΩ mΩ S pF pF pF VDS = 25V, VGS = 0V, f = 1.0 MHz Drain-Source Diode Characteristics and Maximun Ratings Notes : a.Repetitive Rating : Pulse width limited by maximum junction temperature. b.Pulse Test : Pulse Width < 300µs, Duty Cycle < 2%. c.Guaranteed by design, not subject to production testing. 2 CED6186/CEU6186 24 VGS=10,8,7V 50 25 C 40 30 20 10 0 TJ=125 C -55 C 0 2 4 6 8 10 ID, Drain Current (A) 16 12 8 4 0 0.0 VGS=4V VGS=3V 0.5 1.0 1.5 2.0 2.5 3.0 ID, Drain Current (A) 20 VDS, Drain-to-Source Voltage (V) Figure 1. Output Characteristics 1200 1000 800 600 400 200 0 Coss Crss 0 5 10 15 20 25 2.2 1.9 1.6 1.3 1.0 0.7 0.4 -100 VGS, Gate-to-Source Voltage (V) Figure 2. Transfer Characteristics ID=19A VGS=10V RDS(ON), Normalized RDS(ON), On-Resistance(Ohms) Ciss C, Capacitance (pF) -50 0 50 100 150 200 VDS, Drain-to-Source Voltage (V) Figure 3. Capacitance 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 -50 VDS=VGS TJ, Junction Temperature( C) Figure 4. On-Resistance Variation with Temperature IS, Source-drain current (A) VGS=0V 10 2 VTH, Normalized Gate-Source Threshold Voltage ID=250µA 10 1 -25 0 25 50 75 100 125 150 10 0 0.4 0.6 0.8 1.0 1.2 1.4 TJ, Junction Temperature( C) Figure 5. Gate Threshold Variation with Temperature VSD, Body Diode Forward Voltage (V) Figure 6. Body Diode Forward Voltage Variation with Source Current 3 CED6186/CEU6186 VGS, Gate to Source Voltage (V) 10 8 6 4 2 0 VDS=48V ID=28A 10 3 ID, Drain Current (A) 10 2 RDS(ON)Limit 1ms 100ms 10ms DC 10 1 0 5 10 15 20 25 10 0 TC=25 C TJ=175 C Single Pulse 10 -1 10 0 10 1 10 2 Qg, Total Gate Charge (nC) Figure 7. Gate Charge VDD t on V IN VGS RGEN G RL D VOUT td(on) VOUT 10% VDS, Drain-Source Voltage (V) Figure 8. Maximum Safe Operating Area toff tr 90% td(off) 90% 10% tf INVERTED 90% S VIN 50% 10% 50% PULSE WIDTH Figure 9. Switching Test Circuit Figure 10. Switching Waveforms r(t),Normalized Effective Transient Thermal Impedance 10 0 D=0.5 0.2 10 -1 0.1 0.05 0.02 0.01 Single Pulse PDM t1 t2 10 -2 1. RθJA (t)=r (t) * RθJA 2. RθJA=See Datasheet 3. TJM-TA = P* RθJC (t) 4. Duty Cycle, D=t1/t2 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 Square Wave Pulse Duration (sec) Figure 11. Normalized Thermal Transient Impedance Curve 4
CED6186 价格&库存

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