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CED75A3_08

CED75A3_08

  • 厂商:

    CET(华瑞)

  • 封装:

  • 描述:

    CED75A3_08 - N-Channel Enhancement Mode Field Effect Transistor - Chino-Excel Technology

  • 数据手册
  • 价格&库存
CED75A3_08 数据手册
N-Channel Enhancement Mode Field Effect Transistor FEATURES 25V, 60A, RDS(ON) = 9mΩ @VGS = 10V. RDS(ON) = 13mΩ @VGS = 4.5V. Super high dense cell design for extremely low RDS(ON). High power and current handing capability. Lead free product is acquired. TO-251 & TO-252 package. CED75A3/CEU75A3 D D G S CEU SERIES TO-252(D-PAK) G D G S CED SERIES TO-251(I-PAK) S ABSOLUTE MAXIMUM RATINGS Parameter Drain-Source Voltage Gate-Source Voltage Drain Current-Continuous Drain Current-Pulsed a Tc = 25 C unless otherwise noted Symbol Limit VDS VGS ID IDM PD EAS IAS TJ,Tstg 25 Units V V A A W W/ C mJ A C ±20 60 200 56 0.37 60 11 -55 to 175 Maximum Power Dissipation @ TC = 25 C - Derate above 25 C Single Pulsed Avalanche Energy d Single Pulsed Avalanche Current d Operating and Store Temperature Range Thermal Characteristics Parameter Thermal Resistance, Junction-to-Case Thermal Resistance, Junction-to-Ambient Symbol RθJC RθJA Limit 2.7 50 Units C/W C/W Specification and data are subject to change without notice . 1 Rev 3. 2008. Jan. http://www.cetsemi.com CED75A3/CEU75A3 Electrical Characteristics Parameter Off Characteristics Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current Gate Body Leakage Current, Forward Gate Body Leakage Current, Reverse On Characteristics b Gate Threshold Voltage Static Drain-Source On-Resistance Dynamic Characteristics c Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Switching Characteristics c Turn-On Delay Time Turn-On Rise Time Turn-Off Delay Time Turn-Off Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Drain-Source Diode Forward Current Drain-Source Diode Forward Voltage b td(on) tr td(off) tf Qg Qgs Qgd IS VSD VGS = 0V, IS = 20A 0.85 VDS = 15V, ID = 20A, VGS = 5V VDD = 15V, ID = 1A, VGS = 10V, RGEN = 6Ω 12 4 32 6 10 3.6 2.9 60 1.2 25 10 65 15 13 ns ns ns ns nC nC nC A V gFS Ciss Coss Crss VDS = 10V, ID = 15A VDS = 15V, VGS = 0V, f = 1.0 MHz 12 1180 270 145 S pF pF pF BVDSS IDSS IGSSF IGSSR VGS(th) RDS(on) VGS = 0V, ID = 250µA VDS = 25V, VGS = 0V VGS = 20V, VDS = 0V VGS = -20V, VDS = 0V VGS = VDS, ID = 250µA VGS = 10V, ID = 30A VGS = 4.5V, ID = 30A 1 7 10 25 1 100 -100 3 9 13 V µA Tc = 25 C unless otherwise noted Symbol Test Condition Min Typ Max Units nA nA V mΩ mΩ Drain-Source Diode Characteristics and Maximun Ratings Notes : a.Repetitive Rating : Pulse width limited by maximum junction temperature b.Pulse Test : Pulse Width < 300µs, Duty Cycle < 2%. c.Guaranteed by design, not subject to production testing. d.L = 1mH, IAS = 11A, VDD = 50V, RG = 25Ω, Starting TJ = 25 C 2 CED75A3/CEU75A3 100 VGS=10,8,6,4V 100 ID, Drain Current (A) 60 ID, Drain Current (A) 80 80 60 VGS=3V 40 40 25 C 20 TJ=125 C -55 C 3 4 5 20 0 0 1 2 3 4 0 0 1 2 VDS, Drain-to-Source Voltage (V) Figure 1. Output Characteristics 1800 1500 1200 900 600 300 0 0 5 10 Coss Crss 15 20 25 Ciss 2.2 1.9 1.6 1.3 1.0 0.7 0.4 -100 VGS, Gate-to-Source Voltage (V) Figure 2. Transfer Characteristics RDS(ON), Normalized RDS(ON), On-Resistance(Ohms) ID=30A VGS=10V C, Capacitance (pF) -50 0 50 100 150 200 VDS, Drain-to-Source Voltage (V) Figure 3. Capacitance 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 -50 TJ, Junction Temperature( C) Figure 4. On-Resistance Variation with Temperature VGS=0V 2 VTH, Normalized Gate-Source Threshold Voltage VDS=VGS ID=250µA IS, Source-drain current (A) 10 10 1 10 -25 0 25 50 75 100 125 150 0 0.4 0.6 0.8 1.0 1.2 1.4 TJ, Junction Temperature( C) Figure 5. Gate Threshold Variation with Temperature VSD, Body Diode Forward Voltage (V) Figure 6. Body Diode Forward Voltage Variation with Source Current 3 CED75A3/CEU75A3 VGS, Gate to Source Voltage (V) 10 8 6 4 2 0 VDS=15V ID=20A 10 3 RDS(ON)Limit ID, Drain Current (A) 10 2 10ms 100ms 1ms DC 10 1 0 4 8 12 16 20 10 0 TC=25 C TJ=175 C Single Pulse 10 -1 10 0 10 1 10 2 Qg, Total Gate Charge (nC) Figure 7. Gate Charge VDD t on V IN VGS RGEN G RL D VOUT td(on) VOUT 10% VDS, Drain-Source Voltage (V) Figure 8. Maximum Safe Operating Area toff tr 90% td(off) 90% 10% tf INVERTED 90% S VIN 50% 10% 50% PULSE WIDTH Figure 9. Switching Test Circuit Figure 10. Switching Waveforms r(t),Normalized Effective Transient Thermal Impedance 10 0 D=0.5 0.2 10 -1 0.1 0.05 0.02 0.01 Single Pulse PDM t1 t2 10 -2 1. RθJC (t)=r (t) * RθJC 2. RθJC=See Datasheet 3. TJM-TC = P* RθJC (t) 4. Duty Cycle, D=t1/t2 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 Square Wave Pulse Duration (sec) Figure 11. Normalized Thermal Transient Impedance Curve 4
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