N-Channel Enhancement Mode Field Effect Transistor FEATURES
Type CEP12N5 CEB12N5 CEF12N5 VDSS 500V 500V 500V RDS(ON) 0.54Ω 0.54Ω 0.54Ω ID @VGS 10V 10V 10V
CEP12N5/CEB12N5 CEF12N5
PRELIMINARY
12A
12A 12A d
Super high dense cell design for extremely low RDS(ON). High power and current handing capability. Lead free product is acquired.
D
D
G
G D S G
CEP SERIES TO-220
S CEB SERIES TO-263(DD-PAK)
G
D
S
CEF SERIES TO-220F
S
ABSOLUTE MAXIMUM RATINGS
Parameter Drain-Source Voltage Gate-Source Voltage Drain Current-Continuous Drain Current-Pulsed
a
Tc = 25 C unless otherwise noted Limit Symbol TO-220/263 VDS VGS ID IDM PD TJ,Tstg
e
TO-220F
Units V V
500
±30
12 48 166 1.3 -55 to 150 12 48 50 0.4
d d
A A W W/ C C
Maximum Power Dissipation @ TC = 25 C - Derate above 25 C Operating and Store Temperature Range
Thermal Characteristics
Parameter Thermal Resistance, Junction-to-Case Thermal Resistance, Junction-to-Ambient Symbol RθJC RθJA 0.75 62.5 Limit 2.5 65 Units C/W C/W
This is preliminary information on a new product in development now . Details are subject to change without notice . 1
Rev 1. 2008.Oct. http://www.cetsemi.com
Electrical Characteristics
Parameter Off Characteristics Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current Gate Body Leakage Current, Forward Gate Body Leakage Current, Reverse On Characteristics b Gate Threshold Voltage Static Drain-Source On-Resistance Dynamic Characteristics c Input Capacitance Output Capacitance Reverse Transfer Capacitance Switching Characteristics c Turn-On Delay Time Turn-On Rise Time Turn-Off Delay Time Turn-Off Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Drain-Source Diode Forward Current Drain-Source Diode Forward Voltage
b
CEP12N5/CEB12N5 CEF12N5
Tc = 25 C unless otherwise noted Symbol BVDSS IDSS IGSSF IGSSR VGS(th) RDS(on) Test Condition VGS = 0V, ID = 250µA VDS =500V, VGS = 0V VGS = 30V, VDS = 0V VGS = -30V, VDS = 0V VGS = VDS, ID = 250µA VGS = 10V, ID = 6A 2 0.45 Min 500 1 100 -100 4 0.54 Typ Max Units V
µA
nA nA V Ω
Ciss Coss Crss td(on) tr td(off) tf Qg Qgs Qgd ISf VSDg
VDS = 25V, VGS = 0V, f = 1.0 MHz
1745 205 20 31.6 25.6 146.3 32 44.1 7.3 17.3 12 63.2 51.2 292.6 64 58.7
pF pF pF ns ns ns ns nC nC nC A V
VDD = 250V, ID = 12A, VGS = 10V, RGEN = 25Ω
VDS = 400V,ID = 12A, VGS = 10V
Drain-Source Diode Characteristics and Maximun Ratings VGS = 0V, IS = 12A 1.4
Notes : a.Repetitive Rating : Pulse width limited by maximum junction temperature . b.Pulse Test : Pulse Width < 300µs, Duty Cycle < 2% . c.Guaranteed by design, not subject to production testing. d.Limited only by maximum temperature allowed . e.Pulse width limited by safe operating area . f.Full package IS(max) =6A . g.Full package VSD test condition IS =6A . h.L = 15mH, IAS = 8.5A, VDD = 50V, RG = 25Ω, Starting TJ = 25 C
2
CEP12N5/CEB12N5 CEF12N5
12 10 8 6 4 2 0 VGS=10,9,8,7,6,5V 14 12
ID, Drain Current (A)
ID, Drain Current (A)
10 8 6 4 2 0 TJ=125C 0 1.5 3.0 4.5
25 C
VGS=4V
-55 C 6.0 7.5
0
5
10
15
20
25
30
VDS, Drain-to-Source Voltage (V) Figure 1. Output Characteristics
2400 2000 1600 1200 800 400 0 Coss Crss 0 5 10 15 20 25 Ciss 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -100
VGS, Gate-to-Source Voltage (V) Figure 2. Transfer Characteristics
ID=12A VGS=10V
RDS(ON), Normalized RDS(ON), On-Resistance(Ohms)
C, Capacitance (pF)
-50
0
50
100
150
200
VDS, Drain-to-Source Voltage (V) Figure 3. Capacitance
1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 -50 VDS=VGS
TJ, Junction Temperature( C) Figure 4. On-Resistance Variation with Temperature
10
1
VTH, Normalized Gate-Source Threshold Voltage
IS, Source-drain current (A)
ID=250µA
VGS=0V
10
0
10 -25 0 25 50 75 100 125 150
-1
0.4
0.6
0.8
1.0
1.2
1.4
1.6
TJ, Junction Temperature( C) Figure 5. Gate Threshold Variation with Temperature
VSD, Body Diode Forward Voltage (V) Figure 6. Body Diode Forward Voltage Variation with Source Current
3
CEP12N5/CEB12N5 CEF12N5
VGS, Gate to Source Voltage (V)
10 8 6 4 2 0 VDS=400V ID=12A 10
2
RDS(ON)Limit 100ms
ID, Drain Current (A)
10
1
1ms 10ms DC
10
0
0
15
30
45
60
10
-1
TC=25 C TJ=150 C Single Pulse 10
0
10
1
10
2
10
3
Qg, Total Gate Charge (nC) Figure 7. Gate Charge VDD t on V IN VGS RGEN G RL D VOUT td(on) VOUT
10%
VDS, Drain-Source Voltage (V) Figure 8. Maximum Safe Operating Area
toff tr
90%
td(off)
90% 10%
tf
INVERTED
90%
S
VIN
50% 10%
50%
PULSE WIDTH
Figure 9. Switching Test Circuit
Figure 10. Switching Waveforms
r(t),Normalized Effective Transient Thermal Impedance
10
0
D=0.5
0.2
10
-1
0.1 0.05 0.02 0.01 Single Pulse
PDM t1 t2
10
-2
1. RθJC (t)=r (t) * RθJC 2. RθJC=See Datasheet 3. TJM-TC = P* RθJC (t) 4. Duty Cycle, D=t1/t2
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
1
Square Wave Pulse Duration (msec) Figure 11. Normalized Thermal Transient Impedance Curve
4