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CEP16N10L

CEP16N10L

  • 厂商:

    CET(华瑞)

  • 封装:

  • 描述:

    CEP16N10L - N-Channel Enhancement Mode Field Effect Transistor - Chino-Excel Technology

  • 数据手册
  • 价格&库存
CEP16N10L 数据手册
N-Channel Enhancement Mode Field Effect Transistor FEATURES 100V, 15.2A, RDS(ON) = 115mΩ @VGS = 10V. RDS(ON) = 125mΩ @VGS = 5V. Super high dense cell design for extremely low RDS(ON). High power and current handing capability. Lead free product is acquired. TO-220 & TO-263 package. CEP16N10L/CEB16N10L PRELIMINARY D D G G D S S CEB SERIES TO-263(DD-PAK) G CEP SERIES TO-220 S ABSOLUTE MAXIMUM RATINGS Parameter Drain-Source Voltage Gate-Source Voltage Drain Current-Continuous Drain Current-Pulsed a Tc = 25 C unless otherwise noted Symbol Limit VDS VGS ID IDM PD TJ,Tstg 100 Units V V A A W W/ C C ±20 15.2 60 60 0.48 -55 to 175 Maximum Power Dissipation @ TC = 25 C - Derate above 25 C Operating and Store Temperature Range Thermal Characteristics Parameter Thermal Resistance, Junction-to-Case Thermal Resistance, Junction-to-Ambient Symbol RθJC RθJA Limit 2.5 50 Units C/W C/W Details are subject to change without notice . 1 Rev 1. 2010.Jan. http://www.cetsemi.com CEP16N10L/CEB16N10L Electrical Characteristics Parameter Off Characteristics Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current Gate Body Leakage Current, Forward Gate Body Leakage Current, Reverse On Characteristics b Gate Threshold Voltage Static Drain-Source On-Resistance Forward Transconductance Dynamic Characteristics c Input Capacitance Output Capacitance Reverse Transfer Capacitance Switching Characteristics c Turn-On Delay Time Turn-On Rise Time Turn-Off Delay Time Turn-Off Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Drain-Source Diode Forward Current Drain-Source Diode Forward Voltage b td(on) tr td(off) tf Qg Qgs Qgd IS VSD VGS = 0V, IS = 15.2A VDS = 80V, ID = 15A, VGS = 10V VDD =50V, ID = 15A, VGS = 10V, RGEN = 25Ω 10 2.8 73 7.5 16 2 3 15.2 1.5 30 7 150 15 25 ns ns ns ns nC nC nC A V Ciss Coss Crss VDS = 25V, VGS = 0V, f = 1.0 MHz 640 110 30 pF pF pF VGS(th) RDS(on) gFS VGS = VDS, ID = 250µA VGS = 10V, ID = 7A VGS = 5V, ID = 5.5A VDS = 10V, ID = 7A 1 95 100 5 3 115 125 V mΩ mΩ S BVDSS IDSS IGSSF IGSSR VGS = 0V, ID = 250µA VDS = 100V, VGS = 0V VGS = 20V, VDS = 0V VGS = -20V, VDS = 0V 100 1 100 -100 V µA Tc = 25 C unless otherwise noted Symbol Test Condition Min Typ Max Units nA nA Drain-Source Diode Characteristics and Maximun Ratings Notes : a.Repetitive Rating : Pulse width limited by maximum junction temperature b.Pulse Test : Pulse Width < 300µs, Duty Cycle < 2%. c.Guaranteed by design, not subject to production testing. d. L=0.5mH, IAS=13.3A, VDD=25V, RG=25Ω, Starting TJ=25 C 2 CEP16N10L/CEB16N10L 20 VGS=10,8,6,5V 20 25 C ID, Drain Current (A) ID, Drain Current (A) 15 VGS=4.0V 15 10 10 5 5 TJ=125 C -55 C 2.0 3.0 4.0 5.0 0 0 1 2 3 4 5 0 0.0 1.0 VDS, Drain-to-Source Voltage (V) Figure 1. Output Characteristics 800 700 Ciss 2.2 1.9 1.6 1.3 1.0 0.7 0.4 -100 VGS, Gate-to-Source Voltage (V) Figure 2. Transfer Characteristics 600 500 400 300 200 100 0 0 5 10 Coss Crss 15 20 25 RDS(ON), Normalized RDS(ON), On-Resistance(Ohms) ID=7A VGS=10V C, Capacitance (pF) -50 0 50 100 150 200 VDS, Drain-to-Source Voltage (V) Figure 3. Capacitance 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 -50 VDS=VGS TJ, Junction Temperature( C) Figure 4. On-Resistance Variation with Temperature IS, Source-drain current (A) VGS=0V 10 1 VTH, Normalized Gate-Source Threshold Voltage ID=250µA 10 0 -25 0 25 50 75 100 125 150 10 -1 0.2 0.6 1.0 1.4 1.8 2.2 TJ, Junction Temperature( C) Figure 5. Gate Threshold Variation with Temperature VSD, Body Diode Forward Voltage (V) Figure 6. Body Diode Forward Voltage Variation with Source Current 3 CEP16N10L/CEB16N10L VGS, Gate to Source Voltage (V) 10 8 6 4 2 0 VDS=80V ID=15A 10 2 RDS(ON)Limit ID, Drain Current (A) 100ms 10 1 1ms 10ms DC 10 0 0 3 6 9 12 15 18 10 -1 TC=25 C TJ=175 C Single Pulse 10 -1 10 0 10 1 10 2 Qg, Total Gate Charge (nC) Figure 7. Gate Charge VDD t on V IN VGS RGEN G RL D VOUT td(on) VOUT 10% VDS, Drain-Source Voltage (V) Figure 8. Maximum Safe Operating Area toff tr 90% td(off) 90% 10% tf INVERTED 90% S VIN 50% 10% 50% PULSE WIDTH Figure 9. Switching Test Circuit Figure 10. Switching Waveforms r(t),Normalized Effective Transient Thermal Impedance 10 0 D=0.5 0.2 10 -1 0.1 0.05 0.02 0.01 Single Pulse PDM t1 t2 10 -2 1. RθJC (t)=r (t) * RθJC 2. RθJC=See Datasheet 3. TJM-TC = P* RθJC (t) 4. Duty Cycle, D=t1/t2 10 -2 10 -1 10 0 10 1 10 2 10 3 10 4 Square Wave Pulse Duration (msec) Figure 11. Normalized Thermal Transient Impedance Curve 4
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